Commits

Breadcrumbs

History for

onmain

User selector

All users

Datepicker

All time

Commit History

Commits on Dec 14, 2021

• [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.

  Show description for 3f1c403
  topperc

  committed
  3f1c403

  Copy full SHA for 3f1c403

Commits on Nov 17, 2021

• [CodeGen] Update LiveIntervals in TargetInstrInfo::convertToThreeAddress

  Show description for 3264e95
  jayfoad

  committed
  3264e95

  Copy full SHA for 3264e95

Commits on Oct 27, 2021

• [amdgpu] Handle the case where there is no scavenged register.

  Show description for e6a4ba3
  darkbuck

  committed
  e6a4ba3

  Copy full SHA for e6a4ba3

Commits on Sep 23, 2021

• [TII] Remove the MFI argument to convertToThreeAddress. NFC.

  Show description for 6cef28e
  jayfoad

  committed
  6cef28e

  Copy full SHA for 6cef28e

Commits on Sep 3, 2021

• [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0.

  Show description for 75620fa
  topperc

  committed
  75620fa

  Copy full SHA for 75620fa

Commits on Aug 9, 2021

• [RISCV] Introduce a RISCV CondCode enum instead of using ISD:SET* in MIR. NFC

  Show description for 88bc29f
  topperc

  committed
  88bc29f

  Copy full SHA for 88bc29f

Commits on Jul 23, 2021

• [RISCV] Add FrameSetup/FrameDestroy flag to prologue/epilog instructions.

  Show description for 4b2dd31
  Hsiangkai

  committed
  4b2dd31

  Copy full SHA for 4b2dd31

Commits on Jun 8, 2021

• Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

  Show description for 8b4c80d
  topperc

  committed
  8b4c80d

  Copy full SHA for 8b4c80d

Commits on Jun 3, 2021

• [RISCV] Reserve an emergency spill slot for any RVV spills

  Show description for 8790e85
  frasercrmck

  committed
  8790e85

  Copy full SHA for 8790e85

Commits on May 14, 2021

• [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().

  Show description for b41e130
  Hsiangkai

  committed
  b41e130

  Copy full SHA for b41e130

Commits on Mar 18, 2021

• [RISCV] Spilling for Zvlsseg registers.

  Show description for aa8d33a
  Hsiangkai

  committed
  aa8d33a

  Copy full SHA for aa8d33a

Commits on Mar 16, 2021

• [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'

  Show description for 6ab8927
  MaskRay

  committed
  6ab8927

  Copy full SHA for 6ab8927

Commits on Mar 9, 2021

• [RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert.

  Show description for 478317f
  topperc

  committed
  478317f

  Copy full SHA for 478317f

Commits on Feb 17, 2021

• [RISCV] Frame handling for RISC-V V extension.

  Show description for 5a31a67
  Hsiangkai

  committed
  5a31a67

  Copy full SHA for 5a31a67

Commits on Feb 8, 2021

• [RISCV] Make scalable vector FMA commutable for register allocation.

  Show description for b7b4f4c
  topperc

  committed
  b7b4f4c

  Copy full SHA for b7b4f4c

Commits on Jan 27, 2021

• [RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC

  Show description for 58aa049
  topperc

  committed
  58aa049

  Copy full SHA for 58aa049

Commits on Nov 12, 2020

• [RISCV] Don't include CodeGen layer files in MC layer

  Show description for 0add5f9
  topperc

  committed
  0add5f9

  Copy full SHA for 0add5f9

Commits on Sep 21, 2020

• [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()

  Show description for 8cf6778
  arichardson

  committed
  8cf6778

  Copy full SHA for 8cf6778

Commits on Jul 31, 2020

• Upgrade MC to v0.9.

  Show description for 47a4a27
  Hsiangkai

  committed
  47a4a27

  Copy full SHA for 47a4a27

Commits on Jun 27, 2020

• [RISCV] Assemble/Disassemble v-ext instructions.

  Show description for 66da87d
  Hsiangkai

  committed
  66da87d

  Copy full SHA for 66da87d

Commits on Feb 3, 2020

• [NFC] unsigned->Register in storeRegTo/loadRegFromStack

  Show description for 5c8ba50
  

  Simon Moll

  committed
  5c8ba50

  Copy full SHA for 5c8ba50

Commits on Dec 19, 2019

• [RISCV] Enable the machine outliner for RISC-V

  Show description for a116f28
  lewis-revill

  committed
  a116f28

  Copy full SHA for a116f28

Commits on Dec 9, 2019

• [RISCV] Machine Operand Flag Serialization

  Show description for c20930a
  lenary

  committed
  c20930a

  Copy full SHA for c20930a

Commits on Nov 11, 2019

• Use MCRegister in copyPhysReg

  arsenm

  committed
  e6c9a9a

  Copy full SHA for e6c9a9a

Commits on Nov 5, 2019

• [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook

  Show description for 0d47c7a
  luismarques

  committed
  0d47c7a

  Copy full SHA for 0d47c7a

Commits on Oct 16, 2019

• [RISCV] Add MachineInstr immediate verification

  Show description for 1893f9a
  luismarques

  committed
  1893f9a

  Copy full SHA for 1893f9a

Commits on Sep 13, 2019

• [RISCV] Support stack offset exceed 32-bit for RV64

  Show description for a49a16d
  ShivaChen

  committed
  a49a16d

  Copy full SHA for a49a16d

• Revert "[RISCV] Support stack offset exceed 32-bit for RV64"

  Show description for ea530ba
  ShivaChen

  committed
  ea530ba

  Copy full SHA for ea530ba

• [RISCV] Support stack offset exceed 32-bit for RV64

  Show description for eaa230f
  ShivaChen

  committed
  eaa230f

  Copy full SHA for eaa230f

Commits on Aug 16, 2019

• [RISCV] Convert registers from unsigned to Register

  Show description for fa06e95
  luismarques

  committed
  fa06e95

  Copy full SHA for fa06e95

Commits on Jan 25, 2019

• Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

  Show description for 05a6064
  

  Ana Pazos

  committed
  05a6064

  Copy full SHA for 05a6064

Commits on Jan 24, 2019

• Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"

  Show description for 5c0521a
  

  Ana Pazos

  committed
  5c0521a

  Copy full SHA for 5c0521a

• [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

  Show description for c54abc5
  

  Ana Pazos

  committed
  c54abc5

  Copy full SHA for c54abc5

Commits on Jan 19, 2019

• Update the file headers across all of the LLVM projects in the monorepo

  Show description for 2946cd7
  chandlerc

  committed
  2946cd7

  Copy full SHA for 2946cd7

Commits on Apr 26, 2018

• [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

  Show description for fda6037
  asb

  committed
  fda6037

  Copy full SHA for fda6037

Pagination

Previous

Next