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luismarquesluismarques
committedAug 16, 2019
[RISCV] Convert registers from unsigned to Register
Only in public interfaces that have not yet been converted should there remain registers with unsigned type. Differential Revision: https://reviews.llvm.org/D66252 llvm-svn: 369114
·
llvmorg-15-init2020.06-alpha
1 parent 4c78b78 commit fa06e95

11 files changed

+82
-78
lines changed
 

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

+33-32
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "llvm/ADT/STLExtras.h"
1717
#include "llvm/ADT/SmallVector.h"
1818
#include "llvm/ADT/StringSwitch.h"
19+
#include "llvm/CodeGen/Register.h"
1920
#include "llvm/MC/MCAssembler.h"
2021
#include "llvm/MC/MCContext.h"
2122
#include "llvm/MC/MCExpr.h"
@@ -79,7 +80,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
7980

8081
// Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that
8182
// synthesize the desired immedate value into the destination register.
82-
void emitLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out);
83+
void emitLoadImm(Register DestReg, int64_t Value, MCStreamer &Out);
8384

8485
// Helper to emit a combination of AUIPC and SecondOpcode. Used to implement
8586
// helpers such as emitLoadLocalAddress and emitLoadAddress.
@@ -194,7 +195,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
194195
/// instruction
195196
struct RISCVOperand : public MCParsedAsmOperand {
196197

197-
enum KindTy {
198+
enum class KindTy {
198199
Token,
199200
Register,
200201
Immediate,
@@ -204,7 +205,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
204205
bool IsRV64;
205206

206207
struct RegOp {
207-
unsigned RegNum;
208+
Register RegNum;
208209
};
209210

210211
struct ImmOp {
@@ -236,26 +237,26 @@ struct RISCVOperand : public MCParsedAsmOperand {
236237
StartLoc = o.StartLoc;
237238
EndLoc = o.EndLoc;
238239
switch (Kind) {
239-
case Register:
240+
case KindTy::Register:
240241
Reg = o.Reg;
241242
break;
242-
case Immediate:
243+
case KindTy::Immediate:
243244
Imm = o.Imm;
244245
break;
245-
case Token:
246+
case KindTy::Token:
246247
Tok = o.Tok;
247248
break;
248-
case SystemRegister:
249+
case KindTy::SystemRegister:
249250
SysReg = o.SysReg;
250251
break;
251252
}
252253
}
253254

254-
bool isToken() const override { return Kind == Token; }
255-
bool isReg() const override { return Kind == Register; }
256-
bool isImm() const override { return Kind == Immediate; }
255+
bool isToken() const override { return Kind == KindTy::Token; }
256+
bool isReg() const override { return Kind == KindTy::Register; }
257+
bool isImm() const override { return Kind == KindTy::Immediate; }
257258
bool isMem() const override { return false; }
258-
bool isSystemRegister() const { return Kind == SystemRegister; }
259+
bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
259260

260261
static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
261262
RISCVMCExpr::VariantKind &VK) {
@@ -593,46 +594,46 @@ struct RISCVOperand : public MCParsedAsmOperand {
593594
bool isRV64() const { return IsRV64; }
594595

595596
unsigned getReg() const override {
596-
assert(Kind == Register && "Invalid type access!");
597-
return Reg.RegNum;
597+
assert(Kind == KindTy::Register && "Invalid type access!");
598+
return Reg.RegNum.id();
598599
}
599600

600601
StringRef getSysReg() const {
601-
assert(Kind == SystemRegister && "Invalid access!");
602+
assert(Kind == KindTy::SystemRegister && "Invalid access!");
602603
return StringRef(SysReg.Data, SysReg.Length);
603604
}
604605

605606
const MCExpr *getImm() const {
606-
assert(Kind == Immediate && "Invalid type access!");
607+
assert(Kind == KindTy::Immediate && "Invalid type access!");
607608
return Imm.Val;
608609
}
609610

610611
StringRef getToken() const {
611-
assert(Kind == Token && "Invalid type access!");
612+
assert(Kind == KindTy::Token && "Invalid type access!");
612613
return Tok;
613614
}
614615

615616
void print(raw_ostream &OS) const override {
616617
switch (Kind) {
617-
case Immediate:
618+
case KindTy::Immediate:
618619
OS << *getImm();
619620
break;
620-
case Register:
621+
case KindTy::Register:
621622
OS << "<register x";
622623
OS << getReg() << ">";
623624
break;
624-
case Token:
625+
case KindTy::Token:
625626
OS << "'" << getToken() << "'";
626627
break;
627-
case SystemRegister:
628+
case KindTy::SystemRegister:
628629
OS << "<sysreg: " << getSysReg() << '>';
629630
break;
630631
}
631632
}
632633

633634
static std::unique_ptr<RISCVOperand> createToken(StringRef Str, SMLoc S,
634635
bool IsRV64) {
635-
auto Op = std::make_unique<RISCVOperand>(Token);
636+
auto Op = std::make_unique<RISCVOperand>(KindTy::Token);
636637
Op->Tok = Str;
637638
Op->StartLoc = S;
638639
Op->EndLoc = S;
@@ -642,7 +643,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
642643

643644
static std::unique_ptr<RISCVOperand> createReg(unsigned RegNo, SMLoc S,
644645
SMLoc E, bool IsRV64) {
645-
auto Op = std::make_unique<RISCVOperand>(Register);
646+
auto Op = std::make_unique<RISCVOperand>(KindTy::Register);
646647
Op->Reg.RegNum = RegNo;
647648
Op->StartLoc = S;
648649
Op->EndLoc = E;
@@ -652,7 +653,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
652653

653654
static std::unique_ptr<RISCVOperand> createImm(const MCExpr *Val, SMLoc S,
654655
SMLoc E, bool IsRV64) {
655-
auto Op = std::make_unique<RISCVOperand>(Immediate);
656+
auto Op = std::make_unique<RISCVOperand>(KindTy::Immediate);
656657
Op->Imm.Val = Val;
657658
Op->StartLoc = S;
658659
Op->EndLoc = E;
@@ -662,7 +663,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
662663

663664
static std::unique_ptr<RISCVOperand>
664665
createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) {
665-
auto Op = std::make_unique<RISCVOperand>(SystemRegister);
666+
auto Op = std::make_unique<RISCVOperand>(KindTy::SystemRegister);
666667
Op->SysReg.Data = Str.data();
667668
Op->SysReg.Length = Str.size();
668669
Op->SysReg.Encoding = Encoding;
@@ -743,7 +744,7 @@ struct RISCVOperand : public MCParsedAsmOperand {
743744
// Return the matching FPR64 register for the given FPR32.
744745
// FIXME: Ideally this function could be removed in favour of using
745746
// information from TableGen.
746-
unsigned convertFPR32ToFPR64(unsigned Reg) {
747+
Register convertFPR32ToFPR64(Register Reg) {
747748
switch (Reg) {
748749
default:
749750
llvm_unreachable("Not a recognised FPR32 register");
@@ -788,7 +789,7 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
788789
if (!Op.isReg())
789790
return Match_InvalidOperand;
790791

791-
unsigned Reg = Op.getReg();
792+
Register Reg = Op.getReg();
792793
bool IsRegFPR32 =
793794
RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg);
794795
bool IsRegFPR32C =
@@ -978,7 +979,7 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
978979
// alternative ABI names), setting RegNo to the matching register. Upon
979980
// failure, returns true and sets RegNo to 0. If IsRV32E then registers
980981
// x16-x31 will be rejected.
981-
static bool matchRegisterNameHelper(bool IsRV32E, unsigned &RegNo,
982+
static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo,
982983
StringRef Name) {
983984
RegNo = MatchRegisterName(Name);
984985
if (RegNo == 0)
@@ -996,7 +997,7 @@ bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
996997
RegNo = 0;
997998
StringRef Name = getLexer().getTok().getIdentifier();
998999

999-
if (matchRegisterNameHelper(isRV32E(), RegNo, Name))
1000+
if (matchRegisterNameHelper(isRV32E(), (Register&)RegNo, Name))
10001001
return Error(StartLoc, "invalid register name");
10011002

10021003
getParser().Lex(); // Eat identifier token.
@@ -1028,7 +1029,7 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
10281029
return MatchOperand_NoMatch;
10291030
case AsmToken::Identifier:
10301031
StringRef Name = getLexer().getTok().getIdentifier();
1031-
unsigned RegNo;
1032+
Register RegNo;
10321033
matchRegisterNameHelper(isRV32E(), RegNo, Name);
10331034

10341035
if (RegNo == 0) {
@@ -1618,12 +1619,12 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
16181619
S.EmitInstruction((Res ? CInst : Inst), getSTI());
16191620
}
16201621

1621-
void RISCVAsmParser::emitLoadImm(unsigned DestReg, int64_t Value,
1622+
void RISCVAsmParser::emitLoadImm(Register DestReg, int64_t Value,
16221623
MCStreamer &Out) {
16231624
RISCVMatInt::InstSeq Seq;
16241625
RISCVMatInt::generateInstSeq(Value, isRV64(), Seq);
16251626

1626-
unsigned SrcReg = RISCV::X0;
1627+
Register SrcReg = RISCV::X0;
16271628
for (RISCVMatInt::Inst &Inst : Seq) {
16281629
if (Inst.Opc == RISCV::LUI) {
16291630
emitToStreamer(
@@ -1777,7 +1778,7 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
17771778
default:
17781779
break;
17791780
case RISCV::PseudoLI: {
1780-
unsigned Reg = Inst.getOperand(0).getReg();
1781+
Register Reg = Inst.getOperand(0).getReg();
17811782
const MCOperand &Op1 = Inst.getOperand(1);
17821783
if (Op1.isExpr()) {
17831784
// We must have li reg, %lo(sym) or li reg, %pcrel_lo(sym) or similar.

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

+10-9
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "MCTargetDesc/RISCVMCTargetDesc.h"
1414
#include "TargetInfo/RISCVTargetInfo.h"
1515
#include "Utils/RISCVBaseInfo.h"
16+
#include "llvm/CodeGen/Register.h"
1617
#include "llvm/MC/MCContext.h"
1718
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
1819
#include "llvm/MC/MCFixedLenDisassembler.h"
@@ -56,7 +57,7 @@ extern "C" void LLVMInitializeRISCVDisassembler() {
5657
createRISCVDisassembler);
5758
}
5859

59-
static const unsigned GPRDecoderTable[] = {
60+
static const Register GPRDecoderTable[] = {
6061
RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
6162
RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
6263
RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
@@ -82,12 +83,12 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
8283
// We must define our own mapping from RegNo to register identifier.
8384
// Accessing index RegNo in the register class will work in the case that
8485
// registers were added in ascending order, but not in general.
85-
unsigned Reg = GPRDecoderTable[RegNo];
86+
Register Reg = GPRDecoderTable[RegNo];
8687
Inst.addOperand(MCOperand::createReg(Reg));
8788
return MCDisassembler::Success;
8889
}
8990

90-
static const unsigned FPR32DecoderTable[] = {
91+
static const Register FPR32DecoderTable[] = {
9192
RISCV::F0_32, RISCV::F1_32, RISCV::F2_32, RISCV::F3_32,
9293
RISCV::F4_32, RISCV::F5_32, RISCV::F6_32, RISCV::F7_32,
9394
RISCV::F8_32, RISCV::F9_32, RISCV::F10_32, RISCV::F11_32,
@@ -107,7 +108,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
107108
// We must define our own mapping from RegNo to register identifier.
108109
// Accessing index RegNo in the register class will work in the case that
109110
// registers were added in ascending order, but not in general.
110-
unsigned Reg = FPR32DecoderTable[RegNo];
111+
Register Reg = FPR32DecoderTable[RegNo];
111112
Inst.addOperand(MCOperand::createReg(Reg));
112113
return MCDisassembler::Success;
113114
}
@@ -118,12 +119,12 @@ static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
118119
if (RegNo > 8) {
119120
return MCDisassembler::Fail;
120121
}
121-
unsigned Reg = FPR32DecoderTable[RegNo + 8];
122+
Register Reg = FPR32DecoderTable[RegNo + 8];
122123
Inst.addOperand(MCOperand::createReg(Reg));
123124
return MCDisassembler::Success;
124125
}
125126

126-
static const unsigned FPR64DecoderTable[] = {
127+
static const Register FPR64DecoderTable[] = {
127128
RISCV::F0_64, RISCV::F1_64, RISCV::F2_64, RISCV::F3_64,
128129
RISCV::F4_64, RISCV::F5_64, RISCV::F6_64, RISCV::F7_64,
129130
RISCV::F8_64, RISCV::F9_64, RISCV::F10_64, RISCV::F11_64,
@@ -143,7 +144,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
143144
// We must define our own mapping from RegNo to register identifier.
144145
// Accessing index RegNo in the register class will work in the case that
145146
// registers were added in ascending order, but not in general.
146-
unsigned Reg = FPR64DecoderTable[RegNo];
147+
Register Reg = FPR64DecoderTable[RegNo];
147148
Inst.addOperand(MCOperand::createReg(Reg));
148149
return MCDisassembler::Success;
149150
}
@@ -154,7 +155,7 @@ static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
154155
if (RegNo > 8) {
155156
return MCDisassembler::Fail;
156157
}
157-
unsigned Reg = FPR64DecoderTable[RegNo + 8];
158+
Register Reg = FPR64DecoderTable[RegNo + 8];
158159
Inst.addOperand(MCOperand::createReg(Reg));
159160
return MCDisassembler::Success;
160161
}
@@ -185,7 +186,7 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185186
if (RegNo > 8)
186187
return MCDisassembler::Fail;
187188

188-
unsigned Reg = GPRDecoderTable[RegNo + 8];
189+
Register Reg = GPRDecoderTable[RegNo + 8];
189190
Inst.addOperand(MCOperand::createReg(Reg));
190191
return MCDisassembler::Success;
191192
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "MCTargetDesc/RISCVMCTargetDesc.h"
1616
#include "Utils/RISCVBaseInfo.h"
1717
#include "llvm/ADT/Statistic.h"
18+
#include "llvm/CodeGen/Register.h"
1819
#include "llvm/MC/MCAsmInfo.h"
1920
#include "llvm/MC/MCCodeEmitter.h"
2021
#include "llvm/MC/MCContext.h"
@@ -100,7 +101,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
100101
const MCSubtargetInfo &STI) const {
101102
MCInst TmpInst;
102103
MCOperand Func;
103-
unsigned Ra;
104+
Register Ra;
104105
if (MI.getOpcode() == RISCV::PseudoTAIL) {
105106
Func = MI.getOperand(0);
106107
Ra = RISCV::X6;

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "RISCVTargetStreamer.h"
1818
#include "TargetInfo/RISCVTargetInfo.h"
1919
#include "llvm/ADT/STLExtras.h"
20+
#include "llvm/CodeGen/Register.h"
2021
#include "llvm/MC/MCAsmInfo.h"
2122
#include "llvm/MC/MCInstrInfo.h"
2223
#include "llvm/MC/MCRegisterInfo.h"
@@ -52,7 +53,7 @@ static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
5253
const Triple &TT) {
5354
MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
5455

55-
unsigned SP = MRI.getDwarfRegNum(RISCV::X2, true);
56+
Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
5657
MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
5758
MAI->addInitialFrameState(Inst);
5859

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -271,9 +271,9 @@ static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
271271
}
272272

273273
static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL,
274-
MachineBasicBlock *MBB, unsigned DestReg,
275-
unsigned OldValReg, unsigned NewValReg,
276-
unsigned MaskReg, unsigned ScratchReg) {
274+
MachineBasicBlock *MBB, Register DestReg,
275+
Register OldValReg, Register NewValReg,
276+
Register MaskReg, Register ScratchReg) {
277277
assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
278278
assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
279279
assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique");
@@ -394,8 +394,8 @@ bool RISCVExpandPseudo::expandAtomicBinOp(
394394
}
395395

396396
static void insertSext(const RISCVInstrInfo *TII, DebugLoc DL,
397-
MachineBasicBlock *MBB, unsigned ValReg,
398-
unsigned ShamtReg) {
397+
MachineBasicBlock *MBB, Register ValReg,
398+
Register ShamtReg) {
399399
BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
400400
.addReg(ValReg)
401401
.addReg(ShamtReg);

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