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Commits on Jan 27, 2022

• [RISCV] fix dead code

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  Xinlong-Wu

  committed
  6a4d3f3

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Commits on Jan 24, 2022

• [RISCV] Initially support the K-extension instructions on the LLVM MC layer

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  Xinlong-Wu

  committed
  e29d8fb

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Commits on Dec 14, 2021

• [RISCV] Support named opcodes in .insn directive.

  Show description for 10a7198
  

  Nelson Chu

  authored and

  topperc

  committed
  10a7198

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Commits on Oct 28, 2021

• [RISCV] Use vmv.v.[v|i] if we know COPY is under the same vl and vtype.

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  Hsiangkai

  committed
  0a9b829

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Commits on Oct 17, 2021

• [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

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  kito-cheng

  committed
  ff13189

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Commits on Sep 24, 2021

• [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

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  Hsiangkai

  committed
  7d39a8a

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Commits on Sep 12, 2021

• [RISCV] Initial support .insn directive for the assembler.

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  topperc

  committed
  2838797

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Commits on Aug 4, 2021

• [RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.

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  topperc

  committed
  643ce70

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Commits on Jul 5, 2021

• [RISCV] Pass FeatureBitset by reference rather than by value. NFCI

  Show description for 21a1bcb
  topperc

  committed
  21a1bcb

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Commits on May 27, 2021

• [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

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  topperc

  committed
  527cd01

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Commits on May 24, 2021

• [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

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  topperc

  committed
  b510e4c

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Commits on May 21, 2021

• RISCV: add a few deprecated aliases for CSRs

  Show description for 6c6b3e3
  compnerd

  committed
  6c6b3e3

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Commits on May 12, 2021

• [RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

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  topperc

  committed
  9c34540

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Commits on May 11, 2021

• [RISCV] Move instruction information into the RISCVII namespace (NFC)

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  Evandro Menezes

  committed
  3a64b70

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Commits on Apr 28, 2021

• [RISCV] Add explanatory comment to RISCVOp::OPERAND_AVL.

  topperc

  committed
  1d4d6a9

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Commits on Apr 27, 2021

• [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter.

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  topperc

  committed
  ce09dd5

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Commits on Feb 8, 2021

• [RISCV] Make scalable vector FMA commutable for register allocation.

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  topperc

  committed
  b7b4f4c

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Commits on Jan 27, 2021

• [RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC

  Show description for 58aa049
  topperc

  committed
  58aa049

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• [RISCV] Group the legal vector types into lists we can iterator over in the RISCVISelLowering constructor

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  topperc

  committed
  04570e9

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Commits on Jan 21, 2021

• [RISCV] Make LMUL field in VTYPE continuous.

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  Hsiangkai

  committed
  9dd5aea

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Commits on Jan 14, 2021

• [RISCV] Merge Utils library into MCTargetDesc

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  topperc

  committed
  387d3c2

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Commits on Oct 4, 2018

• [RISCV] Support named operands for CSR instructions.

  Show description for 9d6c553
  

  Ana Pazos

  committed
  9d6c553

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Commits on Sep 7, 2018

• [RISCV] Fix crash in decoding instruction with unknown floating point rounding mode

  Show description for b2ed11a
  

  Ana Pazos

  committed
  b2ed11a

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Commits on Dec 7, 2017

• [RISCV] MC layer support for load/store instructions of the C (compressed) extension

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  asb

  committed
  9f6aec4

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• [RISCV] MC layer support for the standard RV32F instruction set extension

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  asb

  committed
  0d6cf90

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Commits on Oct 19, 2017

• [RISCV] Prepare for the use of variable-sized register classes

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  asb

  committed
  ee7c7ec

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Commits on Sep 28, 2017

• [RISCV] Add common fixups and relocations

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  asb

  committed
  9d3f125

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Commits on Sep 17, 2017

• [RISCV] Add support for all RV32I instructions

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  asb

  committed
  6758ecb

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