[RISCV] Prepare for the use of variable-sized register classes

While parameterising by XLen, also take the opportunity to clean up the 
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at 
<https://github.com/lowrisc/riscv-llvm>.

llvm-svn: 316159

Author: asb

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

@@ -56,14 +56,14 @@ extern "C" void LLVMInitializeRISCVDisassembler() {
 }
 
 static const unsigned GPRDecoderTable[] = {
-  RISCV::X0_32,  RISCV::X1_32,  RISCV::X2_32,  RISCV::X3_32,
-  RISCV::X4_32,  RISCV::X5_32,  RISCV::X6_32,  RISCV::X7_32,
-  RISCV::X8_32,  RISCV::X9_32,  RISCV::X10_32, RISCV::X11_32,
-  RISCV::X12_32, RISCV::X13_32, RISCV::X14_32, RISCV::X15_32,
-  RISCV::X16_32, RISCV::X17_32, RISCV::X18_32, RISCV::X19_32,
-  RISCV::X20_32, RISCV::X21_32, RISCV::X22_32, RISCV::X23_32,
-  RISCV::X24_32, RISCV::X25_32, RISCV::X26_32, RISCV::X27_32,
-  RISCV::X28_32, RISCV::X29_32, RISCV::X30_32, RISCV::X31_32
+  RISCV::X0,  RISCV::X1,  RISCV::X2,  RISCV::X3,
+  RISCV::X4,  RISCV::X5,  RISCV::X6,  RISCV::X7,
+  RISCV::X8,  RISCV::X9,  RISCV::X10, RISCV::X11,
+  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
+  RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
+  RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
+  RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
+  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
 };
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -26,9 +26,10 @@ enum {
   InstFormatR = 1,
   InstFormatI = 2,
   InstFormatS = 3,
-  InstFormatSB = 4,
+  InstFormatB = 4,
   InstFormatU = 5,
-  InstFormatOther = 6,
+  InstFormatJ = 6,
+  InstFormatOther = 7,
 
   InstFormatMask = 15
 };

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

@@ -159,7 +159,7 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
     if (Desc.getOpcode() == RISCV::JAL) {
       FixupKind = RISCV::fixup_riscv_jal;
-    } else if (MIFrm == RISCVII::InstFormatSB) {
+    } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
     }
   }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

@@ -42,7 +42,7 @@ static MCInstrInfo *createRISCVMCInstrInfo() {
 
 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
-  InitRISCVMCRegisterInfo(X, RISCV::X1_32);
+  InitRISCVMCRegisterInfo(X, RISCV::X1);
   return X;
 }
 
@@ -51,6 +51,14 @@ static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
   return new RISCVMCAsmInfo(TT);
 }
 
+static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
+                                                   StringRef CPU, StringRef FS) {
+  std::string CPUName = CPU;
+  if (CPUName.empty())
+    CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
+  return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
+}
+
 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
                                                unsigned SyntaxVariant,
                                                const MCAsmInfo &MAI,
@@ -67,6 +75,6 @@ extern "C" void LLVMInitializeRISCVTargetMC() {
     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
-    TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfoImpl);
+    TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
   }
 }

llvm/lib/Target/RISCV/RISCV.td

@@ -9,19 +9,37 @@
 
 include "llvm/Target/Target.td"
 
-include "RISCVRegisterInfo.td"
-include "RISCVInstrInfo.td"
+//===----------------------------------------------------------------------===//
+// RISC-V subtarget features and instruction predicates.
+//===----------------------------------------------------------------------===//
 
+def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
+                                    "Implements RV64">;
 
-def RISCVInstrInfo : InstrInfo;
+def RV64         : HwMode<"+64bit">;
+def RV32         : HwMode<"-64bit">;
+
+//===----------------------------------------------------------------------===//
+// Register file, instruction descriptions.
+//===----------------------------------------------------------------------===//
+
+include "RISCVRegisterInfo.td"
+include "RISCVInstrInfo.td"
 
-def Feature64Bit   : SubtargetFeature<"64bit", "HasRV64", "true",
-                                      "Implements RV64">;
+//===----------------------------------------------------------------------===//
+// RISC-V processors supported.
+//===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+//===----------------------------------------------------------------------===//
+// Define the RISC-V target.
+//===----------------------------------------------------------------------===//
+
+def RISCVInstrInfo : InstrInfo;
+
 def RISCVAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
 }

llvm/lib/Target/RISCV/RISCVInstrFormats.td

@@ -35,12 +35,40 @@ def InstFormatPseudo : InstFormat<0>;
 def InstFormatR      : InstFormat<1>;
 def InstFormatI      : InstFormat<2>;
 def InstFormatS      : InstFormat<3>;
-def InstFormatSB     : InstFormat<4>;
+def InstFormatB      : InstFormat<4>;
 def InstFormatU      : InstFormat<5>;
-def InstFormatOther  : InstFormat<6>;
+def InstFormatJ      : InstFormat<6>;
+def InstFormatOther  : InstFormat<7>;
 
-class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
-                InstFormat format>
+// The following opcode names and match those given in Table 19.1 in the
+// RISC-V User-level ISA specification ("RISC-V base opcode map").
+class RISCVOpcode<bits<7> val> {
+  bits<7> Value = val;
+}
+def OPC_LOAD      : RISCVOpcode<0b0000011>;
+def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;
+def OPC_MISC_MEM  : RISCVOpcode<0b0001111>;
+def OPC_OP_IMM    : RISCVOpcode<0b0010011>;
+def OPC_AUIPC     : RISCVOpcode<0b0010111>;
+def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
+def OPC_STORE     : RISCVOpcode<0b0100011>;
+def OPC_STORE_FP  : RISCVOpcode<0b0100111>;
+def OPC_AMO       : RISCVOpcode<0b0101111>;
+def OPC_OP        : RISCVOpcode<0b0110011>;
+def OPC_LUI       : RISCVOpcode<0b0110111>;
+def OPC_OP_32     : RISCVOpcode<0b0111011>;
+def OPC_MADD      : RISCVOpcode<0b1000011>;
+def OPC_MSUB      : RISCVOpcode<0b1000111>;
+def OPC_NMSUB     : RISCVOpcode<0b1001011>;
+def OPC_NMADD     : RISCVOpcode<0b1001111>;
+def OPC_OP_FP     : RISCVOpcode<0b1010011>;
+def OPC_BRANCH    : RISCVOpcode<0b1100011>;
+def OPC_JALR      : RISCVOpcode<0b1100111>;
+def OPC_JAL       : RISCVOpcode<0b1101111>;
+def OPC_SYSTEM    : RISCVOpcode<0b1110011>;
+
+class RVInst<dag outs, dag ins, string opcodestr, string argstr,
+             list<dag> pattern, InstFormat format>
     : Instruction {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
@@ -58,22 +86,26 @@ class RISCVInst<dag outs, dag ins, string asmstr, list<dag> pattern,
 
   dag OutOperandList = outs;
   dag InOperandList = ins;
-  let AsmString = asmstr;
+  let AsmString = opcodestr # "\t" # argstr;
   let Pattern = pattern;
 
   let TSFlags{3-0} = format.Value;
 }
 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern>
-    : RISCVInst<outs, ins, "", pattern, InstFormatPseudo> {
+    : RVInst<outs, ins, "", "", pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
-class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
-         string asmstr, list<dag> pattern> : RISCVInst<outs, ins, asmstr, pattern, InstFormatR>
-{
+// Instruction formats are listed in the order they appear in the RISC-V
+// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
+// RVInstRAtomic) sorted alphabetically.
+
+class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+              dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
@@ -83,12 +115,12 @@ class FR<bits<7> funct7, bits<3> funct3, bits<7> opcode, dag outs, dag ins,
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
-{
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
@@ -97,12 +129,12 @@ class FI<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatI>
-{
+class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
+                   dag outs, dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<5> shamt;
   bits<5> rs1;
   bits<5> rd;
@@ -114,12 +146,12 @@ class FI32Shift<bit arithshift, bits<3> funct3, bits<7> opcode, dag outs, dag in
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatS>
-{
+class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
@@ -129,12 +161,12 @@ class FS<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = imm12{4-0};
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatSB>
-{
+class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;
@@ -146,23 +178,23 @@ class FSB<bits<3> funct3, bits<7> opcode, dag outs, dag ins, string asmstr, list
   let Inst{14-12} = funct3;
   let Inst{11-8} = imm12{3-0};
   let Inst{7} = imm12{10};
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FU<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
-{
+class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+              string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
   bits<20> imm20;
   bits<5> rd;
 
   let Inst{31-12} = imm20;
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }
 
-class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
-    : RISCVInst<outs, ins, asmstr, pattern, InstFormatU>
-{
+class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+              string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {
   bits<20> imm20;
   bits<5> rd;
 
@@ -171,5 +203,5 @@ class FUJ<bits<7> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{20} = imm20{10};
   let Inst{19-12} = imm20{18-11};
   let Inst{11-7} = rd;
-  let Opcode = opcode;
+  let Opcode = opcode.Value;
 }