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Commits on Jan 4, 2021

• [Sparc] Fixes for the internal assembler

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  LemonBoy

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Commits on Nov 18, 2019

• [Sparc] Fix "Cannot select" error for AtomicFence on 32-bit V9

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  jrtc27

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Commits on Sep 13, 2019

• DAG/GlobalISel: Correct type profile of bitcount ops

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  arsenm

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Commits on Jan 19, 2019

• Update the file headers across all of the LLVM projects in the monorepo

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  chandlerc

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Commits on Sep 3, 2018

• [Sparc] allow tls_add/tls_call syntax in assembler parser

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  doac

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Commits on May 23, 2016

• [SPARC] Fix 8 and 16-bit atomic load and store.

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  jyknight

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Commits on Mar 29, 2016

• [SPARC] Use AtomicExpandPass to expand AtomicRMW instructions.

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  jyknight

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Commits on May 18, 2015

• Sparc: Add the "alternate address space" load/store instructions.

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  jyknight

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Commits on Apr 28, 2015

• Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"

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  Sergey Dmitrouk

  committed
  842a51b

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• Revert "[DebugInfo] Add debug locations to constant SD nodes"

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  djasper-gh

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• [DebugInfo] Add debug locations to constant SD nodes

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  Sergey Dmitrouk

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Commits on May 16, 2014

• Sparc: disable printing on longer "brX,pt" aliases

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  TNorthover

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Commits on Mar 2, 2014

• [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.

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  vegovin

  committed
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• [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).

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  vegovin

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• [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.

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  vegovin

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Commits on Mar 1, 2014

• [SparcV9] Add support for parsing branch instructions with prediction.

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  vegovin

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• [Sparc] Add support to disassemble sparc memory instructions.

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  vegovin

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Commits on Feb 7, 2014

• [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.

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  vegovin

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Commits on Jan 30, 2014

• Implement SPARCv9 atomic_swap_64 with a pseudo.

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  stoklund

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Commits on Jan 24, 2014

• Implement atomicrmw operations in 32 and 64 bits for SPARCv9.

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  stoklund

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Commits on Jan 12, 2014

• [Sparc] Add support for parsing floating point instructions.

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  vegovin

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Commits on Jan 9, 2014

• [Sparc] Multiclass for loads/stores. No functionality change intended.

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  vegovin

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Commits on Jan 8, 2014

• [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly.

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  vegovin

  committed
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• [Sparc] Add support for parsing branch instructions and conditional moves.

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  vegovin

  committed
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Commits on Jan 6, 2014

• [Sparc] Add initial implementation of disassembler for sparc

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  vegovin

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Commits on Jan 4, 2014

• [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.

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  vegovin

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Commits on Jan 1, 2014

• [Sparc] Handle atomic loads/stores in sparc backend.

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  vegovin

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Commits on Dec 29, 2013

• [SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.

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  vegovin

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Commits on Nov 24, 2013

• [Sparc]: Implement LEA pattern for sparcv9.

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  vegovin

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Commits on Nov 3, 2013

• [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.

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  vegovin

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• [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.

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  vegovin

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Commits on Oct 6, 2013

• [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.

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  vegovin

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Commits on Sep 22, 2013

• [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

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  vegovin

  committed
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• [Sparc] Add support for TLS in sparc.

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  vegovin

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Commits on Jun 7, 2013

• Remember the anyext patterns.

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  stoklund

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