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[SparcV9] Use separate instruction patterns for 64 bit arithmetic instructions instead of reusing 32 bit instruction patterns.
 This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
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4 files changed

+199
-40
lines changed

4 files changed

+199
-40
lines changed

‎llvm/lib/Target/Sparc/SparcAsmPrinter.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
227227
if (MI->getOpcode() == SP::CALL)
228228
assert(TF == SPII::MO_NO_FLAG &&
229229
"Cannot handle target flags on call address");
230-
else if (MI->getOpcode() == SP::SETHIi)
230+
else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi)
231231
assert((TF == SPII::MO_HI || TF == SPII::MO_H44 || TF == SPII::MO_HH
232232
|| TF == SPII::MO_TLS_GD_HI22
233233
|| TF == SPII::MO_TLS_LDM_HI22
@@ -250,7 +250,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
250250
else if (MI->getOpcode() == SP::TLS_LDXrr)
251251
assert(TF == SPII::MO_TLS_IE_LDX &&
252252
"Cannot handle target flags on ldx for TLS");
253-
else if (MI->getOpcode() == SP::XORri)
253+
else if (MI->getOpcode() == SP::XORri || MI->getOpcode() == SP::XORXri)
254254
assert((TF == SPII::MO_TLS_LDO_LOX10 || TF == SPII::MO_TLS_LE_LOX10) &&
255255
"Cannot handle target flags on xor for TLS");
256256
else

‎llvm/lib/Target/Sparc/SparcInstr64Bit.td

+59-20
Original file line numberDiff line numberDiff line change
@@ -141,32 +141,36 @@ def : Pat<(i64 imm:$val),
141141
let Predicates = [Is64Bit] in {
142142

143143
// Register-register instructions.
144-
145-
def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
146-
def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
147-
def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
148-
149-
def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
150-
def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>;
151-
def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
152-
153-
def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
154-
def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
144+
defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
145+
defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
146+
defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
147+
148+
def ANDXNrr : F3_1<2, 0b000101,
149+
(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
150+
"andn $b, $c, $dst",
151+
[(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
152+
def ORXNrr : F3_1<2, 0b000110,
153+
(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
154+
"orn $b, $c, $dst",
155+
[(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
156+
def XNORXrr : F3_1<2, 0b000111,
157+
(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
158+
"xnor $b, $c, $dst",
159+
[(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
160+
161+
defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
162+
defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
155163

156164
def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
157165

158-
def : Pat<(tlsadd i64:$a, i64:$b, tglobaltlsaddr:$sym),
159-
(TLS_ADDrr $a, $b, $sym)>;
166+
def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
167+
(ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
168+
"add $rs1, $rs2, $rd, $sym",
169+
[(set i64:$rd,
170+
(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
160171

161172
// Register-immediate instructions.
162173

163-
def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
164-
def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>;
165-
def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
166-
167-
def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
168-
def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
169-
170174
def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
171175

172176
def : Pat<(ctpop i64:$src), (POPCrr $src)>;
@@ -402,3 +406,38 @@ def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
402406
(MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
403407

404408
} // Predicates = [Is64Bit]
409+
410+
411+
// 64 bit SETHI
412+
let Predicates = [Is64Bit] in {
413+
def SETHIXi : F2_1<0b100,
414+
(outs IntRegs:$rd), (ins i64imm:$imm22),
415+
"sethi $imm22, $rd",
416+
[(set i64:$rd, SETHIimm:$imm22)]>;
417+
}
418+
// Global addresses, constant pool entries
419+
let Predicates = [Is64Bit] in {
420+
421+
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
422+
def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>;
423+
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
424+
def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>;
425+
426+
// GlobalTLS addresses
427+
def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
428+
def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>;
429+
def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
430+
(ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
431+
def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
432+
(XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
433+
434+
// Blockaddress
435+
def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
436+
def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>;
437+
438+
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
439+
def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
440+
def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
441+
def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
442+
(ADDXri $r, tblockaddress:$in)>;
443+
}

‎llvm/lib/Target/Sparc/SparcInstrInfo.td

+22-18
Original file line numberDiff line numberDiff line change
@@ -210,15 +210,16 @@ def FCC_O : FCC_VAL<29>; // Ordered
210210
//===----------------------------------------------------------------------===//
211211

212212
/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
213-
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
213+
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
214+
RegisterClass RC, ValueType Ty, Operand immOp> {
214215
def rr : F3_1<2, Op3Val,
215-
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
216+
(outs RC:$dst), (ins RC:$b, RC:$c),
216217
!strconcat(OpcStr, " $b, $c, $dst"),
217-
[(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
218+
[(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>;
218219
def ri : F3_2<2, Op3Val,
219-
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
220+
(outs RC:$dst), (ins RC:$b, immOp:$c),
220221
!strconcat(OpcStr, " $b, $c, $dst"),
221-
[(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
222+
[(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>;
222223
}
223224

224225
/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
@@ -464,7 +465,7 @@ let rd = 0, imm22 = 0 in
464465
def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
465466

466467
// Section B.11 - Logical Instructions, p. 106
467-
defm AND : F3_12<"and", 0b000001, and>;
468+
defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
468469

469470
def ANDNrr : F3_1<2, 0b000101,
470471
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
@@ -474,7 +475,7 @@ def ANDNri : F3_2<2, 0b000101,
474475
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
475476
"andn $b, $c, $dst", []>;
476477

477-
defm OR : F3_12<"or", 0b000010, or>;
478+
defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
478479

479480
def ORNrr : F3_1<2, 0b000110,
480481
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
@@ -483,7 +484,7 @@ def ORNrr : F3_1<2, 0b000110,
483484
def ORNri : F3_2<2, 0b000110,
484485
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
485486
"orn $b, $c, $dst", []>;
486-
defm XOR : F3_12<"xor", 0b000011, xor>;
487+
defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
487488

488489
def XNORrr : F3_1<2, 0b000111,
489490
(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
@@ -494,12 +495,12 @@ def XNORri : F3_2<2, 0b000111,
494495
"xnor $b, $c, $dst", []>;
495496

496497
// Section B.12 - Shift Instructions, p. 107
497-
defm SLL : F3_12<"sll", 0b100101, shl>;
498-
defm SRL : F3_12<"srl", 0b100110, srl>;
499-
defm SRA : F3_12<"sra", 0b100111, sra>;
498+
defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
499+
defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
500+
defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
500501

501502
// Section B.13 - Add Instructions, p. 108
502-
defm ADD : F3_12<"add", 0b000000, add>;
503+
defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
503504

504505
// "LEA" forms of add (patterns to make tblgen happy)
505506
let Predicates = [Is32Bit] in
@@ -509,18 +510,18 @@ let Predicates = [Is32Bit] in
509510
[(set iPTR:$dst, ADDRri:$addr)]>;
510511

511512
let Defs = [ICC] in
512-
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
513+
defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
513514

514515
let Uses = [ICC], Defs = [ICC] in
515-
defm ADDX : F3_12<"addxcc", 0b011000, adde>;
516+
defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
516517

517518
// Section B.15 - Subtract Instructions, p. 110
518-
defm SUB : F3_12 <"sub" , 0b000100, sub>;
519+
defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
519520
let Uses = [ICC], Defs = [ICC] in
520-
defm SUBX : F3_12 <"subxcc" , 0b011100, sube>;
521+
defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
521522

522523
let Defs = [ICC] in
523-
defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
524+
defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
524525

525526
let Defs = [ICC], rd = 0 in {
526527
def CMPrr : F3_1<2, 0b010100,
@@ -542,7 +543,7 @@ let Uses = [ICC], Defs = [ICC] in
542543
// Section B.18 - Multiply Instructions, p. 113
543544
let Defs = [Y] in {
544545
defm UMUL : F3_12np<"umul", 0b001010>;
545-
defm SMUL : F3_12 <"smul", 0b001011, mul>;
546+
defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
546547
}
547548

548549
// Section B.19 - Divide Instructions, p. 115
@@ -987,6 +988,8 @@ def : Pat<(i32 imm:$val),
987988

988989

989990
// Global addresses, constant pool entries
991+
let Predicates = [Is32Bit] in {
992+
990993
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
991994
def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
992995
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
@@ -1009,6 +1012,7 @@ def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
10091012
def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
10101013
def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
10111014
(ADDri $r, tblockaddress:$in)>;
1015+
}
10121016

10131017
// Calls:
10141018
def : Pat<(call tglobaladdr:$dst),

‎llvm/test/CodeGen/SPARC/64spill.ll

+116
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,116 @@
1+
; RUN: llc < %s -march=sparcv9 | FileCheck %s
2+
3+
target datalayout = "E-i64:64-n32:64-S128"
4+
target triple = "sparc64-sun-sparc"
5+
6+
; CHECK-LABEL: test_and_spill
7+
; CHECK: and %i0, %i1, [[R:%[gilo][0-7]]]
8+
; CHECK: stx [[R]], [%fp+{{.+}}]
9+
; CHECK: ldx [%fp+{{.+}}, %i0
10+
define i64 @test_and_spill(i64 %a, i64 %b) {
11+
entry:
12+
%r0 = and i64 %a, %b
13+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
14+
ret i64 %r0
15+
}
16+
17+
; CHECK-LABEL: test_or_spill
18+
; CHECK: or %i0, %i1, [[R:%[gilo][0-7]]]
19+
; CHECK: stx [[R]], [%fp+{{.+}}]
20+
; CHECK: ldx [%fp+{{.+}}, %i0
21+
define i64 @test_or_spill(i64 %a, i64 %b) {
22+
entry:
23+
%r0 = or i64 %a, %b
24+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
25+
ret i64 %r0
26+
}
27+
28+
; CHECK-LABEL: test_xor_spill
29+
; CHECK: xor %i0, %i1, [[R:%[gilo][0-7]]]
30+
; CHECK: stx [[R]], [%fp+{{.+}}]
31+
; CHECK: ldx [%fp+{{.+}}, %i0
32+
define i64 @test_xor_spill(i64 %a, i64 %b) {
33+
entry:
34+
%r0 = xor i64 %a, %b
35+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
36+
ret i64 %r0
37+
}
38+
39+
40+
; CHECK-LABEL: test_add_spill
41+
; CHECK: add %i0, %i1, [[R:%[gilo][0-7]]]
42+
; CHECK: stx [[R]], [%fp+{{.+}}]
43+
; CHECK: ldx [%fp+{{.+}}, %i0
44+
define i64 @test_add_spill(i64 %a, i64 %b) {
45+
entry:
46+
%r0 = add i64 %a, %b
47+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
48+
ret i64 %r0
49+
}
50+
51+
; CHECK-LABEL: test_sub_spill
52+
; CHECK: sub %i0, %i1, [[R:%[gilo][0-7]]]
53+
; CHECK: stx [[R]], [%fp+{{.+}}]
54+
; CHECK: ldx [%fp+{{.+}}, %i0
55+
define i64 @test_sub_spill(i64 %a, i64 %b) {
56+
entry:
57+
%r0 = sub i64 %a, %b
58+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
59+
ret i64 %r0
60+
}
61+
62+
; CHECK-LABEL: test_andi_spill
63+
; CHECK: and %i0, 1729, [[R:%[gilo][0-7]]]
64+
; CHECK: stx [[R]], [%fp+{{.+}}]
65+
; CHECK: ldx [%fp+{{.+}}, %i0
66+
define i64 @test_andi_spill(i64 %a) {
67+
entry:
68+
%r0 = and i64 %a, 1729
69+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
70+
ret i64 %r0
71+
}
72+
73+
; CHECK-LABEL: test_ori_spill
74+
; CHECK: or %i0, 1729, [[R:%[gilo][0-7]]]
75+
; CHECK: stx [[R]], [%fp+{{.+}}]
76+
; CHECK: ldx [%fp+{{.+}}, %i0
77+
define i64 @test_ori_spill(i64 %a) {
78+
entry:
79+
%r0 = or i64 %a, 1729
80+
%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
81+
ret i64 %r0
82+
}
83+
84+
; CHECK-LABEL: test_xori_spill
85+
; CHECK: xor %i0, 1729, [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%fp+{{.+}}]
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; CHECK: ldx [%fp+{{.+}}, %i0
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define i64 @test_xori_spill(i64 %a) {
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entry:
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%r0 = xor i64 %a, 1729
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%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
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ret i64 %r0
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}
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; CHECK-LABEL: test_addi_spill
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; CHECK: add %i0, 1729, [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%fp+{{.+}}]
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; CHECK: ldx [%fp+{{.+}}, %i0
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define i64 @test_addi_spill(i64 %a) {
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entry:
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%r0 = add i64 %a, 1729
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%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
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ret i64 %r0
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}
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; CHECK-LABEL: test_subi_spill
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; CHECK: add %i0, -1729, [[R:%[gilo][0-7]]]
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; CHECK: stx [[R]], [%fp+{{.+}}]
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; CHECK: ldx [%fp+{{.+}}, %i0
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define i64 @test_subi_spill(i64 %a) {
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entry:
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%r0 = sub i64 %a, 1729
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%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{g1},~{g2},~{g3},~{g4},~{g5},~{g6},~{g7},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6}"(i64 %r0)
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ret i64 %r0
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}
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