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Commits on Jan 28, 2022

• [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.

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Commits on Oct 2, 2021

• Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"

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  topperc

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Commits on Sep 8, 2021

• [RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos

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  topperc

  committed
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Commits on Sep 2, 2021

• [RISCV] Split PseudoVSETVLI into 2 instructions to allow different register classes for rs1.

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  topperc

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Commits on May 24, 2021

• [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

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  topperc

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Commits on Mar 18, 2021

• [RISCV] Spilling for Zvlsseg registers.

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  Hsiangkai

  committed
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Commits on Feb 3, 2021

• [RISCV] Add new vector instructions in v0.10.

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  Hsiangkai

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Commits on Dec 29, 2020

• [RISCV] Define vmclr.m/vmset.m intrinsics.

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  zakk0610

  committed
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Commits on Dec 4, 2020

• [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

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  topperc

  committed
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Commits on Jul 15, 2020

• [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos

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  jrtc27

  committed
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Commits on Jul 14, 2020

• Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"

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  lenary

  committed
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Commits on Jul 9, 2020

• [RISCV] Avoid Splitting MBB in RISCVExpandPseudo

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  lenary

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Commits on Jun 29, 2020

• [RISCV] Split the pseudo instruction splitting pass

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  luismarques

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Commits on Nov 14, 2019

• [RISCV] Use addi rather than add x0

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  lenary

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Commits on Aug 16, 2019

• [RISCV] Convert registers from unsigned to Register

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  luismarques

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Commits on Aug 12, 2019

• [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM

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  dsandersllvm

  committed
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Commits on Jun 19, 2019

• [RISCV] Add lowering of global TLS addresses

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  lewis-revill

  committed
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Commits on Jun 11, 2019

• [RISCV] Add lowering of addressing sequences for PIC

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  lewis-revill

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Commits on Apr 1, 2019

• [RISCV] Generate address sequences suitable for mcmodel=medium

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Commits on Jan 19, 2019

• Update the file headers across all of the LLVM projects in the monorepo

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  chandlerc

  committed
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Commits on Jan 17, 2019

• [RISCV] Add codegen support for RV64A

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  asb

  committed
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Commits on Nov 29, 2018

• [RISCV] Implement codegen for cmpxchg on RV32IA

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  asb

  committed
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Commits on Sep 19, 2018

• [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

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  asb

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