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Commits on Jun 14, 2021

• [RISCV] Transform unaligned RVV vector loads/stores to aligned ones

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  frasercrmck

  committed
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Commits on Jun 6, 2021

• [TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC)

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  nikic

  committed
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Commits on Jun 1, 2021

• [RISCV] Support vector types in combination with fastcc

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  frasercrmck

  committed
  4f500c4

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Commits on May 27, 2021

• [VP][SelectionDAG] Add a target-configurable EVL operand type

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  frasercrmck

  committed
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Commits on May 26, 2021

• [RISCV] Optimize SEW=64 shifts by splat on RV32.

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  topperc

  committed
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Commits on May 24, 2021

• [RISCV] Prevent store combining from infinitely looping

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  frasercrmck

  committed
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Commits on May 11, 2021

• [RISCV] Move instruction information into the RISCVII namespace (NFC)

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  Evandro Menezes

  committed
  3a64b70

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Commits on May 6, 2021

• [RISCV] Remove unused RISCV::VLEFF and VLEFF_MASK. NFC

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  topperc

  committed
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Commits on May 5, 2021

• [RISCV][VP] Lower VP ISD nodes to RVV instructions

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  frasercrmck

  committed
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Commits on May 4, 2021

• [RISCV] Lower splats of non-constant i1s as SETCCs

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  frasercrmck

  committed
  46fa214

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Commits on May 3, 2021

• [RISCV] Add support for fmin/fmax vector reductions

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  frasercrmck

  committed
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Commits on Apr 26, 2021

• [RISCV] [1/2] Add IR intrinsic for Zbe extension

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  LevyHsu

  authored and

  topperc

  committed
  8cf54c7

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Commits on Apr 23, 2021

• [RISCV] Only expose one interface for getContainerForFixedLengthVector in the RISCVTargetLowering class

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  topperc

  committed
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• [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max)

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  frasercrmck

  committed
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Commits on Apr 22, 2021

• [RISCV] [1/2] Add IR intrinsic for Zbp extension

  Show description for b49337b
  

  LevyHsu

  authored and

  topperc

  committed
  b49337b

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• [RISCV] Custom lowering of SET_ROUNDING

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  spavloff

  committed
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• [RISCV] Custom lowering of FLT_ROUNDS_

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  spavloff

  committed
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Commits on Apr 13, 2021

• [RISCV] Rename RISCVISD::GREVI(W)/GORCI(W) to RISCVISD::GREV(W)/GORC(W). Don't require second operand to be a constant.

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  topperc

  committed
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• [RISCV] Rename RISCVISD::SHFLI to RISCVISD::SHFL and don't require the second operand to be an immediate.

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  topperc

  committed
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Commits on Apr 8, 2021

• [RISCV] Support OR/XOR/AND reductions on vector masks

  Show description for a569344
  frasercrmck

  committed
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• [RISCV] DAG nodes and pseudo instructions for CSR access

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  spavloff

  committed
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Commits on Apr 7, 2021

• [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.

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  topperc

  committed
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Commits on Apr 5, 2021

• [RISCV] Split RISCVISD::VMV_S_XF_VL into separate integer and FP.

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  topperc

  committed
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Commits on Apr 1, 2021

• [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat.

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  topperc

  committed
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• [RISCV] Add custom type legalization to form MULHSU when possible.

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  topperc

  committed
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Commits on Mar 31, 2021

• [RISCV] Add RISCVISD opcodes for CLZW and CTZW.

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  topperc

  committed
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• [RISCV] Add support for the stepvector intrinsic

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  frasercrmck

  committed
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Commits on Mar 22, 2021

• [RISCV] Add support for fixed vector masked gather/scatter.

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  topperc

  committed
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Commits on Mar 19, 2021

• [RISCV] Lower scalable vector masked loads to intrinsics to match fixed vectors and reduce isel patterns.

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  topperc

  committed
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Commits on Mar 18, 2021

• [RISCV] Support scalable-vector masked scatter operations

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  frasercrmck

  committed
  3495031

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• [RISCV] Support scalable-vector masked gather operations

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  frasercrmck

  committed
  0331399

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Commits on Mar 17, 2021

• [RISCV] Support masked load/store for fixed vectors.

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  topperc

  committed
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Commits on Mar 15, 2021

• [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC.

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  topperc

  committed
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• [RISCV] Support inline asm for vector instructions.

  Show description for a81dff1
  Hsiangkai

  committed
  a81dff1

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Commits on Mar 12, 2021

• [RISCV] Optimize INSERT_VECTOR_ELT sequences

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  frasercrmck

  committed
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