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LevyHsu
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[RISCV] [1/2] Add IR intrinsic for Zbe extension
RV32/64: bcompress bdecompress RV64 ONLY: bcompressw bdecompressw Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D101143
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‎clang/include/clang/Basic/BuiltinsRISCV.def

+9
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,15 @@ TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
2626
TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
2727
TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
2828

29+
// Zbe extension
30+
TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
31+
TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
32+
"experimental-zbe,64bit")
33+
TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc",
34+
"experimental-zbe")
35+
TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc",
36+
"experimental-zbe,64bit")
37+
2938
// Zbp extension
3039
TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
3140
TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")

‎clang/lib/CodeGen/CGBuiltin.cpp

+14
Original file line numberDiff line numberDiff line change
@@ -17844,6 +17844,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
1784417844
case RISCV::BI__builtin_riscv_clmul:
1784517845
case RISCV::BI__builtin_riscv_clmulh:
1784617846
case RISCV::BI__builtin_riscv_clmulr:
17847+
case RISCV::BI__builtin_riscv_bcompress_32:
17848+
case RISCV::BI__builtin_riscv_bcompress_64:
17849+
case RISCV::BI__builtin_riscv_bdecompress_32:
17850+
case RISCV::BI__builtin_riscv_bdecompress_64:
1784717851
case RISCV::BI__builtin_riscv_grev_32:
1784817852
case RISCV::BI__builtin_riscv_grev_64:
1784917853
case RISCV::BI__builtin_riscv_gorc_32:
@@ -17883,6 +17887,16 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
1788317887
ID = Intrinsic::riscv_clmulr;
1788417888
break;
1788517889

17890+
// Zbe
17891+
case RISCV::BI__builtin_riscv_bcompress_32:
17892+
case RISCV::BI__builtin_riscv_bcompress_64:
17893+
ID = Intrinsic::riscv_bcompress;
17894+
break;
17895+
case RISCV::BI__builtin_riscv_bdecompress_32:
17896+
case RISCV::BI__builtin_riscv_bdecompress_64:
17897+
ID = Intrinsic::riscv_bdecompress;
17898+
break;
17899+
1788617900
// Zbp
1788717901
case RISCV::BI__builtin_riscv_grev_32:
1788817902
case RISCV::BI__builtin_riscv_grev_64:

‎clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbe.c

+33
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2+
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbe -emit-llvm %s -o - \
3+
// RUN: | FileCheck %s -check-prefix=RV32ZBE
4+
5+
// RV32ZBE-LABEL: @bcompress(
6+
// RV32ZBE-NEXT: entry:
7+
// RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
8+
// RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
9+
// RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
10+
// RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
11+
// RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
12+
// RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
13+
// RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]])
14+
// RV32ZBE-NEXT: ret i32 [[TMP2]]
15+
//
16+
long bcompress(long rs1, long rs2) {
17+
return __builtin_riscv_bcompress_32(rs1, rs2);
18+
}
19+
20+
// RV32ZBE-LABEL: @bdecompress(
21+
// RV32ZBE-NEXT: entry:
22+
// RV32ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
23+
// RV32ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
24+
// RV32ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
25+
// RV32ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
26+
// RV32ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
27+
// RV32ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
28+
// RV32ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]])
29+
// RV32ZBE-NEXT: ret i32 [[TMP2]]
30+
//
31+
long bdecompress(long rs1, long rs2) {
32+
return __builtin_riscv_bdecompress_32(rs1, rs2);
33+
}

‎clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbe.c

+63
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2+
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbe -emit-llvm %s -o - \
3+
// RUN: | FileCheck %s -check-prefix=RV64ZBE
4+
5+
// RV64ZBE-LABEL: @bcompressw(
6+
// RV64ZBE-NEXT: entry:
7+
// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
8+
// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
9+
// RV64ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
10+
// RV64ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
11+
// RV64ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
12+
// RV64ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
13+
// RV64ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bcompress.i32(i32 [[TMP0]], i32 [[TMP1]])
14+
// RV64ZBE-NEXT: ret i32 [[TMP2]]
15+
//
16+
int bcompressw(int rs1, int rs2) {
17+
return __builtin_riscv_bcompress_32(rs1, rs2);
18+
}
19+
20+
// RV64ZBE-LABEL: @bdecompressw(
21+
// RV64ZBE-NEXT: entry:
22+
// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
23+
// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
24+
// RV64ZBE-NEXT: store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
25+
// RV64ZBE-NEXT: store i32 [[RS2:%.*]], i32* [[RS2_ADDR]], align 4
26+
// RV64ZBE-NEXT: [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
27+
// RV64ZBE-NEXT: [[TMP1:%.*]] = load i32, i32* [[RS2_ADDR]], align 4
28+
// RV64ZBE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.bdecompress.i32(i32 [[TMP0]], i32 [[TMP1]])
29+
// RV64ZBE-NEXT: ret i32 [[TMP2]]
30+
//
31+
int bdecompressw(int rs1, int rs2) {
32+
return __builtin_riscv_bdecompress_32(rs1, rs2);
33+
}
34+
35+
// RV64ZBE-LABEL: @bcompress(
36+
// RV64ZBE-NEXT: entry:
37+
// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
38+
// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
39+
// RV64ZBE-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
40+
// RV64ZBE-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
41+
// RV64ZBE-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
42+
// RV64ZBE-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
43+
// RV64ZBE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bcompress.i64(i64 [[TMP0]], i64 [[TMP1]])
44+
// RV64ZBE-NEXT: ret i64 [[TMP2]]
45+
//
46+
long bcompress(long rs1, long rs2) {
47+
return __builtin_riscv_bcompress_64(rs1, rs2);
48+
}
49+
50+
// RV64ZBE-LABEL: @bdecompress(
51+
// RV64ZBE-NEXT: entry:
52+
// RV64ZBE-NEXT: [[RS1_ADDR:%.*]] = alloca i64, align 8
53+
// RV64ZBE-NEXT: [[RS2_ADDR:%.*]] = alloca i64, align 8
54+
// RV64ZBE-NEXT: store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
55+
// RV64ZBE-NEXT: store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
56+
// RV64ZBE-NEXT: [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
57+
// RV64ZBE-NEXT: [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
58+
// RV64ZBE-NEXT: [[TMP2:%.*]] = call i64 @llvm.riscv.bdecompress.i64(i64 [[TMP0]], i64 [[TMP1]])
59+
// RV64ZBE-NEXT: ret i64 [[TMP2]]
60+
//
61+
long bdecompress(long rs1, long rs2) {
62+
return __builtin_riscv_bdecompress_64(rs1, rs2);
63+
}

‎llvm/include/llvm/IR/IntrinsicsRISCV.td

+4
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,10 @@ let TargetPrefix = "riscv" in {
8989
def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
9090
def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
9191

92+
// Zbe
93+
def int_riscv_bcompress : BitManipGPRGPRIntrinsics;
94+
def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
95+
9296
// Zbp
9397
def int_riscv_grev : BitManipGPRGPRIntrinsics;
9498
def int_riscv_gorc : BitManipGPRGPRIntrinsics;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+30
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
191191
if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
192192
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
193193

194+
if (Subtarget.hasStdExtZbe() && Subtarget.is64Bit())
195+
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
196+
194197
if (Subtarget.is64Bit()) {
195198
setOperationAction(ISD::ADD, MVT::i32, Custom);
196199
setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -3152,6 +3155,12 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
31523155
IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
31533156
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
31543157
}
3158+
case Intrinsic::riscv_bcompress:
3159+
case Intrinsic::riscv_bdecompress: {
3160+
unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS
3161+
: RISCVISD::BDECOMPRESS;
3162+
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
3163+
}
31553164
case Intrinsic::riscv_vmv_x_s:
31563165
assert(Op.getValueType() == XLenVT && "Unexpected VT!");
31573166
return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
@@ -4753,6 +4762,21 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
47534762
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
47544763
break;
47554764
}
4765+
case Intrinsic::riscv_bcompress:
4766+
case Intrinsic::riscv_bdecompress: {
4767+
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
4768+
"Unexpected custom legalisation");
4769+
SDValue NewOp1 =
4770+
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
4771+
SDValue NewOp2 =
4772+
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
4773+
unsigned Opc = IntNo == Intrinsic::riscv_bcompress
4774+
? RISCVISD::BCOMPRESSW
4775+
: RISCVISD::BDECOMPRESSW;
4776+
SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
4777+
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
4778+
break;
4779+
}
47564780
case Intrinsic::riscv_vmv_x_s: {
47574781
EVT VT = N->getValueType(0);
47584782
MVT XLenVT = Subtarget.getXLenVT();
@@ -5708,6 +5732,8 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
57085732
case RISCVISD::FSRW:
57095733
case RISCVISD::SHFLW:
57105734
case RISCVISD::UNSHFLW:
5735+
case RISCVISD::BCOMPRESSW:
5736+
case RISCVISD::BDECOMPRESSW:
57115737
// TODO: As the result is sign-extended, this is conservatively correct. A
57125738
// more precise answer could be calculated for SRAW depending on known
57135739
// bits in the shift amount.
@@ -7458,6 +7484,10 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
74587484
NODE_NAME_CASE(SHFLW)
74597485
NODE_NAME_CASE(UNSHFL)
74607486
NODE_NAME_CASE(UNSHFLW)
7487+
NODE_NAME_CASE(BCOMPRESS)
7488+
NODE_NAME_CASE(BCOMPRESSW)
7489+
NODE_NAME_CASE(BDECOMPRESS)
7490+
NODE_NAME_CASE(BDECOMPRESSW)
74617491
NODE_NAME_CASE(VMV_V_X_VL)
74627492
NODE_NAME_CASE(VFMV_V_F_VL)
74637493
NODE_NAME_CASE(VMV_X_S)

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

+8
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,14 @@ enum NodeType : unsigned {
9999
SHFLW,
100100
UNSHFL,
101101
UNSHFLW,
102+
// Bit Compress/Decompress implement the generic bit extract and bit deposit
103+
// functions. This operation is also referred to as bit gather/scatter, bit
104+
// pack/unpack, parallel extract/deposit, compress/expand, or right
105+
// compress/right expand.
106+
BCOMPRESS,
107+
BCOMPRESSW,
108+
BDECOMPRESS,
109+
BDECOMPRESSW,
102110
// Vector Extension
103111
// VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
104112
// for the VL value to be used for the operation.

‎llvm/lib/Target/RISCV/RISCVInstrInfoB.td

+14
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,10 @@ def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
3333
def riscv_shflw : SDNode<"RISCVISD::SHFLW", SDT_RISCVIntBinOpW>;
3434
def riscv_unshfl : SDNode<"RISCVISD::UNSHFL", SDTIntBinOp>;
3535
def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>;
36+
def riscv_bcompress : SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>;
37+
def riscv_bcompressw : SDNode<"RISCVISD::BCOMPRESSW", SDT_RISCVIntBinOpW>;
38+
def riscv_bdecompress : SDNode<"RISCVISD::BDECOMPRESS", SDTIntBinOp>;
39+
def riscv_bdecompressw : SDNode<"RISCVISD::BDECOMPRESSW",SDT_RISCVIntBinOpW>;
3640

3741
def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
3842
let Name = "UImmLog2XLenHalf";
@@ -934,6 +938,16 @@ def : PatGprGpr<int_riscv_clmulh, CLMULH>;
934938
def : PatGprGpr<int_riscv_clmulr, CLMULR>;
935939
} // Predicates = [HasStdExtZbc]
936940

941+
let Predicates = [HasStdExtZbe] in {
942+
def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
943+
def : PatGprGpr<riscv_bdecompress, BDECOMPRESS>;
944+
} // Predicates = [HasStdExtZbe]
945+
946+
let Predicates = [HasStdExtZbe, IsRV64] in {
947+
def : PatGprGpr<riscv_bcompressw, BCOMPRESSW>;
948+
def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
949+
} // Predicates = [HasStdExtZbe, IsRV64]
950+
937951
let Predicates = [HasStdExtZbr] in {
938952
def : PatGpr<int_riscv_crc32_b, CRC32B>;
939953
def : PatGpr<int_riscv_crc32_h, CRC32H>;

‎llvm/test/CodeGen/RISCV/rv32zbe-intrinsic.ll

+37
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV32IB
4+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbe -verify-machineinstrs < %s \
5+
; RUN: | FileCheck %s -check-prefix=RV32IBE
6+
7+
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
8+
9+
define i32 @bcompress32(i32 %a, i32 %b) nounwind {
10+
; RV32IB-LABEL: bcompress32:
11+
; RV32IB: # %bb.0:
12+
; RV32IB-NEXT: bcompress a0, a0, a1
13+
; RV32IB-NEXT: ret
14+
;
15+
; RV32IBE-LABEL: bcompress32:
16+
; RV32IBE: # %bb.0:
17+
; RV32IBE-NEXT: bcompress a0, a0, a1
18+
; RV32IBE-NEXT: ret
19+
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
20+
ret i32 %tmp
21+
}
22+
23+
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
24+
25+
define i32 @bdecompress32(i32 %a, i32 %b) nounwind {
26+
; RV32IB-LABEL: bdecompress32:
27+
; RV32IB: # %bb.0:
28+
; RV32IB-NEXT: bdecompress a0, a0, a1
29+
; RV32IB-NEXT: ret
30+
;
31+
; RV32IBE-LABEL: bdecompress32:
32+
; RV32IBE: # %bb.0:
33+
; RV32IBE-NEXT: bdecompress a0, a0, a1
34+
; RV32IBE-NEXT: ret
35+
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
36+
ret i32 %tmp
37+
}

‎llvm/test/CodeGen/RISCV/rv64zbe-intrinsic.ll

+69
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s -check-prefix=RV64IB
4+
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbe -verify-machineinstrs < %s \
5+
; RUN: | FileCheck %s -check-prefix=RV64IBE
6+
7+
declare i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
8+
9+
define signext i32 @bcompress32(i32 signext %a, i32 signext %b) nounwind {
10+
; RV64IB-LABEL: bcompress32:
11+
; RV64IB: # %bb.0:
12+
; RV64IB-NEXT: bcompressw a0, a0, a1
13+
; RV64IB-NEXT: ret
14+
;
15+
; RV64IBE-LABEL: bcompress32:
16+
; RV64IBE: # %bb.0:
17+
; RV64IBE-NEXT: bcompressw a0, a0, a1
18+
; RV64IBE-NEXT: ret
19+
%tmp = call i32 @llvm.riscv.bcompress.i32(i32 %a, i32 %b)
20+
ret i32 %tmp
21+
}
22+
23+
declare i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
24+
25+
define signext i32 @bdecompress32(i32 signext %a, i32 signext %b) nounwind {
26+
; RV64IB-LABEL: bdecompress32:
27+
; RV64IB: # %bb.0:
28+
; RV64IB-NEXT: bdecompressw a0, a0, a1
29+
; RV64IB-NEXT: ret
30+
;
31+
; RV64IBE-LABEL: bdecompress32:
32+
; RV64IBE: # %bb.0:
33+
; RV64IBE-NEXT: bdecompressw a0, a0, a1
34+
; RV64IBE-NEXT: ret
35+
%tmp = call i32 @llvm.riscv.bdecompress.i32(i32 %a, i32 %b)
36+
ret i32 %tmp
37+
}
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declare i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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define i64 @bcompress64(i64 %a, i64 %b) nounwind {
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; RV64IB-LABEL: bcompress64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bcompress a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bcompress64:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bcompress a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bcompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}
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declare i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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define i64 @bdecompress64(i64 %a, i64 %b) nounwind {
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; RV64IB-LABEL: bdecompress64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: bdecompress a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBE-LABEL: bdecompress64:
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; RV64IBE: # %bb.0:
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; RV64IBE-NEXT: bdecompress a0, a0, a1
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; RV64IBE-NEXT: ret
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%tmp = call i64 @llvm.riscv.bdecompress.i64(i64 %a, i64 %b)
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ret i64 %tmp
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}

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