The Herd toolsuite to deal with .cat memory models (version 7.xx)

Box86 - Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices

OpenTitan: Open source silicon root of trust

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

stb single-file public domain libraries for C/C++

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Collect some CS textbooks for learning.

Open-sourced DDR3 controller

NVMeVirt: A Versatile Software-defined Virtual NVMe Device

Sail RISC-V model

The RISC-V Virtual Machine

Mold: A Modern Linker 🦠

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

使用 C++23 从零实现的 RISC-V 模拟器

Dynamic Instrumentation Tool Platform

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

Kite: Architecture Simulator for RISC-V Instruction Set

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

SimpleVisor is a simple, portable, Intel VT-x hypervisor with two specific goals: using the least amount of assembly code (10 lines), and having the smallest amount of VMX-related code to support d…

The OpenPiton Platform

Embedded systems memory management library. Implementations for malloc(), free(), and other useful memory management functions

Bao, a Lightweight Static Partitioning Hypervisor

Multi-Architecture UEFI Environment Driver

A basic working RISCV emulator written in C

Network on Chip Simulator

A small, light weight, RISC CPU soft core