AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Send video/audio over HDMI on an FPGA

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

AMBA AXI VIP

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

Test suite designed to check compliance with the SystemVerilog standard.

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Методические материалы по разработке процессора архитектуры RISC-V

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

A simple superscalar out-of-order RISC-V microprocessor

Network on Chip Implementation written in SytemVerilog

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

Vector processor for RISC-V vector ISA

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.