Skip to content

feat: add succinct-zkvm os and target #138463

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 7 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from 1 commit
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Next Next commit
feat: succinct-zkvm target
  • Loading branch information
nhtyy committed Mar 13, 2025
commit ea4c1604cf9c3731ae897b013595505ec1dca06b
1 change: 1 addition & 0 deletions compiler/rustc_target/src/spec/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1954,6 +1954,7 @@ supported_targets! {

("riscv32i-unknown-none-elf", riscv32i_unknown_none_elf),
("riscv32im-risc0-zkvm-elf", riscv32im_risc0_zkvm_elf),
("riscv32im-succinct-zkvm-elf", riscv32im_succinct_zkvm_elf),
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

By putting a dash in the target OS, you make it look like it's vendor:succinct, os:zkvm. I would recommend calling it riscv32im-succinct_zkvm-elf or even just rustc32im-succinct-elf instead

Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Fixed!

("riscv32im-unknown-none-elf", riscv32im_unknown_none_elf),
("riscv32ima-unknown-none-elf", riscv32ima_unknown_none_elf),
("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
use crate::spec::{
Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata, TargetOptions,
};

pub(crate) fn target() -> Target {
Target {
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
llvm_target: "riscv32".into(),
metadata: TargetMetadata {
description: Some("Succinct's zero-knowledge Virtual Machine (RV32IM ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: None,
},
pointer_width: 32,
arch: "riscv32".into(),

options: TargetOptions {
os: "succinct-zkvm".into(),
vendor: "succinct".into(),
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(),

// The zkvm is singlethreaded and all operations are atomic.
// The std-lib is compiled with lowered atomicsa and the default Succinct build tools
// enforce this on programs.
max_atomic_width: Some(64),
atomic_cas: true,

features: "+m".into(),
llvm_abiname: "ilp32".into(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
emit_debug_gdb_scripts: false,
eh_frame_header: false,
singlethread: true,
..Default::default()
},
}
}
1 change: 1 addition & 0 deletions src/bootstrap/src/core/sanity.rs
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ pub struct Finder {
const STAGE0_MISSING_TARGETS: &[&str] = &[
// just a dummy comment so the list doesn't get onelined
"wasm32-wali-linux-musl",
"riscv32im-succinct-zkvm-elf"
];

/// Minimum version threshold for libstdc++ required when using prebuilt LLVM
Expand Down
1 change: 1 addition & 0 deletions src/tools/build-manifest/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,7 @@ static TARGETS: &[&str] = &[
"powerpc64le-unknown-linux-musl",
"riscv32i-unknown-none-elf",
"riscv32im-risc0-zkvm-elf",
"riscv32im-succinct-zkvm-elf",
"riscv32im-unknown-none-elf",
"riscv32ima-unknown-none-elf",
"riscv32imc-unknown-none-elf",
Expand Down
3 changes: 3 additions & 0 deletions tests/assembly/targets/targets-elf.rs
Original file line number Diff line number Diff line change
Expand Up @@ -421,6 +421,9 @@
//@ revisions: riscv32im_risc0_zkvm_elf
//@ [riscv32im_risc0_zkvm_elf] compile-flags: --target riscv32im-risc0-zkvm-elf
//@ [riscv32im_risc0_zkvm_elf] needs-llvm-components: riscv
//@ revisions: riscv32im_succinct_zkvm_elf
//@ [riscv32im_succinct_zkvm_elf] compile-flags: --target riscv32im-succinct-zkvm-elf
//@ [riscv32im_succinct_zkvm_elf] needs-llvm-components: riscv
//@ revisions: riscv32im_unknown_none_elf
//@ [riscv32im_unknown_none_elf] compile-flags: --target riscv32im-unknown-none-elf
//@ [riscv32im_unknown_none_elf] needs-llvm-components: riscv
Expand Down
Loading