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Commits on Feb 7, 2022

• [llvm] Use = default (NFC)

  kazutakahirata

  committed
  3a3cb92

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Commits on Feb 1, 2022

• [RISCC] Add missing words to comment. NFC

  topperc

  committed
  f943c58

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• [RISCV] Fix a vsetvli insertion bug involving loads/stores.

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  topperc

  committed
  7eb7810

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Commits on Jan 2, 2022

• [RISCV] Prune unnecessary vector pseudo instructions. NFC

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  topperc

  committed
  4602f41

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Commits on Dec 31, 2021

• [RISCV] Fix incorrect cases of vmv.s.f in the VSETVLI insert pass.

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  jacquesguan

  committed
  05f82dc

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Commits on Dec 30, 2021

• [RISCV] Teach VSETVLInsert to eliminate redundant vsetvli for vmv.s.x and vfmv.s.f.

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  jacquesguan

  committed
  128c6ed

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Commits on Nov 15, 2021

• [RISCV] Teach needVSETVLIPHI to handle mask register instructions.

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  topperc

  committed
  f59307b

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Commits on Oct 29, 2021

• [RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register instructions better.

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  topperc

  committed
  aefcd59

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Commits on Oct 28, 2021

• [RISCV] Replace most uses of RISCVSubtarget::hasStdExtV. NFCI

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  topperc

  committed
  1387483

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Commits on Oct 22, 2021

• [RISCV] Fix missing cross-block VSETVLI insertion

  Show description for 74c6895
  frasercrmck

  committed
  74c6895

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Commits on Sep 24, 2021

• [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

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  Hsiangkai

  committed
  7d39a8a

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Commits on Sep 10, 2021

• [RISCV] Teach vsetvli insertion that stores don't use the policy bits in vtype.

  Show description for 6c7cadb
  topperc

  committed
  6c7cadb

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Commits on Sep 3, 2021

• [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0.

  Show description for 75620fa
  topperc

  committed
  75620fa

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Commits on Sep 2, 2021

• [RISCV] Split PseudoVSETVLI into 2 instructions to allow different register classes for rs1.

  Show description for e4e69ba
  topperc

  committed
  e4e69ba

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Commits on Aug 12, 2021

• [RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for unit-stride or strided loads/stores in some cases.

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  topperc

  committed
  79fbddb

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Commits on Aug 4, 2021

• [RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.

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  topperc

  committed
  643ce70

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Commits on Aug 3, 2021

• [RISCV] Teach VSETVLI insertion to merge the unused VSETVLI with the one need to be insert after it.

  Show description for 7900ee0
  

  jacquesguan

  authored and

  benshi001

  committed
  7900ee0

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Commits on Jul 23, 2021

• [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.

  Show description for 5edccc4
  topperc

  committed
  5edccc4

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Commits on Jul 21, 2021

• [RISCV] Cleanup comment around vector tail policy handling. NFC

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  topperc

  committed
  a467c08

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Commits on Jun 21, 2021

• [RISCV] Remove extra character from a comment. NFC

  topperc

  committed
  c2e01ee

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Commits on Jun 18, 2021

• [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch.

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  topperc

  committed
  ac87133

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Commits on Jun 9, 2021

• [RISCV] Remove unused method from RISCVInsertVSETVLI. NFC

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  topperc

  committed
  8dfd081

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Commits on Jun 4, 2021

• [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.

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  topperc

  committed
  c653711

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• [RISCV] Simplify some code in RISCVInsertVSETVLI by calling an existing function that does the same thing. NFCI

  topperc

  committed
  e9313fa

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Commits on May 27, 2021

• [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli.

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  topperc

  committed
  0fa5aac

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• [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

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  topperc

  committed
  527cd01

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Commits on May 26, 2021

• [RISCV] Use X0 as destination of inserted vsetvli when possible.

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  topperc

  committed
  fdf10e6

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• [RISCV] Don't propagate VL/VTYPE across inline assembly in the Insert VSETVLI pass.

  Show description for b2c7ac8
  topperc

  committed
  b2c7ac8

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• [RISCV] Enable cross basic block aware vsetvli insertion

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  topperc

  committed
  1b47a3d

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Commits on May 24, 2021

• [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.

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  topperc

  committed
  b510e4c

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