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Commits on Feb 5, 2022

• Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)."

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  topperc

  committed
  c1cef11

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• [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).

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  topperc

  committed
  673d68c

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Commits on Feb 3, 2022

• [RISCV] Remove RISCVISD::SPLAT_VECTOR_I64 in favor of RISCVISD::VMV_V_X_VL.

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  topperc

  committed
  2349fb0

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Commits on Feb 2, 2022

• [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.

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  topperc

  committed
  b73d151

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Commits on Jan 30, 2022

• [RISCV] Remove RISCVISD::BREV8 and use RISCVISD::GREV instead.

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  topperc

  committed
  5245453

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Commits on Jan 29, 2022

• [RISCV] Custom legalize BITREVERSE with Zbkb.

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  topperc

  committed
  d8f929a

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Commits on Jan 28, 2022

• [RISCV] Add support for matching vwmulsu from fixed vectors

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  ZCBing

  authored and

  benshi001

  committed
  6d6c44a

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Commits on Jan 24, 2022

• [RISCV][VP] Lower VP_MERGE to RVV instructions

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  frasercrmck

  committed
  af773a1

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Commits on Jan 20, 2022

• [RISCV] Optimize vector_shuffles that are interleaving the lowest elements of two vectors.

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  topperc

  committed
  fa8bb22

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Commits on Jan 18, 2022

• Recommit "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

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  topperc

  committed
  aa7fc02

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• Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

  Show description for e328385
  topperc

  committed
  e328385

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• [RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering.

  Show description for b634f8a
  topperc

  committed
  b634f8a

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• Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

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  david-arm

  committed
  f4515ab

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• [RISCV] Provide VLOperand in td.

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  HanKuanChen

  authored and

  topperc

  committed
  ec9cb3a

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• [RISCV] Make SplatOperand start from 0.

  Show description for 3fc4b58
  

  HanKuanChen

  authored and

  topperc

  committed
  3fc4b58

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Commits on Jan 17, 2022

• [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

  Show description for 197f3c0
  david-arm

  committed
  197f3c0

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Commits on Jan 13, 2022

• Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

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  david-arm

  committed
  ba471ba

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• [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

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  david-arm

  committed
  31009f0

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• [RISCV] Add bfp and bfpw intrinsic in zbf extension

  Show description for 16877c5
  

  Lian Wang

  authored and

  benshi001

  committed
  16877c5

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Commits on Jan 11, 2022

• [RISCV] Generate 32 bits jumptable entries when code model is small

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  pcwang-thead

  committed
  c6430fa

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• [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT

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  pcwang-thead

  committed
  98d51c2

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Commits on Jan 6, 2022

• [RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.

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  topperc

  committed
  808c662

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Commits on Dec 31, 2021

• [RISCV] Use constant pool for large integers

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  pcwang-thead

  committed
  41454ab

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Commits on Dec 23, 2021

• [RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions

  Show description for 10b3675
  

  victor-eds

  authored and

  topperc

  committed
  10b3675

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• [RISCV] Support strict FP conversion operations.

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  topperc

  committed
  b7b260e

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• [RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.

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  jacquesguan

  committed
  28a3e7d

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Commits on Dec 14, 2021

• [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.

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  topperc

  committed
  3f1c403

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Commits on Nov 30, 2021

• [DAG] Create fptosi.sat from clamped fptosi

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  davemgreen

  committed
  9e8a71c

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• Revert "[DAG] Create fptosi.sat from clamped fptosi"

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  zmodem

  committed
  a87782c

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• [DAG] Create fptosi.sat from clamped fptosi

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  davemgreen

  committed
  52ff3b0

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Commits on Nov 19, 2021

• [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk

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  ptomsich

  authored and

  topperc

  committed
  af57a71

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Commits on Nov 16, 2021

• [RISCV] Override TargetLowering::hasAndNot for Zbb.

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  topperc

  committed
  391b0ba

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Commits on Nov 4, 2021

• [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

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  zakk0610

  committed
  0649dfe

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Commits on Sep 23, 2021

• [RISCV][VP] Add support for VP_REDUCE_* operations

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  frasercrmck

  committed
  e7c879a

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Commits on Sep 20, 2021

• [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.

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  topperc

  committed
  d85e347

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