Commits

History for

Commits on Feb 4, 2022

[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
topperc
committedFeb 4, 2022

Commits on Jan 6, 2022

[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
topperc
committedJan 6, 2022

Commits on Sep 20, 2021

[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
topperc
committedSep 20, 2021

Commits on May 24, 2021

[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
topperc
committedMay 24, 2021

Commits on Mar 16, 2021

[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
MaskRay
committedMar 16, 2021

Commits on Jan 14, 2021

[RISCV] Merge Utils library into MCTargetDesc
topperc
committedJan 14, 2021

Commits on Dec 11, 2020

[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
topperc
committedDec 11, 2020

Commits on Jun 29, 2020

[RISCV] Split the pseudo instruction splitting pass
luismarques
committedJun 29, 2020

Commits on Aug 20, 2019

[RISCV GlobalISel] Adding initial GlobalISel infrastructure
dsandersllvm
committedAug 20, 2019

Commits on Jan 19, 2019

Update the file headers across all of the LLVM projects in the monorepo
chandlerc
committedJan 19, 2019

Commits on Oct 4, 2018

[RISCV] Support named operands for CSR instructions.
Ana Pazos
committedOct 4, 2018

Commits on Sep 19, 2018

[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A
asb
committedSep 19, 2018

Commits on Jun 27, 2018

[RISCV] Add machine function pass to merge base + offset
Sameer AbuAsal
committedJun 27, 2018

Commits on Nov 8, 2017

[RISCV] Codegen support for memory operations on global addresses
asb
committedNov 8, 2017

Commits on Oct 19, 2017

[RISCV] Initial codegen support for ALU operations
asb
committedOct 19, 2017

Loading