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Commits on Jan 18, 2022

• Recommit "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

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  topperc

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• Revert "[RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering."

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  topperc

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• [RISCV] Make the operand order for RISCVISD::FSL(W)/FSR(W) match the instruction register numbering.

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  topperc

  committed
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• Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

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  david-arm

  committed
  f4515ab

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• [RISCV] Provide VLOperand in td.

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  HanKuanChen

  authored and

  topperc

  committed
  ec9cb3a

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• [RISCV] Make SplatOperand start from 0.

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  HanKuanChen

  authored and

  topperc

  committed
  3fc4b58

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Commits on Jan 17, 2022

• [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

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  david-arm

  committed
  197f3c0

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Commits on Jan 13, 2022

• Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

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  david-arm

  committed
  ba471ba

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• [CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

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  david-arm

  committed
  31009f0

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• [RISCV] Add bfp and bfpw intrinsic in zbf extension

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  Lian Wang

  authored and

  benshi001

  committed
  16877c5

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Commits on Jan 11, 2022

• [RISCV] Generate 32 bits jumptable entries when code model is small

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  pcwang-thead

  committed
  c6430fa

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• [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT

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  pcwang-thead

  committed
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Commits on Jan 6, 2022

• [RISCV] Change RISCVISD::FCVT*RTZ opcodes to take rounding mode as an operand.

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  topperc

  committed
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Commits on Dec 31, 2021

• [RISCV] Use constant pool for large integers

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  pcwang-thead

  committed
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Commits on Dec 23, 2021

• [RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions

  Show description for 10b3675
  

  victor-eds

  authored and

  topperc

  committed
  10b3675

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• [RISCV] Support strict FP conversion operations.

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  topperc

  committed
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• [RISCV] Override hasAndNotCompare to use more andn when have Zbb extension.

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  jacquesguan

  committed
  28a3e7d

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Commits on Dec 14, 2021

• [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.

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  topperc

  committed
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Commits on Nov 30, 2021

• [DAG] Create fptosi.sat from clamped fptosi

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  davemgreen

  committed
  9e8a71c

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• Revert "[DAG] Create fptosi.sat from clamped fptosi"

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  zmodem

  committed
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• [DAG] Create fptosi.sat from clamped fptosi

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  davemgreen

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Commits on Nov 19, 2021

• [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk

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  ptomsich

  authored and

  topperc

  committed
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Commits on Nov 16, 2021

• [RISCV] Override TargetLowering::hasAndNot for Zbb.

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  topperc

  committed
  391b0ba

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Commits on Nov 4, 2021

• [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

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  zakk0610

  committed
  0649dfe

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Commits on Sep 23, 2021

• [RISCV][VP] Add support for VP_REDUCE_* operations

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  frasercrmck

  committed
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Commits on Sep 20, 2021

• [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.

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  topperc

  committed
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Commits on Sep 10, 2021

• [RISCV] Enable CGP to sink splat operands of Add/Sub/Mul/Shl/LShr/AShr

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  topperc

  committed
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Commits on Sep 7, 2021

• [RISCV][VP] Custom lower VP_STORE and VP_LOAD

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  frasercrmck

  committed
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• [RISCV][VP] Custom lower VP_SCATTER and VP_GATHER

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  frasercrmck

  committed
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Commits on Aug 22, 2021

• [DAGCombiner] Add target hook function to decide folding (mul (add x, c1), c2)

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  benshi001

  committed
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Commits on Aug 7, 2021

• [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.

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  topperc

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Commits on Jul 31, 2021

• [RISCV] Rename RISCVISD::FCVT_W_RV64 to FCVT_W_RTZ_RV64. NFC

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  topperc

  committed
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Commits on Jul 27, 2021

• [RISCV] Add support for vector saturating add/sub operations

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  frasercrmck

  committed
  172487f

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Commits on Jul 24, 2021

• [RISCV] Custom lower (i32 (fptoui/fptosi X)).

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  topperc

  committed
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Commits on Jul 6, 2021

• [RISCV] Add support for matching vwmul(u) and vwmacc(u) from fixed vectors.

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