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  1. python-to-verilog python-to-verilog Public

    Generate a Verilog Source file and testbench file for a given Moore FSM

    Python 17 4

  2. netlist netlist Public

    To build data structures for netlist description and to calculate fan outs and fan ins

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    Static Timing Analysis Assignment for EE5301 Proj 1b

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  4. vhdl-designs vhdl-designs Public

    Practice files for VHDL Digital Design

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  5. gauravtewari.github.io gauravtewari.github.io Public

    Forked from poole/lanyon

    Lanyon Theme forked

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  6. .emacs.d.old .emacs.d.old Public

    Backup of emacs config dir

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