davemuscle
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youtube-rip Public
Python script for ripping albums from Youtube utilizing yt-dlp and ffmpeg
Python UpdatedDec 11, 2023 -
ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedSep 4, 2023 -
cvw Public
Forked from openhwgroup/cvwCORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
Assembly Other UpdatedAug 20, 2023 -
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gravity-sim Public
Basic script for simulating Newtonian-celestial bodies using Pygame
Python UpdatedJun 19, 2023 -
fork-gtkwave Public
Forked from gtkwave/gtkwaveGTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
C GNU General Public License v2.0 UpdatedApr 8, 2023 -
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BrianHG-DDR3-Controller Public
Forked from BrianHGinc/BrianHG-DDR3-ControllerPersonal fork of open-source DDR3 PHY and controller
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sigma_delta_converters Public
Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
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camera_journey Public
Various lessons learned while designing an OV5640 camera display in VHDL/Embedded Linux on a Cyclone V SOC board
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fpga_mandlebrot_fractal Public
Mandlebrot fractal engine and native HDMI video pipeline designed in VHDL with a focus on timing analysis and resource utilization
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10band_nixie Public
Analog spectrum analyzer using old-world IN-9 neon gas Nixie Tubes on a through-hole PCB
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96band_msa Public
Music spectrum analyzer implemented on a 7-series FPGA with novel DSP algorithms written in VHDL to accurately bin piano keys to frequency ranges and display in real-time