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Caching-Policies Public
Implementation and comparison of various caching policies, on different type of workloads
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RANSAC_Robust_Curve_Fitting Public
Python implementation of RANSAC algorithm
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Python Implementation of Histogram Equalisation and Histogram Matching
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Image_Denoising Public
Python implementation of the Non Local Means algorithm for Image Denoising
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Pan_Tompkins_QRS_Detection Public
Python Implementation of Pan Tompkins Algorithm for QRS peak detection
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DataScience Public
Repository for implementation details for Data-Science
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Agent-Based-Simulations Public
Agent-Based-Modelling Models
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Netlogo Simulation for virality of videos on social media platform based on research by team @Google
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Scholaris Public
Forked from antimattercorrade/ScholarisA crowdsourced search engine, which will return the specifics about professors depending on various types of search queries.
HTML UpdatedMay 11, 2021 -
SeeSPIM-Compiler Public
This project implements a Compiler for a language similar to C. The Compiler takes as input program written in the language and generates MIPS assembly code that can be run on SPIM or simulators li…
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Mini_LinkedIn Public
A cli-interactive application build on the top of Network layer, with custom protocols, client-server finite-state-machines and TCP socket. This has been tested with mininet using network topologies.
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Socket-Programming-Variants Public
File transfer over TCP/UDP sockets with network programming on mininet and various models
Python UpdatedDec 9, 2020 -
TCP_UDP_File_Transfer Public
Simple file transfer over TCP, UDP sockets, with custom protocol configurations.
Python UpdatedDec 9, 2020 -
Concurrent-Trie Public
Concurrent Trie with different locking techniques (HOH, Single lock, Reader-Writer lock)
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concurrent_web_servers Public
Concurrent web server using producer-consumer problem with different scheduling policies - Shortest File First, Shortest File Name First, First in First Out, and security.
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This Project has been done under prof. Joycee Makie @ IIT Gandhinagar. The project contains tools to generate codes and implementation of arithmetic operations on a FPGA.
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RISCV_Three_Stage Public
RISC-V 3 stage in-order pipeline in verilog
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