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Revert "[AArch64] AArch64TargetLowering::computeKnownBitsForTargetNode - add support for AArch64ISD::MOV/MVN constants" (llvm#155503)
Reverts llvm#154039, as it breaks bots.
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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 0 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -2626,32 +2626,6 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
26262626
<< Op->getConstantOperandVal(1)));
26272627
break;
26282628
}
2629-
case AArch64ISD::MOVImsl: {
2630-
Known = KnownBits::makeConstant(
2631-
APInt(Known.getBitWidth(), ~(~Op->getConstantOperandVal(0)
2632-
<< Op->getConstantOperandVal(1))));
2633-
break;
2634-
}
2635-
case AArch64ISD::MOVIedit: {
2636-
Known = KnownBits::makeConstant(APInt(
2637-
Known.getBitWidth(),
2638-
AArch64_AM::decodeAdvSIMDModImmType10(Op->getConstantOperandVal(0))));
2639-
break;
2640-
}
2641-
case AArch64ISD::MVNIshift: {
2642-
Known = KnownBits::makeConstant(
2643-
APInt(Known.getBitWidth(),
2644-
~(Op->getConstantOperandVal(0) << Op->getConstantOperandVal(1)),
2645-
/*isSigned*/ false, /*implicitTrunc*/ true));
2646-
break;
2647-
}
2648-
case AArch64ISD::MVNImsl: {
2649-
Known = KnownBits::makeConstant(
2650-
APInt(Known.getBitWidth(),
2651-
(~Op->getConstantOperandVal(0) << Op->getConstantOperandVal(1)),
2652-
/*isSigned*/ false, /*implicitTrunc*/ true));
2653-
break;
2654-
}
26552629
case AArch64ISD::LOADgot:
26562630
case AArch64ISD::ADDlow: {
26572631
if (!Subtarget->isTargetILP32())
@@ -30672,16 +30646,6 @@ bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
3067230646
return Op.getOpcode() == AArch64ISD::DUP ||
3067330647
Op.getOpcode() == AArch64ISD::MOVI ||
3067430648
Op.getOpcode() == AArch64ISD::MOVIshift ||
30675-
Op.getOpcode() == AArch64ISD::MOVImsl ||
30676-
Op.getOpcode() == AArch64ISD::MOVIedit ||
30677-
Op.getOpcode() == AArch64ISD::MVNIshift ||
30678-
Op.getOpcode() == AArch64ISD::MVNImsl ||
30679-
// Ignoring fneg(movi(0)), because if it is folded to FPConstant(-0.0),
30680-
// ISel will select fmov(mov i64 0x8000000000000000), resulting in a
30681-
// fmov from fpr to gpr, which is more expensive than fneg(movi(0))
30682-
(Op.getOpcode() == ISD::FNEG &&
30683-
Op.getOperand(0).getOpcode() == AArch64ISD::MOVIedit &&
30684-
Op.getOperand(0).getConstantOperandVal(0) == 0) ||
3068530649
(Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
3068630650
Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
3068730651
TargetLowering::isTargetCanonicalConstantNode(Op);

llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -318,120 +318,6 @@ TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_UADDO_CARRY) {
318318
EXPECT_EQ(Known.One, APInt(8, 0x86));
319319
}
320320

321-
// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
322-
TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_MOVI) {
323-
SDLoc Loc;
324-
auto IntSca32VT = MVT::i32;
325-
auto Int8Vec8VT = MVT::v8i8;
326-
auto Int16Vec8VT = MVT::v16i8;
327-
auto Int4Vec16VT = MVT::v4i16;
328-
auto Int8Vec16VT = MVT::v8i16;
329-
auto Int2Vec32VT = MVT::v2i32;
330-
auto Int4Vec32VT = MVT::v4i32;
331-
auto IntVec64VT = MVT::v1i64;
332-
auto Int2Vec64VT = MVT::v2i64;
333-
auto N165 = DAG->getConstant(0x000000A5, Loc, IntSca32VT);
334-
KnownBits Known;
335-
336-
auto OpMOVIedit64 = DAG->getNode(AArch64ISD::MOVIedit, Loc, IntVec64VT, N165);
337-
Known = DAG->computeKnownBits(OpMOVIedit64);
338-
EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00));
339-
EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF));
340-
341-
auto OpMOVIedit128 =
342-
DAG->getNode(AArch64ISD::MOVIedit, Loc, Int2Vec64VT, N165);
343-
Known = DAG->computeKnownBits(OpMOVIedit128);
344-
EXPECT_EQ(Known.Zero, APInt(64, 0x00FF00FFFF00FF00));
345-
EXPECT_EQ(Known.One, APInt(64, 0xFF00FF0000FF00FF));
346-
347-
auto N264 = DAG->getConstant(264, Loc, IntSca32VT);
348-
auto OpMOVImsl64 =
349-
DAG->getNode(AArch64ISD::MOVImsl, Loc, Int2Vec32VT, N165, N264);
350-
Known = DAG->computeKnownBits(OpMOVImsl64);
351-
EXPECT_EQ(Known.Zero, APInt(32, 0xFFFF5A00));
352-
EXPECT_EQ(Known.One, APInt(32, 0x0000A5FF));
353-
354-
auto N272 = DAG->getConstant(272, Loc, IntSca32VT);
355-
auto OpMOVImsl128 =
356-
DAG->getNode(AArch64ISD::MOVImsl, Loc, Int4Vec32VT, N165, N272);
357-
Known = DAG->computeKnownBits(OpMOVImsl128);
358-
EXPECT_EQ(Known.Zero, APInt(32, 0xFF5A0000));
359-
EXPECT_EQ(Known.One, APInt(32, 0x00A5FFFF));
360-
361-
auto OpMVNImsl64 =
362-
DAG->getNode(AArch64ISD::MVNImsl, Loc, Int2Vec32VT, N165, N272);
363-
Known = DAG->computeKnownBits(OpMVNImsl64);
364-
EXPECT_EQ(Known.Zero, APInt(32, 0x00A5FFFF));
365-
EXPECT_EQ(Known.One, APInt(32, 0xFF5A0000));
366-
367-
auto OpMVNImsl128 =
368-
DAG->getNode(AArch64ISD::MVNImsl, Loc, Int4Vec32VT, N165, N264);
369-
Known = DAG->computeKnownBits(OpMVNImsl128);
370-
EXPECT_EQ(Known.Zero, APInt(32, 0x0000A5FF));
371-
EXPECT_EQ(Known.One, APInt(32, 0xFFFF5A00));
372-
373-
auto N0 = DAG->getConstant(0, Loc, IntSca32VT);
374-
auto OpMOVIshift2Vec32 =
375-
DAG->getNode(AArch64ISD::MOVIshift, Loc, Int2Vec32VT, N165, N0);
376-
Known = DAG->computeKnownBits(OpMOVIshift2Vec32);
377-
EXPECT_EQ(Known.Zero, APInt(32, 0xFFFFFF5A));
378-
EXPECT_EQ(Known.One, APInt(32, 0x000000A5));
379-
380-
auto N24 = DAG->getConstant(24, Loc, IntSca32VT);
381-
auto OpMOVIshift4Vec32 =
382-
DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec32VT, N165, N24);
383-
Known = DAG->computeKnownBits(OpMOVIshift4Vec32);
384-
EXPECT_EQ(Known.Zero, APInt(32, 0x5AFFFFFF));
385-
EXPECT_EQ(Known.One, APInt(32, 0xA5000000));
386-
387-
auto OpMVNIshift2Vec32 =
388-
DAG->getNode(AArch64ISD::MVNIshift, Loc, Int2Vec32VT, N165, N24);
389-
Known = DAG->computeKnownBits(OpMVNIshift2Vec32);
390-
EXPECT_EQ(Known.Zero, APInt(32, 0xA5000000));
391-
EXPECT_EQ(Known.One, APInt(32, 0x5AFFFFFF));
392-
393-
auto OpMVNIshift4Vec32 =
394-
DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec32VT, N165, N0);
395-
Known = DAG->computeKnownBits(OpMVNIshift4Vec32);
396-
EXPECT_EQ(Known.Zero, APInt(32, 0x000000A5));
397-
EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF5A));
398-
399-
auto N8 = DAG->getConstant(8, Loc, IntSca32VT);
400-
auto OpMOVIshift4Vec16 =
401-
DAG->getNode(AArch64ISD::MOVIshift, Loc, Int4Vec16VT, N165, N0);
402-
Known = DAG->computeKnownBits(OpMOVIshift4Vec16);
403-
EXPECT_EQ(Known.Zero, APInt(16, 0xFF5A));
404-
EXPECT_EQ(Known.One, APInt(16, 0x00A5));
405-
406-
auto OpMOVIshift8Vec16 =
407-
DAG->getNode(AArch64ISD::MOVIshift, Loc, Int8Vec16VT, N165, N8);
408-
Known = DAG->computeKnownBits(OpMOVIshift8Vec16);
409-
EXPECT_EQ(Known.Zero, APInt(16, 0x5AFF));
410-
EXPECT_EQ(Known.One, APInt(16, 0xA500));
411-
412-
auto OpMVNIshift4Vec16 =
413-
DAG->getNode(AArch64ISD::MVNIshift, Loc, Int4Vec16VT, N165, N8);
414-
Known = DAG->computeKnownBits(OpMVNIshift4Vec16);
415-
EXPECT_EQ(Known.Zero, APInt(16, 0xA500));
416-
EXPECT_EQ(Known.One, APInt(16, 0x5AFF));
417-
418-
auto OpMVNIshift8Vec16 =
419-
DAG->getNode(AArch64ISD::MVNIshift, Loc, Int8Vec16VT, N165, N0);
420-
Known = DAG->computeKnownBits(OpMVNIshift8Vec16);
421-
EXPECT_EQ(Known.Zero, APInt(16, 0x00A5));
422-
EXPECT_EQ(Known.One, APInt(16, 0xFF5A));
423-
424-
auto OpMOVI8Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int8Vec8VT, N165);
425-
Known = DAG->computeKnownBits(OpMOVI8Vec8);
426-
EXPECT_EQ(Known.Zero, APInt(8, 0x5A));
427-
EXPECT_EQ(Known.One, APInt(8, 0xA5));
428-
429-
auto OpMOVI16Vec8 = DAG->getNode(AArch64ISD::MOVI, Loc, Int16Vec8VT, N165);
430-
Known = DAG->computeKnownBits(OpMOVI16Vec8);
431-
EXPECT_EQ(Known.Zero, APInt(8, 0x5A));
432-
EXPECT_EQ(Known.One, APInt(8, 0xA5));
433-
}
434-
435321
// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
436322
TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
437323
SDLoc Loc;

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