From f9ec8cde0322b4987e41e2e2237570b397ea5acc Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 17:10:20 +0900 Subject: [PATCH 01/23] copy from "STM32CubeH5:STM32H503RBTX_FLASH.ld" --- variants/STM32H5xx/H503RBT/ldscript.ld | 185 +++++++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 variants/STM32H5xx/H503RBT/ldscript.ld diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld new file mode 100644 index 0000000000..4279fe58b9 --- /dev/null +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32H503RBTx Device from STM32H5 series +** 128Kbytes FLASH +** 32Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2021 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file From 9bc34bcbd5577c15ce9451f61e22433411172dcb Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 17:11:45 +0900 Subject: [PATCH 02/23] add offset. --- variants/STM32H5xx/H503RBT/ldscript.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld index 4279fe58b9..b23f150e0e 100644 --- a/variants/STM32H5xx/H503RBT/ldscript.ld +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -44,8 +44,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET } /* Sections */ From 30222b2bb05aa51e4eaa33d89425635f52dca52f Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 17:46:22 +0900 Subject: [PATCH 03/23] copy file. (not yet edit) --- .../H503RBT/variant_NUCLEO_H503RB.cpp | 89 ++++++++ .../STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h | 210 ++++++++++++++++++ 2 files changed, 299 insertions(+) create mode 100644 variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp create mode 100644 variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp new file mode 100644 index 0000000000..40e074826b --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -0,0 +1,89 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_H503RBTX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16/A8 + PB_1, // D17/A9 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_10, // D25 + PB_12, // D26 + PB_13, // D27 + PB_14, // D28 + PB_15, // D29 + PC_0, // D30/A10 + PC_1, // D31/A11 + PC_2, // D32/A12 + PC_3, // D33/A13 + PC_4, // D34/A14 + PC_5, // D35/A15 + PC_6, // D36 + PC_7, // D37 + PC_8, // D38 + PC_9, // D39 + PC_10, // D40 + PC_11, // D41 + PC_12, // D42 + PC_13, // D43 + PC_14, // D44 + PC_15, // D45 + PD_2, // D46 + PH_0, // D47 + PH_1 // D48 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 16, // A8, PB0 + 17, // A9, PB1 + 30, // A10, PC0 + 31, // A11, PC1 + 32, // A12, PC2 + 33, // A13, PC3 + 34, // A14, PC4 + 35 // A15, PC5 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h new file mode 100644 index 0000000000..dbbf762681 --- /dev/null +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -0,0 +1,210 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 PIN_A8 +#define PB1 PIN_A9 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB10 25 +#define PB12 26 +#define PB13 27 +#define PB14 28 +#define PB15 29 +#define PC0 PIN_A10 +#define PC1 PIN_A11 +#define PC2 PIN_A12 +#define PC3 PIN_A13 +#define PC4 PIN_A14 +#define PC5 PIN_A15 +#define PC6 36 +#define PC7 37 +#define PC8 38 +#define PC9 39 +#define PC10 40 +#define PC11 41 +#define PC12 42 +#define PC13 43 +#define PC14 44 +#define PC15 45 +#define PD2 46 +#define PH0 47 +#define PH1 48 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA8_ALT1 (PA8 | ALT1) +#define PA8_ALT2 (PA8 | ALT2) +#define PA9_ALT1 (PA9 | ALT1) +#define PA10_ALT1 (PA10 | ALT1) +#define PA11_ALT1 (PA11 | ALT1) +#define PA12_ALT1 (PA12 | ALT1) +#define PA13_ALT1 (PA13 | ALT1) +#define PA14_ALT1 (PA14 | ALT1) +#define PA14_ALT2 (PA14 | ALT2) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB4_ALT2 (PB4 | ALT2) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB6_ALT2 (PB6 | ALT2) +#define PB7_ALT1 (PB7 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) +#define PB15_ALT2 (PB15 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC2_ALT1 (PC2 | ALT1) +#define PC3_ALT1 (PC3 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC12_ALT1 (PC12 | ALT1) + +#define NUM_DIGITAL_PINS 49 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA0 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PA4_ALT1 +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PA15_ALT1 +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PB10 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA3 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PA2 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA1 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PB3 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PB3 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From e06cfe15ae67044613c8cdb92361fd57821afdc3 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 18:05:18 +0900 Subject: [PATCH 04/23] WIP: Add clock config. --- .../H503RBT/variant_NUCLEO_H503RB.cpp | 103 +++++++++++++++++- 1 file changed, 101 insertions(+), 2 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 40e074826b..181c363662 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -10,7 +10,7 @@ * ******************************************************************************* */ -#if defined(ARDUINO_GENERIC_H503RBTX) +#if defined(ARDUINO_NUCLEO_H503RB) #include "pins_arduino.h" // Digital PinName array @@ -86,4 +86,103 @@ const uint32_t analogInputPin[] = { 35 // A15, PC5 }; -#endif /* ARDUINO_GENERIC_* */ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 250; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 128; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 16; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 2; + PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 8; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* ARDUINO_NUCLEO_H503RB */ From f9585512cb55f0c485b0b7cdf89066350dbb1961 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 19:27:57 +0900 Subject: [PATCH 05/23] Add clock generation description. --- .../H503RBT/variant_NUCLEO_H503RB.cpp | 108 ++++++++++-------- .../STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h | 1 + 2 files changed, 63 insertions(+), 46 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 181c363662..aa8e2d0a13 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -10,6 +10,7 @@ * ******************************************************************************* */ + #if defined(ARDUINO_NUCLEO_H503RB) #include "pins_arduino.h" @@ -101,17 +102,35 @@ WEAK void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /** Configure the main internal regulator output voltage - */ + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE; + /** + * @note How to generate PLL clock + * + * HSE 8 MHz ... STLINK MCO output + * HSE 24 MHz ... on-board X3 (default) + * HSE 4~50 MHz ... prepare your own external clock + * LSE 32.768 kHz ... on-board X2 + * HSI 64 MHz ... internal clock + * HSI48 48 MHz ... internal clock for recovery + * LSI 32 kHz ... internal clock + * CSI 4 MHz ... internal clock for low power + * + * + * SOURCE / PLLM * PLLN + * + * + * PLL ... MULTIPLEXER / PLLP + * + * default CPU clock: + * 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz + */ + + /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -119,7 +138,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLM = 12; RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 2; @@ -127,15 +146,13 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_PCLK3; + /** Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -146,39 +163,38 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 128; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 16; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - PeriphClkInitStruct.PLL3.PLL3M = 2; - PeriphClkInitStruct.PLL3.PLL3N = 96; - PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 8; - PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - Error_Handler(); - } + // TODO: Edit peripherals clock config. + /** Initializes the peripherals clock */ + // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + // PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + // PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + // PeriphClkInitStruct.PLL2.PLL2M = 2; + // PeriphClkInitStruct.PLL2.PLL2N = 128; + // PeriphClkInitStruct.PLL2.PLL2P = 2; + // PeriphClkInitStruct.PLL2.PLL2Q = 16; + // PeriphClkInitStruct.PLL2.PLL2R = 2; + // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + // PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + // PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + // PeriphClkInitStruct.PLL3.PLL3M = 2; + // PeriphClkInitStruct.PLL3.PLL3N = 96; + // PeriphClkInitStruct.PLL3.PLL3P = 2; + // PeriphClkInitStruct.PLL3.PLL3Q = 8; + // PeriphClkInitStruct.PLL3.PLL3R = 2; + // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; + // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; + // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + // PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + + // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + // Error_Handler(); + // } } #ifdef __cplusplus diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h index dbbf762681..66c041da93 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -10,6 +10,7 @@ * ******************************************************************************* */ + #pragma once /*---------------------------------------------------------------------------- From 6fb1a228957ba13276f5cae13c3c17f5938cfe59 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 19:37:19 +0900 Subject: [PATCH 06/23] Add clock config description for NUCLEO-H563ZI. --- .../H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp | 47 +++++++++++++------ .../H563Z(G-I)T/variant_NUCLEO_H563ZI.h | 1 + 2 files changed, 33 insertions(+), 15 deletions(-) diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp index 20211d5437..017d74c204 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp @@ -10,6 +10,7 @@ * ******************************************************************************* */ + #if defined(ARDUINO_NUCLEO_H563ZI) #include "pins_arduino.h" @@ -179,11 +180,30 @@ WEAK void SystemClock_Config(void) while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE; + /** + * @note How to generate PLL clock + * + * HSE 8 MHz ... STLINK MCO output (default) + * HSE 25 MHz ... on-board X3 + * HSE 4~50 MHz ... prepare your own external clock + * LSE 32.768 kHz ... on-board X2 + * HSI 64 MHz ... internal clock + * HSI48 48 MHz ... internal clock for recovery + * LSI 32 kHz ... internal clock + * CSI 4 MHz ... internal clock for low power + * + * + * SOURCE / PLLM * PLLN + * + * + * PLL ... MULTIPLEXER / PLLP + * + * default CPU clock: + * 8(HSE) / 4(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz + */ + + /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -199,15 +219,13 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_PCLK3; + /** Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -218,11 +236,8 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 - | RCC_PERIPHCLK_USB; + /** Initializes the peripherals clock */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; PeriphClkInitStruct.PLL2.PLL2M = 2; @@ -248,6 +263,7 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } @@ -256,4 +272,5 @@ WEAK void SystemClock_Config(void) #ifdef __cplusplus } // extern "C" #endif + #endif /* ARDUINO_NUCLEO_H563ZI */ diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h index 0019181e6b..1e6c4f3078 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h @@ -10,6 +10,7 @@ * ******************************************************************************* */ + #pragma once /*---------------------------------------------------------------------------- From 04fddfe64c1692c0d6e0bb07e0deff6cc0dddb5f Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 19:38:47 +0900 Subject: [PATCH 07/23] fix wording. --- variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp index 017d74c204..7c97ecb07b 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp @@ -174,8 +174,7 @@ WEAK void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /** Configure the main internal regulator output voltage - */ + /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} From 26b23a49b8a083adbd0d9ca1a2e5b41d147ea7be Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 19:41:55 +0900 Subject: [PATCH 08/23] Add NUCLEO-H503RB variant. --- variants/STM32H5xx/H503RBT/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/variants/STM32H5xx/H503RBT/CMakeLists.txt b/variants/STM32H5xx/H503RBT/CMakeLists.txt index 2a4d55b6b1..e0f94897af 100644 --- a/variants/STM32H5xx/H503RBT/CMakeLists.txt +++ b/variants/STM32H5xx/H503RBT/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_H503RB.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) From f149a145760dac4fe1e88fd397b6d178a93c58b0 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 19:55:24 +0900 Subject: [PATCH 09/23] Add default generic clock config. --- variants/STM32H5xx/H503RBT/generic_clock.c | 100 ++++++++++++++++++++- 1 file changed, 97 insertions(+), 3 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index f30dcfb8df..e813043ad1 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -10,6 +10,7 @@ * ******************************************************************************* */ + #if defined(ARDUINO_GENERIC_H503RBTX) #include "pins_arduino.h" @@ -20,8 +21,101 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /** Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** + * @note How to generate PLL clock + * + * HSI 64 MHz ... internal clock + * HSI48 48 MHz ... internal clock for recovery + * LSI 32 kHz ... internal clock + * CSI 4 MHz ... internal clock for low power + * + * + * SOURCE / PLLM * PLLN + * + * + * PLL ... MULTIPLEXER / PLLP + * + * default CPU clock: + * 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz + */ + + /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + // TODO: Edit peripherals clock config. + /** Initializes the peripherals clock */ + // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + // PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + // PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + // PeriphClkInitStruct.PLL2.PLL2M = 2; + // PeriphClkInitStruct.PLL2.PLL2N = 128; + // PeriphClkInitStruct.PLL2.PLL2P = 2; + // PeriphClkInitStruct.PLL2.PLL2Q = 16; + // PeriphClkInitStruct.PLL2.PLL2R = 2; + // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + // PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + // PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + // PeriphClkInitStruct.PLL3.PLL3M = 2; + // PeriphClkInitStruct.PLL3.PLL3N = 96; + // PeriphClkInitStruct.PLL3.PLL3P = 2; + // PeriphClkInitStruct.PLL3.PLL3Q = 8; + // PeriphClkInitStruct.PLL3.PLL3R = 2; + // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; + // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; + // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + // PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + + // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + // Error_Handler(); + // } } -#endif /* ARDUINO_GENERIC_* */ +#endif /* ARDUINO_GENERIC_H503RBTX */ From a030c1995301904a71ff860e472837914e6db5c6 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 20:00:45 +0900 Subject: [PATCH 10/23] WIP: Configure peripherals clock. --- variants/STM32H5xx/H503RBT/generic_clock.c | 39 +++++-------------- .../H503RBT/variant_NUCLEO_H503RB.cpp | 14 +++---- 2 files changed, 16 insertions(+), 37 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index e813043ad1..2674357364 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -84,38 +84,17 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - // TODO: Edit peripherals clock config. /** Initializes the peripherals clock */ - // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - // PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - // PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - // PeriphClkInitStruct.PLL2.PLL2M = 2; - // PeriphClkInitStruct.PLL2.PLL2N = 128; - // PeriphClkInitStruct.PLL2.PLL2P = 2; - // PeriphClkInitStruct.PLL2.PLL2Q = 16; - // PeriphClkInitStruct.PLL2.PLL2R = 2; - // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - // PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - // PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - // PeriphClkInitStruct.PLL3.PLL3M = 2; - // PeriphClkInitStruct.PLL3.PLL3N = 96; - // PeriphClkInitStruct.PLL3.PLL3P = 2; - // PeriphClkInitStruct.PLL3.PLL3Q = 8; - // PeriphClkInitStruct.PLL3.PLL3R = 2; - // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; - // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - // PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - // Error_Handler(); - // } + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_H503RBTX */ diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index aa8e2d0a13..0400608b4c 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -167,6 +167,10 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; // PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; // PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; // PeriphClkInitStruct.PLL2.PLL2M = 2; // PeriphClkInitStruct.PLL2.PLL2N = 128; @@ -177,9 +181,6 @@ WEAK void SystemClock_Config(void) // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; // PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; // PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; // PeriphClkInitStruct.PLL3.PLL3M = 2; // PeriphClkInitStruct.PLL3.PLL3N = 96; @@ -190,11 +191,10 @@ WEAK void SystemClock_Config(void) // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; // PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - // if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { - // Error_Handler(); - // } + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } } #ifdef __cplusplus From 9a723ea10eba183339879743bb1b47dd9a434d2b Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 20:13:36 +0900 Subject: [PATCH 11/23] WIP: peripherals clock config. --- .../H503RBT/variant_NUCLEO_H503RB.cpp | 53 +++++++++---------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 0400608b4c..205b5db043 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -163,34 +163,33 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - // TODO: Edit peripherals clock config. /** Initializes the peripherals clock */ - // PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - // PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - // PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - // PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - // PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - // PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - // PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - // PeriphClkInitStruct.PLL2.PLL2M = 2; - // PeriphClkInitStruct.PLL2.PLL2N = 128; - // PeriphClkInitStruct.PLL2.PLL2P = 2; - // PeriphClkInitStruct.PLL2.PLL2Q = 16; - // PeriphClkInitStruct.PLL2.PLL2R = 2; - // PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - // PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - // PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - // PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - // PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - // PeriphClkInitStruct.PLL3.PLL3M = 2; - // PeriphClkInitStruct.PLL3.PLL3N = 96; - // PeriphClkInitStruct.PLL3.PLL3P = 2; - // PeriphClkInitStruct.PLL3.PLL3Q = 8; - // PeriphClkInitStruct.PLL3.PLL3R = 2; - // PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - // PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; - // PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - // PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + PeriphClkInitStruct.PLL2.PLL2M = 6; + PeriphClkInitStruct.PLL2.PLL2N = 128; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 16; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 6; + PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 8; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); From 97cd7b925da7f0edb621282c5f01e636c7d7b65b Mon Sep 17 00:00:00 2001 From: dojyorin Date: Fri, 4 Aug 2023 20:16:24 +0900 Subject: [PATCH 12/23] fix wording. --- variants/STM32H5xx/H503RBT/generic_clock.c | 16 ++--- .../H503RBT/variant_NUCLEO_H503RB.cpp | 58 +++++++++---------- 2 files changed, 37 insertions(+), 37 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 2674357364..922d77bff7 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -23,7 +23,7 @@ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct = {}; /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); @@ -85,14 +85,14 @@ WEAK void SystemClock_Config(void) } /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + RCC_PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + RCC_PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + RCC_PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + RCC_PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + RCC_PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } } diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 205b5db043..2f0ea77a8a 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -100,7 +100,7 @@ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct = {}; /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); @@ -164,34 +164,34 @@ WEAK void SystemClock_Config(void) } /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 6; - PeriphClkInitStruct.PLL2.PLL2N = 128; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 16; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - PeriphClkInitStruct.PLL3.PLL3M = 6; - PeriphClkInitStruct.PLL3.PLL3N = 96; - PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 8; - PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + RCC_PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + RCC_PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + RCC_PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + RCC_PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + RCC_PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + RCC_PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + RCC_PeriphClkInitStruct.PLL2.PLL2M = 6; + RCC_PeriphClkInitStruct.PLL2.PLL2N = 128; + RCC_PeriphClkInitStruct.PLL2.PLL2P = 2; + RCC_PeriphClkInitStruct.PLL2.PLL2Q = 16; + RCC_PeriphClkInitStruct.PLL2.PLL2R = 2; + RCC_PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + RCC_PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + RCC_PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + RCC_PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + RCC_PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + RCC_PeriphClkInitStruct.PLL3.PLL3M = 6; + RCC_PeriphClkInitStruct.PLL3.PLL3N = 96; + RCC_PeriphClkInitStruct.PLL3.PLL3P = 2; + RCC_PeriphClkInitStruct.PLL3.PLL3Q = 8; + RCC_PeriphClkInitStruct.PLL3.PLL3R = 2; + RCC_PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; + RCC_PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; + RCC_PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + RCC_PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } } From ba9029f4b5f379514d2df8296170917ba8e337b7 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 04:26:30 +0900 Subject: [PATCH 13/23] WIP: revert var name. --- variants/STM32H5xx/H503RBT/CMakeLists.txt | 3 +- variants/STM32H5xx/H503RBT/generic_clock.c | 60 +++++----- .../H503RBT/variant_NUCLEO_H503RB.cpp | 110 +++++++++--------- .../STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h | 2 +- 4 files changed, 81 insertions(+), 94 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/CMakeLists.txt b/variants/STM32H5xx/H503RBT/CMakeLists.txt index e0f94897af..455bd2130d 100644 --- a/variants/STM32H5xx/H503RBT/CMakeLists.txt +++ b/variants/STM32H5xx/H503RBT/CMakeLists.txt @@ -28,5 +28,4 @@ target_link_libraries(variant_bin PUBLIC variant_usage) target_link_libraries(variant INTERFACE variant_bin -) - +) \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 922d77bff7..e46cfcb2f3 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -15,39 +15,33 @@ #include "pins_arduino.h" /** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ + * @note How to generate PLL clock + * + * HSI 64 MHz ... internal clock + * HSI48 48 MHz ... internal clock for recovery + * LSI 32.768 kHz ... internal clock + * CSI 4 MHz ... internal clock for low power + * + * + * SOURCE / PLLM * PLLN + * + * + * PLL ... MULTIPLEXER / PLLP + * + * default CPU clock: + * 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz + */ + +WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** - * @note How to generate PLL clock - * - * HSI 64 MHz ... internal clock - * HSI48 48 MHz ... internal clock for recovery - * LSI 32 kHz ... internal clock - * CSI 4 MHz ... internal clock for low power - * - * - * SOURCE / PLLM * PLLN - * - * - * PLL ... MULTIPLEXER / PLLP - * - * default CPU clock: - * 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz - */ - /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -85,16 +79,16 @@ WEAK void SystemClock_Config(void) } /** Initializes the peripherals clock */ - RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - RCC_PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - RCC_PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; - RCC_PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - RCC_PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - RCC_PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } } -#endif /* ARDUINO_GENERIC_H503RBTX */ +#endif /* ARDUINO_GENERIC_H503RBTX */ \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 2f0ea77a8a..a8f3e21676 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -92,43 +92,37 @@ extern "C" { #endif /** - * @brief System Clock Configuration - * @param None - * @retval None - */ -WEAK void SystemClock_Config(void) -{ + * @note How to generate PLL clock + * + * HSE 8 MHz ... STLINK MCO output + * HSE 24 MHz ... on-board X3 (default) + * HSE 4~50 MHz ... prepare your own external clock + * LSE 32.768 kHz ... on-board X2 + * HSI 64 MHz ... internal clock + * HSI48 48 MHz ... internal clock for recovery + * LSI 32.768 kHz ... internal clock + * CSI 4 MHz ... internal clock for low power + * + * + * SOURCE / PLLM * PLLN + * + * + * PLL ... MULTIPLEXER / PLLP + * + * default CPU clock: + * 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz + */ + +WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** - * @note How to generate PLL clock - * - * HSE 8 MHz ... STLINK MCO output - * HSE 24 MHz ... on-board X3 (default) - * HSE 4~50 MHz ... prepare your own external clock - * LSE 32.768 kHz ... on-board X2 - * HSI 64 MHz ... internal clock - * HSI48 48 MHz ... internal clock for recovery - * LSI 32 kHz ... internal clock - * CSI 4 MHz ... internal clock for low power - * - * - * SOURCE / PLLM * PLLN - * - * - * PLL ... MULTIPLEXER / PLLP - * - * default CPU clock: - * 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz - */ - /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; @@ -164,34 +158,34 @@ WEAK void SystemClock_Config(void) } /** Initializes the peripherals clock */ - RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - RCC_PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - RCC_PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - RCC_PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - RCC_PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - RCC_PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - RCC_PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - RCC_PeriphClkInitStruct.PLL2.PLL2M = 6; - RCC_PeriphClkInitStruct.PLL2.PLL2N = 128; - RCC_PeriphClkInitStruct.PLL2.PLL2P = 2; - RCC_PeriphClkInitStruct.PLL2.PLL2Q = 16; - RCC_PeriphClkInitStruct.PLL2.PLL2R = 2; - RCC_PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - RCC_PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - RCC_PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - RCC_PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - RCC_PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - RCC_PeriphClkInitStruct.PLL3.PLL3M = 6; - RCC_PeriphClkInitStruct.PLL3.PLL3N = 96; - RCC_PeriphClkInitStruct.PLL3.PLL3P = 2; - RCC_PeriphClkInitStruct.PLL3.PLL3Q = 8; - RCC_PeriphClkInitStruct.PLL3.PLL3R = 2; - RCC_PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; - RCC_PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; - RCC_PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - RCC_PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + PeriphClkInitStruct.PLL2.PLL2M = 6; + PeriphClkInitStruct.PLL2.PLL2N = 128; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 16; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 6; + PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 8; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } } @@ -200,4 +194,4 @@ WEAK void SystemClock_Config(void) } // extern "C" #endif -#endif /* ARDUINO_NUCLEO_H503RB */ +#endif /* ARDUINO_NUCLEO_H503RB */ \ No newline at end of file diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h index 66c041da93..dab4a00a69 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -208,4 +208,4 @@ #ifndef SERIAL_PORT_HARDWARE #define SERIAL_PORT_HARDWARE Serial #endif -#endif +#endif \ No newline at end of file From 9d40e8514fed6f9c322d5292ebdf2576d509d8a5 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 04:40:44 +0900 Subject: [PATCH 14/23] align writing style. --- variants/STM32H5xx/H503RBT/ldscript.ld | 78 +++++++++++--------------- 1 file changed, 34 insertions(+), 44 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld index b23f150e0e..c6e7689476 100644 --- a/variants/STM32H5xx/H503RBT/ldscript.ld +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -42,26 +42,22 @@ _Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE - FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +MEMORY { + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH ( rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET } /* Sections */ -SECTIONS -{ +SECTIONS { /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { + .isr_vector : { . = ALIGN(4); KEEP(*(.isr_vector)) /* Startup code */ . = ALIGN(4); - } >FLASH + } > FLASH /* The program code and other data into "FLASH" Rom type memory */ - .text : - { + .text : { . = ALIGN(4); *(.text) /* .text sections (code) */ *(.text*) /* .text* sections (code) */ @@ -74,22 +70,21 @@ SECTIONS . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ - } >FLASH + } > FLASH /* Constant data into "FLASH" Rom type memory */ - .rodata : - { + .rodata : { . = ALIGN(4); *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ . = ALIGN(4); - } >FLASH + } > FLASH - .ARM.extab : { + .ARM.extab : { . = ALIGN(4); *(.ARM.extab* .gnu.linkonce.armextab.*) . = ALIGN(4); - } >FLASH + } > FLASH .ARM : { . = ALIGN(4); @@ -97,43 +92,39 @@ SECTIONS *(.ARM.exidx*) __exidx_end = .; . = ALIGN(4); - } >FLASH + } > FLASH - .preinit_array : - { + .preinit_array : { . = ALIGN(4); PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array*)) PROVIDE_HIDDEN (__preinit_array_end = .); . = ALIGN(4); - } >FLASH + } > FLASH - .init_array : - { + .init_array : { . = ALIGN(4); PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT(.init_array.*))) KEEP (*(.init_array*)) PROVIDE_HIDDEN (__init_array_end = .); . = ALIGN(4); - } >FLASH + } > FLASH - .fini_array : - { + .fini_array : { . = ALIGN(4); PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT(.fini_array.*))) KEEP (*(.fini_array*)) PROVIDE_HIDDEN (__fini_array_end = .); . = ALIGN(4); - } >FLASH + } > FLASH /* Used by the startup to initialize data */ _sidata = LOADADDR(.data); /* Initialized data sections into "RAM" Ram type memory */ - .data : - { + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.data) /* .data sections */ @@ -144,12 +135,11 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end */ - } >RAM AT> FLASH + } > RAM AT > FLASH /* Uninitialized data section into "RAM" Ram type memory */ . = ALIGN(4); - .bss : - { + .bss : { /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; @@ -160,26 +150,26 @@ SECTIONS . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; - } >RAM + } > RAM /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { + ._user_heap_stack : { . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); + PROVIDE(end = .); + PROVIDE(_end = .); . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); - } >RAM + } > RAM /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) + /DISCARD/ : { + libc.a (*) + libm.a (*) + libgcc.a (*) } - .ARM.attributes 0 : { *(.ARM.attributes) } + .ARM.attributes 0 : { + *(.ARM.attributes) + } } \ No newline at end of file From 6615ee4b054786b609249b5319b275885b38ef76 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 04:45:08 +0900 Subject: [PATCH 15/23] fix writing style. --- variants/STM32H5xx/H503RBT/generic_clock.c | 40 +++++++-------- .../H503RBT/variant_NUCLEO_H503RB.cpp | 51 ++++++++++--------- 2 files changed, 46 insertions(+), 45 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index e46cfcb2f3..8247d9f057 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -15,34 +15,34 @@ #include "pins_arduino.h" /** - * @note How to generate PLL clock - * - * HSI 64 MHz ... internal clock - * HSI48 48 MHz ... internal clock for recovery - * LSI 32.768 kHz ... internal clock - * CSI 4 MHz ... internal clock for low power - * - * - * SOURCE / PLLM * PLLN - * - * - * PLL ... MULTIPLEXER / PLLP - * - * default CPU clock: - * 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz - */ +* @note How to generate PLL clock +* +* HSI 64 MHz ... internal clock +* HSI48 48 MHz ... internal clock for recovery +* LSI 32.768 kHz ... internal clock +* CSI 4 MHz ... internal clock for low power +* +* +* SOURCE / PLLM * PLLN +* +* +* PLL ... MULTIPLEXER / PLLP +* +* default CPU clock: +* 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz +*/ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /** Configure the main internal regulator output voltage */ + // Configure the main internal regulator output voltage __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; @@ -66,7 +66,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks */ + // Initializes the CPU, AHB and APB buses clocks RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -78,7 +78,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clock */ + // Initializes the peripherals clock PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index a8f3e21676..acc215047a 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -92,38 +92,38 @@ extern "C" { #endif /** - * @note How to generate PLL clock - * - * HSE 8 MHz ... STLINK MCO output - * HSE 24 MHz ... on-board X3 (default) - * HSE 4~50 MHz ... prepare your own external clock - * LSE 32.768 kHz ... on-board X2 - * HSI 64 MHz ... internal clock - * HSI48 48 MHz ... internal clock for recovery - * LSI 32.768 kHz ... internal clock - * CSI 4 MHz ... internal clock for low power - * - * - * SOURCE / PLLM * PLLN - * - * - * PLL ... MULTIPLEXER / PLLP - * - * default CPU clock: - * 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz - */ +* @note How to generate PLL clock +* +* HSE 8 MHz ... STLINK MCO output +* HSE 24 MHz ... on-board X3 (default) +* HSE 4~50 MHz ... prepare your own external clock +* LSE 32.768 kHz ... on-board X2 +* HSI 64 MHz ... internal clock +* HSI48 48 MHz ... internal clock for recovery +* LSI 32.768 kHz ... internal clock +* CSI 4 MHz ... internal clock for low power +* +* +* SOURCE / PLLM * PLLN +* +* +* PLL ... MULTIPLEXER / PLLP +* +* default CPU clock: +* 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz +*/ WEAK void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /** Configure the main internal regulator output voltage */ + // Configure the main internal regulator output voltage __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ + // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -145,7 +145,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks */ + // Initializes the CPU, AHB and APB buses clocks RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -157,7 +157,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - /** Initializes the peripherals clock */ + // Initializes the peripherals clock PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; @@ -190,8 +190,9 @@ WEAK void SystemClock_Config(void) { } } +// extern "C" #ifdef __cplusplus -} // extern "C" +} #endif #endif /* ARDUINO_NUCLEO_H503RB */ \ No newline at end of file From 60e967a9bf227ac963dc25ac1b1d3901213b5d91 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 15:36:49 +0900 Subject: [PATCH 16/23] remove space. --- variants/STM32H5xx/H503RBT/ldscript.ld | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld index c6e7689476..b0bc831b09 100644 --- a/variants/STM32H5xx/H503RBT/ldscript.ld +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -65,8 +65,8 @@ SECTIONS { *(.glue_7t) /* glue thumb to arm code */ *(.eh_frame) - KEEP (*(.init)) - KEEP (*(.fini)) + KEEP(*(.init)) + KEEP(*(.fini)) . = ALIGN(4); _etext = .; /* define a global symbols at end of code */ @@ -96,27 +96,27 @@ SECTIONS { .preinit_array : { . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); + PROVIDE_HIDDEN(__preinit_array_start = .); + KEEP(*(.preinit_array*)) + PROVIDE_HIDDEN(__preinit_array_end = .); . = ALIGN(4); } > FLASH .init_array : { . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE_HIDDEN(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array*)) + PROVIDE_HIDDEN(__init_array_end = .); . = ALIGN(4); } > FLASH .fini_array : { . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); + PROVIDE_HIDDEN(__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array*)) + PROVIDE_HIDDEN(__fini_array_end = .); . = ALIGN(4); } > FLASH From 29ef7a6ce8a34e10d196912eefaf5cdcbb050d79 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 17:22:52 +0900 Subject: [PATCH 17/23] remove invalid PLL3 clock config. --- variants/STM32H5xx/H503RBT/generic_clock.c | 10 ++++--- .../H503RBT/variant_NUCLEO_H503RB.cpp | 26 +++---------------- 2 files changed, 9 insertions(+), 27 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 8247d9f057..ce67f819ed 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -30,6 +30,8 @@ * * default CPU clock: * 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz +* +* PLL3 supports only H562/H563/H573. */ WEAK void SystemClock_Config(void) { @@ -44,11 +46,11 @@ WEAK void SystemClock_Config(void) { // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -80,11 +82,11 @@ WEAK void SystemClock_Config(void) { // Initializes the peripherals clock PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; + PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index acc215047a..93f47011df 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -159,31 +159,11 @@ WEAK void SystemClock_Config(void) { // Initializes the peripherals clock PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 6; - PeriphClkInitStruct.PLL2.PLL2N = 128; - PeriphClkInitStruct.PLL2.PLL2P = 2; - PeriphClkInitStruct.PLL2.PLL2Q = 16; - PeriphClkInitStruct.PLL2.PLL2R = 2; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ; - PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - PeriphClkInitStruct.PLL3.PLL3M = 6; - PeriphClkInitStruct.PLL3.PLL3N = 96; - PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 8; - PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL2_VCIRANGE_2; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL2_VCORANGE_WIDE; - PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); From 375166de72a96c36579e21a239221bc516a9703f Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 17:38:46 +0900 Subject: [PATCH 18/23] Add comments. --- variants/STM32H5xx/H503RBT/generic_clock.c | 10 ++++------ variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp | 8 ++++---- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index ce67f819ed..690179cd20 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -15,10 +15,10 @@ #include "pins_arduino.h" /** -* @note How to generate PLL clock +* @note [How to generate PLL clock] * * HSI 64 MHz ... internal clock -* HSI48 48 MHz ... internal clock for recovery +* HSI48 48 MHz ... internal clock for USB/RNG with recovery * LSI 32.768 kHz ... internal clock * CSI 4 MHz ... internal clock for low power * @@ -28,10 +28,8 @@ * * PLL ... MULTIPLEXER / PLLP * -* default CPU clock: -* 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz -* -* PLL3 supports only H562/H563/H573. +* - Default CPU clock: 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz +* - PLL3 supports only H562/H563/H573. */ WEAK void SystemClock_Config(void) { diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 93f47011df..bfd02e7456 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -92,14 +92,14 @@ extern "C" { #endif /** -* @note How to generate PLL clock +* @note [How to generate PLL clock] * * HSE 8 MHz ... STLINK MCO output * HSE 24 MHz ... on-board X3 (default) * HSE 4~50 MHz ... prepare your own external clock * LSE 32.768 kHz ... on-board X2 * HSI 64 MHz ... internal clock -* HSI48 48 MHz ... internal clock for recovery +* HSI48 48 MHz ... internal clock for USB/RNG with recovery * LSI 32.768 kHz ... internal clock * CSI 4 MHz ... internal clock for low power * @@ -109,8 +109,8 @@ extern "C" { * * PLL ... MULTIPLEXER / PLLP * -* default CPU clock: -* 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz +* - Default CPU clock: 24(HSE) / 12(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz +* - PLL3 supports only H562/H563/H573. */ WEAK void SystemClock_Config(void) { From 6d591273c67d528af9a7dc9de455b007a822b10e Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 18:22:05 +0900 Subject: [PATCH 19/23] fix clock multiplex. --- variants/STM32H5xx/H503RBT/generic_clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 690179cd20..4f477b93fe 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -28,7 +28,7 @@ * * PLL ... MULTIPLEXER / PLLP * -* - Default CPU clock: 4(CSI) / 1(PLLM) * 125(PLLN) / 2(PLLP) ... 250 MHz +* - Default CPU clock: 4(CSI) / 2(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz * - PLL3 supports only H562/H563/H573. */ @@ -53,8 +53,8 @@ WEAK void SystemClock_Config(void) { RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 2; RCC_OscInitStruct.PLL.PLLR = 2; From 249a206ec234bac5a439cf7016b74308c6614883 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 18:33:41 +0900 Subject: [PATCH 20/23] small fix. --- variants/STM32H5xx/H503RBT/generic_clock.c | 2 +- variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 4f477b93fe..2370257b9b 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -67,7 +67,7 @@ WEAK void SystemClock_Config(void) { } // Initializes the CPU, AHB and APB buses clocks - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index bfd02e7456..152bde1630 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -146,7 +146,7 @@ WEAK void SystemClock_Config(void) { } // Initializes the CPU, AHB and APB buses clocks - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; From 90b60a62555c8fea162665880a7fbf5b1dfc77ac Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sat, 5 Aug 2023 23:30:37 +0900 Subject: [PATCH 21/23] fix comments. --- variants/STM32H5xx/H503RBT/generic_clock.c | 8 ++++---- variants/STM32H5xx/H503RBT/ldscript.ld | 2 +- variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp | 9 ++++----- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 2370257b9b..b7180815b3 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -37,12 +37,12 @@ WEAK void SystemClock_Config(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - // Configure the main internal regulator output voltage + /* Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI; RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -66,7 +66,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - // Initializes the CPU, AHB and APB buses clocks + /* Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -78,7 +78,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - // Initializes the peripherals clock + /* Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; diff --git a/variants/STM32H5xx/H503RBT/ldscript.ld b/variants/STM32H5xx/H503RBT/ldscript.ld index b0bc831b09..3f85cdba2e 100644 --- a/variants/STM32H5xx/H503RBT/ldscript.ld +++ b/variants/STM32H5xx/H503RBT/ldscript.ld @@ -38,7 +38,7 @@ ENTRY(Reset_Handler) /* Highest address of the user mode stack */ _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ -_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Stack_Size = 0x400; /* required amount of stack */ /* Memories definition */ diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 152bde1630..853307d4c8 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -118,12 +118,12 @@ WEAK void SystemClock_Config(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - // Configure the main internal regulator output voltage + /* Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - // Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure + /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; @@ -145,7 +145,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - // Initializes the CPU, AHB and APB buses clocks + /* Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; @@ -157,7 +157,7 @@ WEAK void SystemClock_Config(void) { Error_Handler(); } - // Initializes the peripherals clock + /* Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; @@ -170,7 +170,6 @@ WEAK void SystemClock_Config(void) { } } -// extern "C" #ifdef __cplusplus } #endif From 4a460528bf02782732026380d48772aa8982b1d7 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sun, 6 Aug 2023 01:14:17 +0900 Subject: [PATCH 22/23] revert irrelevant change. --- .../H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp | 52 +++++++------------ .../H563Z(G-I)T/variant_NUCLEO_H563ZI.h | 3 +- 2 files changed, 19 insertions(+), 36 deletions(-) diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp index 7c97ecb07b..e20162a9d0 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp @@ -10,7 +10,6 @@ * ******************************************************************************* */ - #if defined(ARDUINO_NUCLEO_H563ZI) #include "pins_arduino.h" @@ -174,35 +173,17 @@ WEAK void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /** Configure the main internal regulator output voltage */ + /** Configure the main internal regulator output voltage + */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /** - * @note How to generate PLL clock - * - * HSE 8 MHz ... STLINK MCO output (default) - * HSE 25 MHz ... on-board X3 - * HSE 4~50 MHz ... prepare your own external clock - * LSE 32.768 kHz ... on-board X2 - * HSI 64 MHz ... internal clock - * HSI48 48 MHz ... internal clock for recovery - * LSI 32 kHz ... internal clock - * CSI 4 MHz ... internal clock for low power - * - * - * SOURCE / PLLM * PLLN - * - * - * PLL ... MULTIPLEXER / PLLP - * - * default CPU clock: - * 8(HSE) / 4(PLLM) * 250(PLLN) / 2(PLLP) ... 250 MHz - */ - - /** Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON; @@ -218,13 +199,15 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -235,8 +218,11 @@ WEAK void SystemClock_Config(void) Error_Handler(); } - /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + | RCC_PERIPHCLK_USB; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; PeriphClkInitStruct.PLL2.PLL2M = 2; @@ -262,7 +248,6 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } @@ -271,5 +256,4 @@ WEAK void SystemClock_Config(void) #ifdef __cplusplus } // extern "C" #endif - -#endif /* ARDUINO_NUCLEO_H563ZI */ +#endif /* ARDUINO_NUCLEO_H563ZI */ \ No newline at end of file diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h index 1e6c4f3078..86edf8e1a0 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h @@ -10,7 +10,6 @@ * ******************************************************************************* */ - #pragma once /*---------------------------------------------------------------------------- @@ -287,4 +286,4 @@ #ifndef SERIAL_PORT_HARDWARE #define SERIAL_PORT_HARDWARE Serial #endif -#endif +#endif \ No newline at end of file From 936a8cc34cfb0f4fe50aab90b020f264143ad993 Mon Sep 17 00:00:00 2001 From: dojyorin Date: Sun, 6 Aug 2023 01:15:13 +0900 Subject: [PATCH 23/23] revert irrelevant change. --- variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp | 2 +- variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp index e20162a9d0..20211d5437 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.cpp @@ -256,4 +256,4 @@ WEAK void SystemClock_Config(void) #ifdef __cplusplus } // extern "C" #endif -#endif /* ARDUINO_NUCLEO_H563ZI */ \ No newline at end of file +#endif /* ARDUINO_NUCLEO_H563ZI */ diff --git a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h index 86edf8e1a0..0019181e6b 100644 --- a/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h +++ b/variants/STM32H5xx/H563Z(G-I)T/variant_NUCLEO_H563ZI.h @@ -286,4 +286,4 @@ #ifndef SERIAL_PORT_HARDWARE #define SERIAL_PORT_HARDWARE Serial #endif -#endif \ No newline at end of file +#endif