diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h index adfcfd8fac..6349b7fd20 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3614,7 +3613,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5693,7 +5692,7 @@ typedef struct #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) @@ -5778,6 +5777,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define ADC1_COMP_IRQn ADC1_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -5803,4 +5803,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h index a50fb96847..a538cbe81f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3647,7 +3646,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5749,7 +5748,7 @@ typedef struct #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) @@ -5834,6 +5833,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_COMP_IRQn ADC1_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -5859,4 +5859,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h index fa836aa5ff..100a071095 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3658,7 +3657,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5744,7 +5743,7 @@ typedef struct #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) @@ -5830,6 +5829,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_COMP_IRQn ADC1_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -5855,4 +5855,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h index 1acd24ebaa..0c4d289c3b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3687,7 +3686,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5816,7 +5815,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -5906,6 +5905,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_COMP_IRQn ADC1_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -5931,4 +5931,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h index 80ae3f0fb0..e9360b4160 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3723,7 +3722,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5835,7 +5834,7 @@ typedef struct #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) @@ -5920,6 +5919,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -5945,4 +5945,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h index 583b8ff3aa..a056668d39 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3860,7 +3859,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5975,7 +5974,7 @@ typedef struct #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21)) @@ -6060,6 +6059,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_LPUART1_IRQHandler @@ -6085,4 +6085,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h index f082418783..dc83514cef 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3824,7 +3823,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -5976,7 +5975,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -6066,6 +6065,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -6091,4 +6091,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h index 6028b519a1..9890981d4c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3961,7 +3960,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -6116,7 +6115,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -6206,6 +6205,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_LPUART1_IRQHandler @@ -6231,4 +6231,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h index 852d26c263..df8cf52d46 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3952,7 +3951,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -6138,7 +6137,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -6240,6 +6239,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -6266,4 +6266,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h index cc5c806865..941c8f125e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -4315,7 +4314,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7213,7 +7212,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -7322,6 +7321,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler @@ -7348,4 +7348,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h index 77052b9d04..155bd6a953 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3295,7 +3294,7 @@ typedef struct #define LCD_FCR_PON_Pos (4U) #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ -#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */ #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ @@ -4468,7 +4467,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7372,7 +7371,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -7484,6 +7483,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler @@ -7510,4 +7510,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h index 351d1b62d8..23ac2024e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -4452,7 +4451,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7353,7 +7352,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -7462,6 +7461,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler @@ -7488,4 +7488,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h index 5c5a9c1277..da17873f12 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -3423,7 +3422,7 @@ typedef struct #define LCD_FCR_PON_Pos (4U) #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ -#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */ #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ @@ -4603,7 +4602,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7510,7 +7509,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) @@ -7622,6 +7621,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler @@ -7648,4 +7648,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h index a880da97a3..d0df9aea06 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -4067,7 +4066,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -6354,7 +6353,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -6473,6 +6472,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define RNG_LPUART1_IRQHandler LPUART1_IRQHandler @@ -6499,4 +6499,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h index 649749114b..18a980888e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -1464,7 +1463,7 @@ typedef struct #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ -#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ +#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD division ID is 6 */ #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ @@ -4534,7 +4533,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7533,7 +7532,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -7659,6 +7658,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler @@ -7685,4 +7685,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h index a66f1b0af4..af87c0ce07 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -1486,7 +1485,7 @@ typedef struct #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ -#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ +#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD division ID is 6 */ #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ @@ -3440,7 +3439,7 @@ typedef struct #define LCD_FCR_PON_Pos (4U) #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ -#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */ #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ @@ -4685,7 +4684,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7692,7 +7691,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -7821,6 +7820,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler @@ -7847,4 +7847,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h index 376a1cd629..3449d29a4f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -4204,7 +4203,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -6494,7 +6493,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -6613,6 +6612,7 @@ typedef struct #define RCC_CRS_IRQn RCC_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_LPUART1_IRQHandler @@ -6639,4 +6639,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h index 4df3fe4b48..5a1b61eaf8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -1592,7 +1591,7 @@ typedef struct #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ -#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ +#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD division ID is 6 */ #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ @@ -4671,7 +4670,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7673,7 +7672,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -7799,6 +7798,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler @@ -7825,4 +7825,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h index a549a9b9d1..1bbc635359 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,7 +71,7 @@ typedef enum /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ @@ -1614,7 +1613,7 @@ typedef struct #define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */ #define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U) #define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */ -#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */ +#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD division ID is 6 */ #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ @@ -3568,7 +3567,7 @@ typedef struct #define LCD_FCR_PON_Pos (4U) #define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */ -#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */ +#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */ #define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */ #define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */ #define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */ @@ -4822,7 +4821,7 @@ typedef struct #define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ -/*!< RTC congiguration */ +/*!< RTC configuration */ #define RCC_CSR_RTCSEL_Pos (16U) #define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ @@ -7832,7 +7831,7 @@ typedef struct ((INSTANCE) == TIM21) || \ ((INSTANCE) == TIM22)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM21) || \ @@ -7961,6 +7960,7 @@ typedef struct #define RCC_IRQn RCC_CRS_IRQn #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn #define ADC1_IRQn ADC1_COMP_IRQn +#define SVC_IRQn SVCall_IRQn /* Aliases for __IRQHandler */ #define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler @@ -7987,4 +7987,3 @@ typedef struct -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h index 1f03d6dd51..4a550efa6f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h @@ -18,13 +18,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -104,7 +103,7 @@ */ #define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L0xx_CMSIS_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */ -#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ @@ -272,4 +271,3 @@ typedef enum -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h index 8c30248164..5ef3d72ed4 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright(c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -106,4 +105,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md index 77fa1382b0..e0d829b638 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md @@ -1,190 +1,72 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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Accepting Warranty or Additional Liability. + +While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: Copyright [2019] [STMicroelectronics] @@ -192,7 +74,7 @@ you may not use this file except in compliance with the License. You may obtain a copy of the License at - http://www.apache.org/licenses/LICENSE-2.0 + http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md index ca366f6170..e022d05950 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md @@ -1,21 +1,19 @@ -# STM32CubeL0 CMSIS Device MCU Component - -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_l0.svg?color=brightgreen) +# STM32CubeG4 CMSIS Device MCU Component ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. - * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. - * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. - * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product + * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio + * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series + * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... + * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series -Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). - * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. +Two models of publication are proposed for the STM32Cube embedded software : + * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) + * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. ## Description @@ -27,18 +25,11 @@ Details about the content of this release are available in the release note [her ## Compatibility information -In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: - -CMSIS Device L0 | CMSIS Core | Was delivered in the full MCU package ---------------- | ---------- | ------------------------------------- -Tag v1.9.0 | Tag v4.5.0_cm0 | Tag v1.11.0 (and following, if any, till next new tag) -Tag v1.9.1 | Tag v5.4.0_cm0 | Tag v1.12.0 (and following, if any, till next new tag) -Tag v1.9.2 | Tag v5.4.0_cm0 | Tag v1.12.1 (and following, if any, till next new tag) - +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeL0/blob/master/Release_Notes.html) release note. The full **STM32CubeL0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL0). ## Troubleshooting If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l0/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus). +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html index b36c0a1f71..ecfd8d86a5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html @@ -5,33 +5,27 @@ Release Notes for STM32L0xx CMSIS - - + +
-
-

Release Notes for STM32L0xx CMSIS

-

Copyright © 2009-2018 ARM Limited - STMicroelectronics
+

Copyright © 2016 STMicroelectronics

- +
-
-
-

License

-

Licensed by ST under Apache-2.0 license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:

-

Apache License v2.0

Purpose

This driver provides the CMSIS device for the stm32l1xx products. This covers: