RISC-V RVV not enabled despite `-Ctarget-cpu=native` #138789

ThomasHabets · 2025-03-21T14:44:11Z

I tried this code

#![feature(stdarch_riscv_feature_detection)]
fn main() {
    println!("Enabled: {}", cfg!(target_feature="v"));
    println!("Detected: {}", std::arch::is_riscv_feature_detected!("v"));
}

I expected to see this happen

When building with -Ctarget-cpu=native I expect both of these to be true.

Instead, this happened

Both are false. I'm surprised that the first is false because native should mean v is enabled. I'm also surprised that the second is false, because even if not built in, it should be detected at least?

$ RUSTFLAGS="-Ctarget-cpu=native" cargo  +nightly -vvvv run
       Fresh hasvec v0.1.0 (/home/orangepi/scm/hasvec)
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.07s
     Running `CARGO=/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/bin/cargo CARGO_MANIFEST_DIR=/home/orangepi/scm/hasvec CARGO_MANIFEST_PATH=/home/orangepi/scm/hasvec/Cargo.toml CARGO_PKG_AUTHORS='' CARGO_PKG_DESCRIPTION='' CARGO_PKG_HOMEPAGE='' CARGO_PKG_LICENSE='' CARGO_PKG_LICENSE_FILE='' CARGO_PKG_NAME=hasvec CARGO_PKG_README='' CARGO_PKG_REPOSITORY='' CARGO_PKG_RUST_VERSION='' CARGO_PKG_VERSION=0.1.0 CARGO_PKG_VERSION_MAJOR=0 CARGO_PKG_VERSION_MINOR=1 CARGO_PKG_VERSION_PATCH=0 CARGO_PKG_VERSION_PRE='' LD_LIBRARY_PATH='/home/orangepi/scm/hasvec/target/debug/deps:/home/orangepi/scm/hasvec/target/debug:/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/lib/rustlib/riscv64gc-unknown-linux-gnu/lib:/home/orangepi/.rustup/toolchains/nightly-riscv64gc-unknown-linux-gnu/lib:/usr/local/lib:/usr/local/lib:/usr/local/lib:/usr/local/lib' target/debug/hasvec`
Enabled: false
Detected: false

If forcing v feature on, it works as expected:

$ RUSTFLAGS="-Ctarget-cpu=native -Ctarget-feature=+v" cargo +nightly run
warning: unstable feature specified for `-Ctarget-feature`: `v`
  |
  = note: this feature is not stably supported; its behavior can change in the future

warning: `hasvec` (bin "hasvec") generated 1 warning
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.07s
     Running `target/debug/hasvec`
Enabled: true
Detected: true

Meta

$ rustc +nightly --version --verbose
rustc 1.87.0-nightly (1aeb99d24 2025-03-19)
binary: rustc
commit-hash: 1aeb99d248e1b0069110cb03c6f1dcc7b36fd7f3
commit-date: 2025-03-19
host: riscv64gc-unknown-linux-gnu
release: 1.87.0-nightly
LLVM version: 20.1.0

Surely this CPU supports v as a whole? The instructions definitely work. Well, the ones I've tried work. It's an Orange Pi RV2.

$ cat /proc/cpuinfo 
processor       : 0
hart            : 0
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 1
hart            : 1
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 2
hart            : 2
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 3
hart            : 3
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 4
hart            : 4
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 5
hart            : 5
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 6
hart            : 6
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

processor       : 7
hart            : 7
model name      : Ky(R) X1
isa             : rv64imafdcv_zicbom_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zfhmin_zca_zcd_zba_zbb_zbc_zbs_zkt_zve32f_zve32x_zve64d_zve64f_zve64x_zvfh_zvfhmin_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt
mmu             : sv39
uarch           : ky,x60
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200

The text was updated successfully, but these errors were encountered:

ThomasHabets · 2025-03-21T14:58:00Z

I should add: It's my understanding that the v in rv64imafdcv means that the CPU, and therefore target-cpu=native, supports v. And yet rust thinks it doesn't.

bjorn3 · 2025-03-21T15:38:55Z

LLVM is responsible for -Ctarget-cpu=native target feature detection. LLVM likely doesn't recognize your CPU yet.

cuviper · 2025-03-21T16:52:04Z

You can ask rustc which "native" is in effect, e.g. here's mine:

$ rustc --print target-cpus
Available CPUs for this target:
    native                  - Select the CPU of the current host (currently znver5).
...

ThomasHabets · 2025-03-21T17:02:17Z

Generic, apparently:

$ rustc +nightly  --print target-cpus
Available CPUs for this target:
    native              - Select the CPU of the current host (currently generic-rv64).
    generic
    generic-rv32
    generic-rv64        - This is the default target CPU for the current build target (currently riscv64-unknown-linux-gnu).
    mips-p8700
    rocket
    rocket-rv32
    rocket-rv64
    rp2350-hazard3
    sifive-7-series
    sifive-e20
    sifive-e21
    sifive-e24
    sifive-e31
    sifive-e34
    sifive-e76
    sifive-p450
    sifive-p470
    sifive-p550
    sifive-p670
    sifive-s21
    sifive-s51
    sifive-s54
    sifive-s76
    sifive-u54
    sifive-u74
    sifive-x280
    spacemit-x60
    syntacore-scr1-base
    syntacore-scr1-max
    syntacore-scr3-rv32
    syntacore-scr3-rv64
    syntacore-scr4-rv32
    syntacore-scr4-rv64
    syntacore-scr5-rv32
    syntacore-scr5-rv64
    syntacore-scr7
    tt-ascalon-d8
    veyron-v1
    xiangshan-nanhu

So I guess it has specific boards or CPUs, and doesn't at all use the features listed in /proc/cpuinfo?

cuviper · 2025-03-21T17:07:54Z

For -Ctarget-cpu, it needs a named CPU to match. I could imagine something like -Ctarget-features=native being fine-grained for detected features, perhaps.

12101111 · 2025-03-22T19:43:15Z

Currently LLVM can only detect SiFive CPU (by comparing strings from /proc/cpuinfo)

https://github.com/llvm/llvm-project/blob/adcaf1769dea988e13615ef088ff22629966de00/llvm/lib/TargetParser/Host.cpp#L481

Comparing marchid would be better because ky,x60 is the same core as spacemit-x60 but have different brand name in device tree and /proc/cpuinfo.

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVProcessors.td#L561

ThomasHabets added the C-bug Category: This is a bug. label Mar 21, 2025

rustbot added the needs-triage This issue may need triage. Remove it if it has been sufficiently triaged. label Mar 21, 2025

bjorn3 added the A-LLVM Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues. label Mar 21, 2025

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RISC-V RVV not enabled despite `-Ctarget-cpu=native` #138789

RISC-V RVV not enabled despite `-Ctarget-cpu=native` #138789

ThomasHabets commented Mar 21, 2025 •

edited

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ThomasHabets commented Mar 21, 2025

bjorn3 commented Mar 21, 2025

cuviper commented Mar 21, 2025

ThomasHabets commented Mar 21, 2025

cuviper commented Mar 21, 2025

12101111 commented Mar 22, 2025

RISC-V RVV not enabled despite -Ctarget-cpu=native #138789

RISC-V RVV not enabled despite -Ctarget-cpu=native #138789

Comments

ThomasHabets commented Mar 21, 2025 • edited Loading

I tried this code

I expected to see this happen

Instead, this happened

Meta

ThomasHabets commented Mar 21, 2025

bjorn3 commented Mar 21, 2025

cuviper commented Mar 21, 2025

ThomasHabets commented Mar 21, 2025

cuviper commented Mar 21, 2025

12101111 commented Mar 22, 2025

RISC-V RVV not enabled despite `-Ctarget-cpu=native` #138789

RISC-V RVV not enabled despite `-Ctarget-cpu=native` #138789

ThomasHabets commented Mar 21, 2025 •

edited

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