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| 1 | +/*- |
| 2 | + * Copyright 2018 Tarsnap Backup Inc. |
| 3 | + * All rights reserved. |
| 4 | + * |
| 5 | + * Redistribution and use in source and binary forms, with or without |
| 6 | + * modification, are permitted provided that the following conditions |
| 7 | + * are met: |
| 8 | + * 1. Redistributions of source code must retain the above copyright |
| 9 | + * notice, this list of conditions and the following disclaimer. |
| 10 | + * 2. Redistributions in binary form must reproduce the above copyright |
| 11 | + * notice, this list of conditions and the following disclaimer in the |
| 12 | + * documentation and/or other materials provided with the distribution. |
| 13 | + * |
| 14 | + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 15 | + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 16 | + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 17 | + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 18 | + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 19 | + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 20 | + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 21 | + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 22 | + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 23 | + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 24 | + * SUCH DAMAGE. |
| 25 | + */ |
| 26 | + |
| 27 | +#include "php_hash.h" |
| 28 | +#include "php_hash_sha.h" |
| 29 | + |
| 30 | +#if (defined(__i386__) || defined(__x86_64__)) && defined(HAVE_IMMINTRIN_H) |
| 31 | + |
| 32 | +# include <immintrin.h> |
| 33 | + |
| 34 | +# if ZEND_INTRIN_SHA_RESOLVER |
| 35 | +static __m128i be32dec_128(const uint8_t * src) __attribute__((target("ssse3"))); |
| 36 | +void SHA256_Transform_shani(uint32_t state[static restrict 8], const uint8_t block[static restrict 64]) __attribute__((target("ssse3,sha"))); |
| 37 | +# endif |
| 38 | + |
| 39 | +/* Original implementation from libcperciva follows. */ |
| 40 | + |
| 41 | +/** |
| 42 | + * This code uses intrinsics from the following feature sets: |
| 43 | + * SHANI: _mm_sha256msg1_epu32, _mm_sha256msg2_epu32, _mm_sha256rnds2_epu32 |
| 44 | + * SSSE3: _mm_shuffle_epi8, _mm_alignr_epi8 |
| 45 | + * SSE2: Everything else |
| 46 | + * |
| 47 | + * The SSSE3 intrinsics could be avoided at a slight cost by using a few SSE2 |
| 48 | + * instructions in their place; we have not done this since to our knowledge |
| 49 | + * there are presently no CPUs which support the SHANI instruction set but do |
| 50 | + * not support SSSE3. |
| 51 | + */ |
| 52 | + |
| 53 | +/* Load 32-bit big-endian words. */ |
| 54 | +static __m128i |
| 55 | +be32dec_128(const uint8_t * src) |
| 56 | +{ |
| 57 | + const __m128i SHUF = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, 11, |
| 58 | + 4, 5, 6, 7, 0, 1, 2, 3); |
| 59 | + __m128i x; |
| 60 | + |
| 61 | + /* Load four 32-bit words. */ |
| 62 | + x = _mm_loadu_si128((const __m128i *)src); |
| 63 | + |
| 64 | + /* Reverse the order of the bytes in each word. */ |
| 65 | + return (_mm_shuffle_epi8(x, SHUF)); |
| 66 | +} |
| 67 | + |
| 68 | +/* Convert an unsigned 32-bit immediate into a signed value. */ |
| 69 | +#define I32(a) ((UINT32_C(a) >= UINT32_C(0x80000000)) ? \ |
| 70 | + -(int32_t)(UINT32_C(0xffffffff) - UINT32_C(a)) - 1 : (int32_t)INT32_C(a)) |
| 71 | + |
| 72 | +/* Load four unsigned 32-bit immediates into a vector register. */ |
| 73 | +#define IMM4(a, b, c, d) _mm_set_epi32(I32(a), I32(b), I32(c), I32(d)) |
| 74 | + |
| 75 | +/* Run four rounds of SHA256. */ |
| 76 | +#define RND4(S, W, K0, K1, K2, K3) do { \ |
| 77 | + __m128i M; \ |
| 78 | + \ |
| 79 | + /* Add the next four words of message schedule and round constants. */ \ |
| 80 | + M = _mm_add_epi32(W, IMM4(K3, K2, K1, K0)); \ |
| 81 | + \ |
| 82 | + /* Perform two rounds of SHA256, using the low two words in M. */ \ |
| 83 | + S[1] = _mm_sha256rnds2_epu32(S[1], S[0], M); \ |
| 84 | + \ |
| 85 | + /* Shift the two words of M down and perform the next two rounds. */ \ |
| 86 | + M = _mm_srli_si128(M, 8); \ |
| 87 | + S[0] = _mm_sha256rnds2_epu32(S[0], S[1], M); \ |
| 88 | +} while (0) |
| 89 | + |
| 90 | +/* Compute the ith set of four words of message schedule. */ |
| 91 | +#define MSG4(W, i) do { \ |
| 92 | + W[(i + 0) % 4] = _mm_sha256msg1_epu32(W[(i + 0) % 4], W[(i + 1) % 4]); \ |
| 93 | + W[(i + 0) % 4] = _mm_add_epi32(W[(i + 0) % 4], \ |
| 94 | + _mm_alignr_epi8(W[(i + 3) % 4], W[(i + 2) % 4], 4)); \ |
| 95 | + W[(i + 0) % 4] = _mm_sha256msg2_epu32(W[(i + 0) % 4], W[(i + 3) % 4]); \ |
| 96 | +} while (0) |
| 97 | + |
| 98 | +/* Perform 4 rounds of SHA256 and generate more message schedule if needed. */ |
| 99 | +#define RNDMSG(S, W, i, K0, K1, K2, K3) do { \ |
| 100 | + RND4(S, W[i % 4], K0, K1, K2, K3); \ |
| 101 | + if (i < 12) \ |
| 102 | + MSG4(W, i + 4); \ |
| 103 | +} while (0) |
| 104 | + |
| 105 | +/** |
| 106 | + * SHA256_Transform_shani(state, block): |
| 107 | + * Compute the SHA256 block compression function, transforming ${state} using |
| 108 | + * the data in ${block}. This implementation uses x86 SHANI and SSSE3 |
| 109 | + * instructions, and should only be used if CPUSUPPORT_X86_SHANI and _SSSE3 |
| 110 | + * are defined and cpusupport_x86_shani() and _ssse3() return nonzero. |
| 111 | + */ |
| 112 | +void |
| 113 | +SHA256_Transform_shani(uint32_t state[static restrict 8], |
| 114 | + const uint8_t block[static restrict 64]) |
| 115 | +{ |
| 116 | + __m128i S3210, S7654; |
| 117 | + __m128i S0123, S4567; |
| 118 | + __m128i S0145, S2367; |
| 119 | + __m128i W[4]; |
| 120 | + __m128i S[2]; |
| 121 | + |
| 122 | + /* Load state. */ |
| 123 | + S3210 = _mm_loadu_si128((const __m128i *)&state[0]); |
| 124 | + S7654 = _mm_loadu_si128((const __m128i *)&state[4]); |
| 125 | + |
| 126 | + /* Shuffle the 8 32-bit values into the order we need them. */ |
| 127 | + S0123 = _mm_shuffle_epi32(S3210, 0x1B); |
| 128 | + S4567 = _mm_shuffle_epi32(S7654, 0x1B); |
| 129 | + S0145 = _mm_unpackhi_epi64(S4567, S0123); |
| 130 | + S2367 = _mm_unpacklo_epi64(S4567, S0123); |
| 131 | + |
| 132 | + /* Load input block; this is the start of the message schedule. */ |
| 133 | + W[0] = be32dec_128(&block[0]); |
| 134 | + W[1] = be32dec_128(&block[16]); |
| 135 | + W[2] = be32dec_128(&block[32]); |
| 136 | + W[3] = be32dec_128(&block[48]); |
| 137 | + |
| 138 | + /* Initialize working variables. */ |
| 139 | + S[0] = S0145; |
| 140 | + S[1] = S2367; |
| 141 | + |
| 142 | + /* Perform 64 rounds, 4 at a time. */ |
| 143 | + RNDMSG(S, W, 0, 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5); |
| 144 | + RNDMSG(S, W, 1, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5); |
| 145 | + RNDMSG(S, W, 2, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3); |
| 146 | + RNDMSG(S, W, 3, 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174); |
| 147 | + RNDMSG(S, W, 4, 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc); |
| 148 | + RNDMSG(S, W, 5, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da); |
| 149 | + RNDMSG(S, W, 6, 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7); |
| 150 | + RNDMSG(S, W, 7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967); |
| 151 | + RNDMSG(S, W, 8, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13); |
| 152 | + RNDMSG(S, W, 9, 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85); |
| 153 | + RNDMSG(S, W, 10, 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3); |
| 154 | + RNDMSG(S, W, 11, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070); |
| 155 | + RNDMSG(S, W, 12, 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5); |
| 156 | + RNDMSG(S, W, 13, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3); |
| 157 | + RNDMSG(S, W, 14, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208); |
| 158 | + RNDMSG(S, W, 15, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2); |
| 159 | + |
| 160 | + /* Mix local working variables into global state. */ |
| 161 | + S0145 = _mm_add_epi32(S0145, S[0]); |
| 162 | + S2367 = _mm_add_epi32(S2367, S[1]); |
| 163 | + |
| 164 | + /* Shuffle state back to the original word order and store. */ |
| 165 | + S0123 = _mm_unpackhi_epi64(S2367, S0145); |
| 166 | + S4567 = _mm_unpacklo_epi64(S2367, S0145); |
| 167 | + S3210 = _mm_shuffle_epi32(S0123, 0x1B); |
| 168 | + S7654 = _mm_shuffle_epi32(S4567, 0x1B); |
| 169 | + _mm_storeu_si128((__m128i *)&state[0], S3210); |
| 170 | + _mm_storeu_si128((__m128i *)&state[4], S7654); |
| 171 | +} |
| 172 | + |
| 173 | +#endif |
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