SPI_MODE2 and SPI_MODE3 configurations inverted (espressif#345)

It appears that the configurations for `ck_out_edge` were inverted for `SPI_MODE2` and `SPI_MODE3`. You can check the technical reference manual on page 76, table 23 "Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master".

I've check with my oscilloscope that the current configuration is wrong and this fix corrects the issue.

Author: sparks

cores/esp32/esp32-hal-spi.c

@@ -332,11 +332,11 @@ void spiSetDataMode(spi_t * spi, uint8_t dataMode)
         break;
     case SPI_MODE2:
         spi->dev->pin.ck_idle_edge = 1;
-        spi->dev->user.ck_out_edge = 0;
+        spi->dev->user.ck_out_edge = 1;
         break;
     case SPI_MODE3:
         spi->dev->pin.ck_idle_edge = 1;
-        spi->dev->user.ck_out_edge = 1;
+        spi->dev->user.ck_out_edge = 0;
         break;
     case SPI_MODE0:
     default: