Added LWIP, mbedTLS and PSRAM configs to esp32 build target

paclema · paclema · commit 313019ca9a08 · 2022-12-23T11:01:17.000+01:00
diff --git a/configs/builds.json b/configs/builds.json
@@ -98,7 +98,7 @@
 		},
 		{
 			"target": "esp32",
-			"features":["qio_ram"],
+			"features":["qio_ram","LWIP","PSRAM","mbedTLS"],
 			"idf_libs":["qio","80m"],
 			"bootloaders":[
 				["qio","80m"],
diff --git a/configs/defconfig.LWIP b/configs/defconfig.LWIP
@@ -0,0 +1,4 @@
+CONFIG_LWIP_L2_TO_L3_COPY=y
+CONFIG_LWIP_IP_FORWARD=y
+CONFIG_LWIP_IPV4_NAPT=y
+CONFIG_L2_TO_L3_COPY=y
diff --git a/configs/defconfig.PSRAM b/configs/defconfig.PSRAM
@@ -0,0 +1,3 @@
+CONFIG_SPIRAM_BOOT_INIT=y
+CONFIG_SPIRAM_IGNORE_NOTFOUND=y
+CONFIG_SPIRAM_MEMTEST=y
diff --git a/configs/defconfig.mbedTLS b/configs/defconfig.mbedTLS
@@ -0,0 +1,2 @@
+# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set
+CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y

Original file line number	Diff line number	Diff line change
`@@ -98,7 +98,7 @@`
`98`	`98`	`},`
`99`	`99`	`{`
`100`	`100`	`"target": "esp32",`
`101`		`- "features":["qio_ram"],`
	`101`	`+ "features":["qio_ram","LWIP","PSRAM","mbedTLS"],`
`102`	`102`	`"idf_libs":["qio","80m"],`
`103`	`103`	`"bootloaders":[`
`104`	`104`	`["qio","80m"],`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+CONFIG_SPIRAM_BOOT_INIT=y`
	`2`	`+CONFIG_SPIRAM_IGNORE_NOTFOUND=y`
	`3`	`+CONFIG_SPIRAM_MEMTEST=y`
Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set`
	`2`	`+CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y`