AMDGPU should handle SimplifyDemandedVectorElts for more trivial intrinsics

[arsenm]

As a follow up to #128647, more intrinsics should be handled in SimplifyDemandedVectorElts.

This includes: Intrinsic::amdgcn_readlane, Intrinsic::amdgcn_update_dpp, Intrinsic::amdgcn_permlane16, Intrinsic::amdgcn_permlanex16, Intrinsic::amdgcn_permlane64 and Intrinsic::amdgcn_mov_dpp8

This is mostly a matter of adding the intrinsics to the switch, some boilerplate to keep the other immediate operands as they are, and adding tests similar to the ones added in #128647

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

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If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Matt Arsenault (arsenm)

As a follow up to https://github.com//pull/128647, more intrinsics should be handled in SimplifyDemandedVectorElts.

This includes: Intrinsic::amdgcn_readlane, Intrinsic::amdgcn_update_dpp, Intrinsic::amdgcn_permlane16, Intrinsic::amdgcn_permlanex16, Intrinsic::amdgcn_permlane64 and Intrinsic::amdgcn_mov_dpp8

This is mostly a matter of adding the intrinsics to the switch, some boilerplate to keep the other immediate operands as they are, and adding tests similar to the ones added in #128647

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

As a follow up to https://github.com//pull/128647, more intrinsics should be handled in SimplifyDemandedVectorElts.

This includes: Intrinsic::amdgcn_readlane, Intrinsic::amdgcn_update_dpp, Intrinsic::amdgcn_permlane16, Intrinsic::amdgcn_permlanex16, Intrinsic::amdgcn_permlane64 and Intrinsic::amdgcn_mov_dpp8

This is mostly a matter of adding the intrinsics to the switch, some boilerplate to keep the other immediate operands as they are, and adding tests similar to the ones added in #128647

[jayfoad]

I don't see why this is specific to AMDGPU. It should apply to any isTriviallyScalarizable intrinsic.

[DiviyamPathak]

Can I take this up

[DiviyamPathak]

@arsenm hello how do I handle Intrinsic::amdgcn_permlane16, Intrinsic::amdgcn_permlanex16, Intrinsic::amdgcn_permlane64 in switch. I am new contributor sorry

[BaoshanPang]

@arsenm Do we only support the instrinsic from ll to ll? I am gettting this error when trying to see the assembly ouput:

$ ./bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942  /home/bpang/myworks/github/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll
ScalarizeVectorResult #0: t6: v1i16 = llvm.amdgcn.readfirstlane TargetConstant:i64<3139>, t4

LLVM ERROR: Do not know how to scalarize the result of this operator!

PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:

[BaoshanPang]

And it would stuck there if using option -global-sel

$ ./bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -global-isel
/home/bpang/myworks/github/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/simplify-demanded-vector-elts-lane-intrinsics.ll

[arsenm]

1 X vectors are a degenerate case, the backend doesn't treat them as legal. These should use the scalar type instead (i.e replace '<1 x i16>' with 'i16'