[MIPS] Fix miscompiles consecutive half operations

yingopq · yingopq · commit a618b4994822 · 2024-09-27T03:28:26.000-04:00
Use softPromoteHalf legalization for fp16 rather than PromoteFloat. Fix #97975.
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -365,6 +365,8 @@ class TargetRegisterClass;
       return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
     }
 
+    bool softPromoteHalfType() const override { return true; }
+
     bool isJumpTableRelative() const override {
       return getTargetMachine().isPositionIndependent();
     }
diff --git a/llvm/test/CodeGen/Mips/fp16-promote.ll b/llvm/test/CodeGen/Mips/fp16-promote.ll
@@ -62,8 +62,8 @@ define <4 x float> @test_vec_fpext_float(ptr %p) #0 {
 ; CHECK-LIBCALL-LABEL: test_vec_fpext_double:
 ; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
 ; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
-; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
 ; CHECK-LIBCALL: cvt.d.s
+; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)
 ; CHECK-LIBCALL: cvt.d.s
 ; CHECK-LIBCALL: cvt.d.s
 ; CHECK-LIBCALL: %call16(__gnu_h2f_ieee)

Original file line number	Diff line number	Diff line change
`@@ -365,6 +365,8 @@ class TargetRegisterClass;`
`365`	`365`	`return ABI.IsN64() ? Mips::A1_64 : Mips::A1;`
`366`	`366`	`}`
`367`	`367`
	`368`	`+ bool softPromoteHalfType() const override { return true; }`
	`369`	`+`
`368`	`370`	`bool isJumpTableRelative() const override {`
`369`	`371`	`return getTargetMachine().isPositionIndependent();`
`370`	`372`	`}`