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no Glitches, ReInit hardware
1 parent c17b4bd commit 3027a03

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2 files changed

+54
-47
lines changed

2 files changed

+54
-47
lines changed

cores/esp32/esp32-hal-i2c.c

+53-46
Original file line numberDiff line numberDiff line change
@@ -385,10 +385,10 @@ void i2cReset(i2c_t* i2c){
385385

386386
/* Stickbreaker ISR mode debug support
387387
*/
388-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
388+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
389389
#define INTBUFFMAX 64
390-
static uint32_t intBuff[INTBUFFMAX][3];
391-
static uint32_t intPos=0;
390+
static uint32_t intBuff[INTBUFFMAX][3][2];
391+
static uint32_t intPos[2]={0,0};
392392
#endif
393393

394394
/* Stickbreaker ISR mode debug support
@@ -654,13 +654,10 @@ enable txEmpty, filltx fires, but the SM has already sent a bogus byte out the B
654654
overlap is not an issue, just keep them full/empty the status_reg.xx_fifo_cnt
655655
tells the truth. And the INT's fire correctly
656656
*/
657-
bool readEncountered = false; // 12/01/2017 this needs to be removed
658-
// it is nolonger necessary, the fifo's are independent. Run thru the dq's
659-
// until the cmd[] is full or the txFifo is full.
660657
uint16_t a=i2c->queuePos; // currently executing dq,
661658
bool full=!(i2c->dev->status_reg.tx_fifo_cnt<31);
662659
uint8_t cnt;
663-
while((a < i2c->queueCount)&&!(full || readEncountered)){
660+
while((a < i2c->queueCount) && !full){
664661
I2C_DATA_QUEUE_t *tdq = &i2c->dq[a];
665662
cnt=0;
666663
// add to address to fifo ctrl.addr already has R/W bit positioned correctly
@@ -706,22 +703,19 @@ while((a < i2c->queueCount)&&!(full || readEncountered)){
706703
}
707704
}
708705
}
709-
//11/23/2017 overlap tx/rx/tx
710-
// else readEncountered = true;
711-
712-
if(full) readEncountered =false; //tx possibly needs more
713706

714-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
707+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
715708

716709
// update debug buffer tx counts
717-
cnt += intBuff[intPos][1]>>16;
718-
intBuff[intPos][1] = (intBuff[intPos][1]&0xFFFF)|(cnt<<16);
710+
cnt += intBuff[intPos[i2c->num]][1][i2c->num]>>16;
711+
intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF)|(cnt<<16);
712+
719713
#endif
720714

721-
if(!(full||readEncountered)) a++; // check next buffer for tx
715+
if(!full) a++; // check next buffer for tx
722716
}
723717

724-
if((!full) || readEncountered || (a >= i2c->queueCount)){// disable IRQ, the next dq will re-enable it
718+
if(!full || (a >= i2c->queueCount)){// disable IRQ, the next dq will re-enable it
725719
i2c->dev->int_ena.tx_fifo_empty=0;
726720
}
727721

@@ -755,10 +749,10 @@ if(tdq->ctrl.mode==1) { // read
755749
moveCnt = (tdq->length - tdq->position);
756750
}
757751
}
758-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
752+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
759753
// update Debug rxCount
760-
cnt += (intBuff[intPos][1])&&0xffFF;
761-
intBuff[intPos][1] = (intBuff[intPos][1]&0xFFFF0000)|cnt;
754+
cnt += (intBuff[intPos[i2c->num]][1][i2c->num])&&0xffFF;
755+
intBuff[intPos[i2c->num]][1][i2c->num] = (intBuff[intPos[i2c->num]][1][i2c->num]&0xFFFF0000)|cnt;
762756
#endif
763757
}
764758
else {
@@ -822,23 +816,22 @@ if(p_i2c->stage==I2C_DONE){ //get Out
822816
log_e("eject int=%p, ena=%p",activeInt,p_i2c->dev->int_ena.val);
823817
p_i2c->dev->int_ena.val = 0;
824818
p_i2c->dev->int_clr.val = activeInt; //0x1FFF;
825-
// i2cDumpI2c(p_i2c);
826-
// i2cDumpInts();
827819
return;
828820
}
829821
while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important, don't change
830-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
831-
if(activeInt==(intBuff[intPos][0]&0x1fff)){
832-
intBuff[intPos][0] = (((intBuff[intPos][0]>>16)+1)<<16)|activeInt;
822+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
823+
if(activeInt==(intBuff[intPos[p_i2c->num]][0][p_i2c->num]&0x1fff)){
824+
intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (((intBuff[intPos[p_i2c->num]][0][p_i2c->num]>>16)+1)<<16)|activeInt;
833825
}
834826
else{
835-
intPos++;
836-
intPos %= INTBUFFMAX;
837-
intBuff[intPos][0]=(1<<16)|activeInt;
838-
intBuff[intPos][1] = 0;
827+
intPos[p_i2c->num]++;
828+
intPos[p_i2c->num] %= INTBUFFMAX;
829+
intBuff[intPos[p_i2c->num]][0][p_i2c->num] = (1<<16) | activeInt;
830+
intBuff[intPos[p_i2c->num]][1][p_i2c->num] = 0;
839831
}
840832

841-
intBuff[intPos][2] = xTaskGetTickCountFromISR(); // when IRQ fired
833+
intBuff[intPos[p_i2c->num]][2][p_i2c->num] = xTaskGetTickCountFromISR(); // when IRQ fired
834+
842835
#endif
843836
uint32_t oldInt =activeInt;
844837

@@ -949,13 +942,13 @@ while (activeInt != 0) { // Ordering of 'if(activeInt)' statements is important,
949942
}
950943
}
951944

952-
void i2cDumpInts(){
953-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
945+
void i2cDumpInts(uint8_t num){
946+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
954947
uint32_t b;
955-
log_e("row count INTR TX RX");
948+
log_e("%u row count INTR TX RX",num);
956949
for(uint32_t a=1;a<=INTBUFFMAX;a++){
957-
b=(a+intPos)%INTBUFFMAX;
958-
if(intBuff[b][0]!=0) log_e("[%02d] 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x",b,((intBuff[b][0]>>16)&0xFFFF),(intBuff[b][0]&0xFFFF),((intBuff[b][1]>>16)&0xFFFF),(intBuff[b][1]&0xFFFF),intBuff[b][2]);
950+
b=(a+intPos[num])%INTBUFFMAX;
951+
if(intBuff[b][0][num]!=0) log_e("[%02d] 0x%04x 0x%04x 0x%04x 0x%04x 0x%08x",b,((intBuff[b][0][num]>>16)&0xFFFF),(intBuff[b][0][num]&0xFFFF),((intBuff[b][1][num]>>16)&0xFFFF),(intBuff[b][1][num]&0xFFFF),intBuff[b][2][num]);
959952
}
960953
#else
961954
log_n("enable Core Debug Level \"Error\"");
@@ -986,9 +979,13 @@ I2C_MUTEX_LOCK();
986979
*/
987980
i2c->stage = I2C_DONE; // until ready
988981

989-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
990-
memset(intBuff,0,sizeof(intBuff));
991-
intPos=0;
982+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
983+
for(uint16_t i=0;i<INTBUFFMAX;i++){
984+
intBuff[i][0][i2c->num] = 0;
985+
intBuff[i][1][i2c->num] = 0;
986+
intBuff[i][2][i2c->num] = 0;
987+
}
988+
intPos[i2c->num] = 0;
992989
#endif
993990
// EventGroup is used to signal transmisison completion from ISR
994991
// not always reliable. Sometimes, the FreeRTOS scheduler is maxed out and refuses request
@@ -1075,9 +1072,19 @@ i2c->dev->int_ena.val =
10751072
I2C_TXFIFO_EMPTY_INT_ENA | // (BIT(1)) triggers fillTxFifo()
10761073
I2C_RXFIFO_FULL_INT_ENA; // (BIT(0)) trigger emptyRxFifo()
10771074

1078-
if(!i2c->intr_handle){ // create ISR I2C_0 only,
1079-
// log_e("create ISR");
1080-
uint32_t ret = esp_intr_alloc(ETS_I2C_EXT0_INTR_SOURCE, 0, &i2c_isr_handler_default, i2c, &i2c->intr_handle);
1075+
if(!i2c->intr_handle){ // create ISR for either peripheral
1076+
log_i("create ISR");
1077+
uint32_t ret;
1078+
switch(i2c->num){
1079+
case 0:
1080+
ret = esp_intr_alloc(ETS_I2C_EXT0_INTR_SOURCE, 0, &i2c_isr_handler_default, i2c, &i2c->intr_handle);
1081+
break;
1082+
case 1:
1083+
ret = esp_intr_alloc(ETS_I2C_EXT1_INTR_SOURCE, 0, &i2c_isr_handler_default, i2c, &i2c->intr_handle);
1084+
break;
1085+
default :;
1086+
}
1087+
10811088
if(ret!=ESP_OK){
10821089
log_e("install interrupt handler Failed=%d",ret);
10831090
I2C_MUTEX_UNLOCK();
@@ -1113,11 +1120,11 @@ if(i2c->exitCode!=eBits){ // try to recover from O/S failure
11131120
}
11141121

11151122
if(!(eBits==EVENT_DONE)&&(eBits&~(EVENT_ERROR_NAK|EVENT_ERROR_DATA_NAK|EVENT_ERROR|EVENT_DONE))){ // not only Done, therefore error, exclude ADDR NAK, DATA_NAK
1116-
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
1123+
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_INFO
11171124
i2cDumpI2c(i2c);
1118-
i2cDumpInts();
1125+
i2cDumpInts(i2c->num);
11191126
#else
1120-
log_n("I2C exitCode=%u",eBits);
1127+
log_n("I2C exitCode=0x%x",eBits);
11211128
#endif
11221129
}
11231130

@@ -1128,7 +1135,7 @@ if(eBits&EVENT_DONE){ // no gross timeout
11281135
// expected can be zero due to small packets
11291136
log_e("TimeoutRecovery: expected=%ums, actual=%ums",expected,(tAfter-tBefore));
11301137
i2cDumpI2c(i2c);
1131-
i2cDumpInts();
1138+
i2cDumpInts(i2c->num);
11321139
}
11331140
#endif
11341141
switch(i2c->error){
@@ -1164,7 +1171,7 @@ else { // GROSS timeout, shutdown ISR , report Timeout
11641171
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
11651172
log_e(" Busy Timeout start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error);
11661173
i2cDumpI2c(i2c);
1167-
i2cDumpInts();
1174+
i2cDumpInts(i2c->num);
11681175
#endif
11691176
}
11701177
else { // just a timeout, some data made it out or in.
@@ -1174,7 +1181,7 @@ else { // GROSS timeout, shutdown ISR , report Timeout
11741181
#if ARDUHAL_LOG_LEVEL >= ARDUHAL_LOG_LEVEL_ERROR
11751182
log_e(" Gross Timeout Dead start=0x%x, end=0x%x, =%d, max=%d error=%d",tBefore,tAfter,(tAfter-tBefore),ticksTimeOut,i2c->error);
11761183
i2cDumpI2c(i2c);
1177-
i2cDumpInts();
1184+
i2cDumpInts(i2c->num);
11781185
#endif
11791186
}
11801187
}

cores/esp32/esp32-hal-i2c.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ i2c_err_t i2cAddQueueRead(i2c_t *i2c, uint16_t i2cDeviceAddr, uint8_t *dataPtr,
169169
i2c_err_t i2cFreeQueue(i2c_t *i2c);
170170
i2c_err_t i2cReleaseISR(i2c_t *i2c);
171171
//stickbreaker debug support
172-
void i2cDumpInts();
172+
void i2cDumpInts(uint8_t num);
173173
void i2cDumpI2c(i2c_t *i2c);
174174

175175
#ifdef __cplusplus

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