diff --git a/build-manual/index.html b/build-manual/index.html index aeade3e..553096d 100644 --- a/build-manual/index.html +++ b/build-manual/index.html @@ -42,7 +42,7 @@
Intel® XED Build Guide
-

April 2024

+

September 2024

Introduction

Intel® XED can be built with many compilers:

@@ -1398,6 +1378,44 @@

Returns true if the instruction has a SIB byte.

+

+
+ +

◆ xed_operand_values_ignored_branch_not_taken_hint()

+ +
+
+ + + + + + + + +
xed_bool_t xed_operand_values_ignored_branch_not_taken_hint (const xed_operand_values_tp)
+
+

Returns true if instruction has ignored 0x2E prefix

+ +
+
+ +

◆ xed_operand_values_ignored_branch_taken_hint()

+ +
+
+ + + + + + + + +
xed_bool_t xed_operand_values_ignored_branch_taken_hint (const xed_operand_values_tp)
+
+

Returns true if instruction has ignored 0x3E prefix

+
@@ -1495,26 +1513,6 @@

-

◆ xed_operand_values_is_prefetch()

- -
-
- - - - - - - - -
XED_DLL_EXPORT xed_bool_t xed_operand_values_is_prefetch (const xed_operand_values_tp)
-
-


-

-
diff --git a/ref-manual/group__OPERANDS.js b/ref-manual/group__OPERANDS.js index cd55263..94361da 100644 --- a/ref-manual/group__OPERANDS.js +++ b/ref-manual/group__OPERANDS.js @@ -38,7 +38,6 @@ var group__OPERANDS = [ "xed_operand_values_has_66_prefix", "group__OPERANDS.html#gab0dbe428e16fea4d11c2498ce23eb489", null ], [ "xed_operand_values_has_address_size_prefix", "group__OPERANDS.html#gae3a5a7fec6f106c2f00029920cc5fa27", null ], [ "xed_operand_values_has_branch_displacement", "group__OPERANDS.html#ga4ad34793ee0b41476c742182fa625caa", null ], - [ "xed_operand_values_has_disp", "group__OPERANDS.html#gab0d49de82df18773d120efd1b5facb96", null ], [ "xed_operand_values_has_displacement", "group__OPERANDS.html#ga35cc443e8ea463cfe087ed5ad3287de5", null ], [ "xed_operand_values_has_immediate", "group__OPERANDS.html#ga7be044800ef408c7043e7c443c8c9702", null ], [ "xed_operand_values_has_lock_prefix", "group__OPERANDS.html#gaa2538c59d88956f3eb10a67ee935f468", null ], @@ -51,11 +50,12 @@ var group__OPERANDS = [ "xed_operand_values_has_rexw_prefix", "group__OPERANDS.html#gaf2906d60081b02aa491198720295dae4", null ], [ "xed_operand_values_has_segment_prefix", "group__OPERANDS.html#ga83152cba3e67d2753d01bff505012c6e", null ], [ "xed_operand_values_has_sib_byte", "group__OPERANDS.html#ga87e7a1bf6ad7fc739d57334c60da30f3", null ], + [ "xed_operand_values_ignored_branch_not_taken_hint", "group__OPERANDS.html#ga5ad363d31f2bb56a184e050f9d726574", null ], + [ "xed_operand_values_ignored_branch_taken_hint", "group__OPERANDS.html#ga2a003fcb55418bbb7bab8936fcb56237", null ], [ "xed_operand_values_init", "group__OPERANDS.html#ga5b6cd7ad6c5c853c8ae1179df71fe6d1", null ], [ "xed_operand_values_init_keep_mode", "group__OPERANDS.html#gae001db086cdf4d03d81301448133bbb1", null ], [ "xed_operand_values_init_set_mode", "group__OPERANDS.html#ga6eb60207e9dc46671fc89b83c10071aa", null ], [ "xed_operand_values_is_nop", "group__OPERANDS.html#ga1e19112db73aea4cb91a8682cf7c1dac", null ], - [ "xed_operand_values_is_prefetch", "group__OPERANDS.html#gaf1b7e94aa1e7bc4a75d707d31ca66254", null ], [ "xed_operand_values_lockable", "group__OPERANDS.html#gad6f0386f64431371591ce8c6cb914e7f", null ], [ "xed_operand_values_mandatory_66_prefix", "group__OPERANDS.html#ga8447fdb1d49250e5a38ac9dd5b62e75f", null ], [ "xed_operand_values_memop_without_modrm", "group__OPERANDS.html#ga85403c1bc57896f0cc1f0c5d9abd2274", null ], diff --git a/ref-manual/group__PRINT.js b/ref-manual/group__PRINT.js index 142eb2c..0bb9f5d 100644 --- a/ref-manual/group__PRINT.js +++ b/ref-manual/group__PRINT.js @@ -1,6 +1,7 @@ var group__PRINT = [ [ "xed_format_options_t", "structxed__format__options__t.html", [ + [ "emit_ignored_branch_taken_hint", "structxed__format__options__t.html#ae241ede0d62ea594d6cb4d3b2b3e8460", null ], [ "hex_address_before_symbolic_name", "structxed__format__options__t.html#a9859337bb1e80b9406ef029e2e88a388", null ], [ "lowercase_hex", "structxed__format__options__t.html#aa4854459a1abec9171c9065e164edecf", null ], [ "no_sign_extend_signed_immediates", "structxed__format__options__t.html#a52f1af3c6153aea31d80aa837d8fd075", null ], diff --git a/ref-manual/group__SMALLEXAMPLES.html b/ref-manual/group__SMALLEXAMPLES.html index 09d14bb..8930e38 100644 --- a/ref-manual/group__SMALLEXAMPLES.html +++ b/ref-manual/group__SMALLEXAMPLES.html @@ -122,7 +122,7 @@
unsigned char itext[15] = { 0xf, 0x85, 0x99, 0x00, 0x00, 0x00 };
// initialize the XED tables -- one time.
- +
// The state of the machine -- required for decoding
if (long_mode) {
@@ -815,7 +815,7 @@
#if defined(XED_CET)
unsigned int cet_mode=0;
#endif
- +
xed_state_zero(&dstate);
first_argv = 1;
@@ -1158,7 +1158,7 @@
@ XED_OPERAND_REG6
Definition: xed-operand-enum.h:265
@ XED_OPERAND_REG9
Definition: xed-operand-enum.h:268
@ XED_OPERAND_RELBR
Definition: xed-operand-enum.h:269
-
xed_isa_set_enum_t
Definition: xed-isa-set-enum.h:252
+
xed_isa_set_enum_t
Definition: xed-isa-set-enum.h:308
xed_machine_mode_enum_t mmode
real architected machine modes
Definition: xed-state.h:41
XED_DLL_EXPORT xed_reg_class_enum_t xed_reg_class(xed_reg_enum_t r)
Returns the register class of the given input register.
@ XED_OPERAND_IMM1
Definition: xed-operand-enum.h:207
@@ -1208,7 +1208,7 @@
static const XED_INLINE xed_operand_values_t * xed_decoded_inst_operands_const(const xed_decoded_inst_t *p)
Definition: xed-decoded-inst-api.h:147
XED_DLL_EXPORT xed_bool_t xed_operand_values_has_address_size_prefix(const xed_operand_values_t *p)
XED_DLL_EXPORT xed_uint_t xed_decoded_inst_get_branch_displacement_width_bits(const xed_decoded_inst_t *p)
-
xed_iclass_enum_t
Definition: xed-iclass-enum.h:1886
+
xed_iclass_enum_t
Definition: xed-iclass-enum.h:2002
XED_DLL_EXPORT unsigned int xed_decoded_inst_operand_elements(const xed_decoded_inst_t *p, unsigned int operand_index)
Return the number of element in the operand (for SSE and AVX operands)
XED_DLL_EXPORT xed_operand_element_type_enum_t xed_decoded_inst_operand_element_type(const xed_decoded_inst_t *p, unsigned int operand_index)
Return the type of an element of type xed_operand_element_type_enum_t (for SSE and AVX operands)
const XED_DLL_EXPORT char * xed_iclass_enum_t2str(const xed_iclass_enum_t p)
This converts strings to xed_iclass_enum_t types.
@@ -1216,7 +1216,6 @@
@ XED_OPERAND_PTR
Definition: xed-operand-enum.h:256
@ XED_OPERAND_MEM1
Definition: xed-operand-enum.h:219
const XED_DLL_EXPORT char * xed_chip_enum_t2str(const xed_chip_enum_t p)
This converts strings to xed_chip_enum_t types.
-
void XED_DLL_EXPORT xed_tables_init(void)
#define XED_STATIC_CAST(x, y)
Definition: xed-portability.h:27
#define XED_REINTERPRET_CAST(x, y)
Definition: xed-portability.h:28
static XED_INLINE xed_bits_t xed3_operand_get_roundc(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:1639
@@ -1224,10 +1223,10 @@
static XED_INLINE xed_bits_t xed3_operand_get_reg(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:839
XED_DLL_EXPORT xed_bool_t xed_classify_sse(const xed_decoded_inst_t *d)
#define XED_FMT_LX16
Definition: xed-portability.h:137
-
xed_cpuid_group_enum_t
Definition: xed-cpuid-group-enum.h:284
+
xed_cpuid_group_enum_t
Definition: xed-cpuid-group-enum.h:344
static XED_INLINE xed_uint_t xed_decoded_inst_get_machine_mode_bits(const xed_decoded_inst_t *p)
Definition: xed-decoded-inst-api.h:314
unsigned int xed_bool_t
Definition: xed-types.h:55
-
xed_chip_enum_t
Definition: xed-chip-enum.h:100
+
xed_chip_enum_t
Definition: xed-chip-enum.h:101
static XED_INLINE xed_bits_t xed3_operand_get_rexb4(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:743
const XED_DLL_EXPORT char * xed_operand_visibility_enum_t2str(const xed_operand_visibility_enum_t p)
This converts strings to xed_operand_visibility_enum_t types.
const XED_DLL_EXPORT xed_flag_set_t * xed_simple_flag_get_undefined_flag_set(const xed_simple_flag_t *p)
@@ -1238,7 +1237,7 @@
XED_DLL_EXPORT xed_bool_t xed_simple_flag_get_must_write(const xed_simple_flag_t *p)
static XED_INLINE xed_bits_t xed3_operand_get_rexw(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:703
XED_DLL_EXPORT xed_int32_t xed_decoded_inst_get_signed_immediate(const xed_decoded_inst_t *p)
-
xed_cpuid_rec_enum_t
Definition: xed-cpuid-rec-enum.h:159
+
xed_cpuid_rec_enum_t
Definition: xed-cpuid-rec-enum.h:171
static XED_INLINE xed_category_enum_t xed_decoded_inst_get_category(const xed_decoded_inst_t *p)
Definition: xed-decoded-inst-api.h:54
XED_DLL_EXPORT xed_uint_t xed_decoded_inst_avx512_dest_elements(const xed_decoded_inst_t *p)
Returns the maximum number elements processed for an AVX512 vector instruction.
const XED_DLL_EXPORT char * xed_error_enum_t2str(const xed_error_enum_t p)
This converts strings to xed_error_enum_t types.
@@ -1247,7 +1246,7 @@
XED_DLL_EXPORT xed_bool_t xed_get_cpuid_rec(xed_cpuid_rec_enum_t cpuid_bit, xed_cpuid_rec_t *p)
provides the details of the CPUID specification, if the enumeration value is not sufficient....
static XED_INLINE xed_exception_enum_t xed_inst_exception(const xed_inst_t *p)
Definition: xed-inst.h:359
static XED_INLINE xed_bits_t xed3_operand_get_nominal_opcode(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:1375
-
xed_exception_enum_t
Definition: xed-exception-enum.h:105
+
xed_exception_enum_t
Definition: xed-exception-enum.h:114
@ XED_OPERAND_AGEN
Definition: xed-operand-enum.h:171
xed_error_enum_t
Definition: xed-error-enum.h:48
Definition: xed-inst.h:53
@@ -1266,7 +1265,7 @@
XED_DLL_EXPORT xed_uint_t xed_decoded_inst_get_scale(const xed_decoded_inst_t *p, unsigned int mem_idx)
static const XED_INLINE xed_inst_t * xed_decoded_inst_inst(const xed_decoded_inst_t *p)
Definition: xed-decoded-inst-api.h:46
XED_DLL_EXPORT xed_uint_t xed_decoded_inst_get_nprefixes(const xed_decoded_inst_t *p)
-
@ XED_CHIP_INVALID
Definition: xed-chip-enum.h:101
+
@ XED_CHIP_INVALID
Definition: xed-chip-enum.h:102
XED_DLL_EXPORT xed_bool_t xed_decoded_inst_uses_rflags(const xed_decoded_inst_t *p)
This returns 1 if the flags are read or written.
XED_DLL_EXPORT xed_bool_t xed_classify_amx(const xed_decoded_inst_t *d)
static XED_INLINE void xed_state_zero(xed_state_t *p)
clear the xed_state_t
Definition: xed-state.h:88
@@ -1303,6 +1302,7 @@
static XED_INLINE xed_uint8_t xed_decoded_inst_get_second_immediate(const xed_decoded_inst_t *p)
Definition: xed-decoded-inst-api.h:521
static XED_INLINE void xed3_operand_set_cet(xed_decoded_inst_t *d, xed_bits_t opval)
Definition: xed-operand-accessors.h:1531
@ XED_MACHINE_MODE_LONG_64
64b operating mode
Definition: xed-machine-mode-enum.h:37
+
XED_DLL_EXPORT void xed_tables_init(void)
static XED_INLINE xed_bits_t xed3_operand_get_rexb(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:727
xed_uint32_t of
Definition: xed-flags.h:38
xed_uint32_t leaf
cpuid leaf
Definition: xed-cpuid-rec.h:33
@@ -1315,16 +1315,16 @@
@ XED_OPERAND_REG3
Definition: xed-operand-enum.h:262
Definition: xed-flags.h:35
@ XED_ATTRIBUTE_APX_NF
Definition: xed-attribute-enum.h:136
-
@ XED_EXCEPTION_INVALID
Definition: xed-exception-enum.h:106
+
@ XED_EXCEPTION_INVALID
Definition: xed-exception-enum.h:115
XED_DLL_EXPORT xed_operand_action_enum_t xed_decoded_inst_operand_action(const xed_decoded_inst_t *p, unsigned int operand_index)
Interpret the operand action in light of AVX512 masking and zeroing/merging.
XED_DLL_EXPORT xed_bool_t xed_operand_values_has_66_prefix(const xed_operand_values_t *p)
XED_DLL_EXPORT xed_bool_t xed_operand_values_branch_not_taken_hint(const xed_operand_values_t *p)
-
@ XED_CPUID_GROUP_INVALID
Definition: xed-cpuid-group-enum.h:285
+
@ XED_CPUID_GROUP_INVALID
Definition: xed-cpuid-group-enum.h:345
XED_DLL_EXPORT unsigned int xed_decoded_inst_get_memop_address_width(const xed_decoded_inst_t *p, xed_uint_t memop_idx)
Returns the addressing width in bits (16,32,64) for MEM0 (memop_idx==0) or MEM1 (memop_idx==1).
xed_attribute_enum_t
Definition: xed-attribute-enum.h:132
const XED_DLL_EXPORT char * xed_operand_action_enum_t2str(const xed_operand_action_enum_t p)
This converts strings to xed_operand_action_enum_t types.
-
@ XED_CPUID_REC_INVALID
Definition: xed-cpuid-rec-enum.h:160
+
@ XED_CPUID_REC_INVALID
Definition: xed-cpuid-rec-enum.h:172
Definition: xed-decoded-inst.h:53
static XED_INLINE xed_bits_t xed3_operand_get_rm(const xed_decoded_inst_t *d)
Definition: xed-operand-accessors.h:855
XED_DLL_EXPORT xed_bool_t xed_operand_values_mandatory_66_prefix(const xed_operand_values_t *p)
diff --git a/ref-manual/index.html b/ref-manual/index.html index 5ada7d0..ac2c3f0 100644 --- a/ref-manual/index.html +++ b/ref-manual/index.html @@ -85,7 +85,7 @@
Intel® X86 Encoder Decoder User Guide
-

April 2024

+

September 2024

Introduction

Intel® XED is an acronym for X86 Encoder Decoder. The latter part is pronounced like the (British) English "z".

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index 88f24f8..1ba8c57 100644 --- a/ref-manual/structxed__format__options__t.html +++ b/ref-manual/structxed__format__options__t.html @@ -95,6 +95,9 @@ + + + @@ -124,6 +127,22 @@

Options for the disasembly formatting functions.

Set once during initialization by a calling xed_format_set_options

Field Documentation

+ +

◆ emit_ignored_branch_taken_hint

+ +
+
+

Data Fields

xed_bool_t emit_ignored_branch_taken_hint
 emit ignored branch hints More...
 
unsigned int hex_address_before_symbolic_name
 by default, XED prints the hex address before any symbolic name for branch targets. More...
 
+ + + +
xed_bool_t emit_ignored_branch_taken_hint
+
+ +

emit ignored branch hints

+ +
+

◆ hex_address_before_symbolic_name

diff --git a/ref-manual/structxed__format__options__t.js b/ref-manual/structxed__format__options__t.js index 2dca0a0..9462624 100644 --- a/ref-manual/structxed__format__options__t.js +++ b/ref-manual/structxed__format__options__t.js @@ -1,5 +1,6 @@ var structxed__format__options__t = [ + [ "emit_ignored_branch_taken_hint", "structxed__format__options__t.html#ae241ede0d62ea594d6cb4d3b2b3e8460", null ], [ "hex_address_before_symbolic_name", "structxed__format__options__t.html#a9859337bb1e80b9406ef029e2e88a388", null ], [ "lowercase_hex", "structxed__format__options__t.html#aa4854459a1abec9171c9065e164edecf", null ], [ "no_sign_extend_signed_immediates", "structxed__format__options__t.html#a52f1af3c6153aea31d80aa837d8fd075", null ], diff --git a/ref-manual/xed-build-defines_8h.html b/ref-manual/xed-build-defines_8h.html index 7772735..1324020 100644 --- a/ref-manual/xed-build-defines_8h.html +++ b/ref-manual/xed-build-defines_8h.html @@ -112,7 +112,7 @@   #define XED_SUPPORTS_WBNOINVD   -#define XED_VERSION   "v2024.05.20" +#define XED_VERSION   "v2024.11.04.external"   #define XED_VIA_ENABLED   @@ -279,7 +279,7 @@

- +
#define XED_VERSION   "v2024.05.20"#define XED_VERSION   "v2024.11.04.external"

+ + +

◆ XED_CHIP_DIAMOND_RAPIDS_DEFINED

+ +
+
+ + + + +
#define XED_CHIP_DIAMOND_RAPIDS_DEFINED   1
+
+
@@ -1524,6 +1542,7 @@

XED_CHIP_SAPPHIRE_RAPIDS  XED_CHIP_EMERALD_RAPIDS  XED_CHIP_GRANITE_RAPIDS  +XED_CHIP_DIAMOND_RAPIDS  XED_CHIP_SIERRA_FOREST  XED_CHIP_CLEARWATER_FOREST  XED_CHIP_ARROW_LAKE  diff --git a/ref-manual/xed-chip-enum_8h.js b/ref-manual/xed-chip-enum_8h.js index 394f121..a9cad97 100644 --- a/ref-manual/xed-chip-enum_8h.js +++ b/ref-manual/xed-chip-enum_8h.js @@ -18,6 +18,7 @@ var xed_chip_enum_8h = [ "XED_CHIP_CLEARWATER_FOREST_DEFINED", "xed-chip-enum_8h.html#a1cd5d2a695cab334b6b1c88e42e62b4b", null ], [ "XED_CHIP_COMET_LAKE_DEFINED", "xed-chip-enum_8h.html#a52f95526aadb7a035380598fbf25f13f", null ], [ "XED_CHIP_COOPER_LAKE_DEFINED", "xed-chip-enum_8h.html#a7ba49c0960d1496d8949a8e80f60beb9", null ], + [ "XED_CHIP_DIAMOND_RAPIDS_DEFINED", "xed-chip-enum_8h.html#ac32f600e2f83482be49d1bb4be0a5d47", null ], [ "XED_CHIP_EMERALD_RAPIDS_DEFINED", "xed-chip-enum_8h.html#a97aaa4dc67efc5c3b4d3008f3cf1950b", null ], [ "XED_CHIP_FUTURE_DEFINED", "xed-chip-enum_8h.html#a99d0a5744be906e3abf250e672e30a7e", null ], [ "XED_CHIP_GOLDMONT_DEFINED", "xed-chip-enum_8h.html#a40670a7fc7db0b5866e107a28b4641a6", null ], @@ -141,6 +142,7 @@ var xed_chip_enum_8h = [ "XED_CHIP_SAPPHIRE_RAPIDS", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301aaa5a6ba8d0b59f30e85f4d24f36dfca5", null ], [ "XED_CHIP_EMERALD_RAPIDS", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301aa65307b9254af347fd9463bd92d7115d", null ], [ "XED_CHIP_GRANITE_RAPIDS", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301ab0d31d5d60034001f637bd91d0e9b33b", null ], + [ "XED_CHIP_DIAMOND_RAPIDS", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301ab37c8ca394040200234f18d86e77bc23", null ], [ "XED_CHIP_SIERRA_FOREST", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301a854acc2cd31e1e7dbee62d05f60ef0f7", null ], [ "XED_CHIP_CLEARWATER_FOREST", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301a3fec0d1f78da230c1f2287ca9379d181", null ], [ "XED_CHIP_ARROW_LAKE", "xed-chip-enum_8h.html#ae77c7c405380680ef2414d50d67f1301aafcbe20ded104a28c14d5bf0960644b4", null ], diff --git a/ref-manual/xed-chip-features_8h.html b/ref-manual/xed-chip-features_8h.html index ef89b81..f4d4514 100644 --- a/ref-manual/xed-chip-features_8h.html +++ b/ref-manual/xed-chip-features_8h.html @@ -101,7 +101,7 @@ - +

Macros

#define XED_FEATURE_VECTOR_MAX   6
#define XED_FEATURE_VECTOR_MAX   7
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -149,6 +177,8 @@ + + @@ -157,6 +187,16 @@ + + + + + + + + + + @@ -179,6 +219,14 @@ + + + + + + + + @@ -191,6 +239,8 @@ + + @@ -207,6 +257,12 @@ + + + + + + @@ -235,6 +291,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -283,6 +375,24 @@ + + + + + + + + + + + + + + + + + + @@ -495,8 +605,12 @@ + + + + @@ -545,6 +659,12 @@ + + + + + + @@ -619,16 +739,44 @@
  XED_CPUID_GROUP_AES,
+  XED_CPUID_GROUP_AMX_AVX512_AVX10, +
  XED_CPUID_GROUP_AMX_BF16,
+  XED_CPUID_GROUP_AMX_BF16_AVX10, +
  XED_CPUID_GROUP_AMX_COMPLEX,
+  XED_CPUID_GROUP_AMX_COMPLEX_AVX10, +
  XED_CPUID_GROUP_AMX_FP16,
+  XED_CPUID_GROUP_AMX_FP16_AVX10, +
+  XED_CPUID_GROUP_AMX_FP8, +
  XED_CPUID_GROUP_AMX_INT8,
+  XED_CPUID_GROUP_AMX_INT8_AVX10, +
+  XED_CPUID_GROUP_AMX_MOVRS, +
+  XED_CPUID_GROUP_AMX_TF32, +
  XED_CPUID_GROUP_AMX_TILE,
+  XED_CPUID_GROUP_AMX_TRANSPOSE, +
+  XED_CPUID_GROUP_AMX_TRANSPOSE_BF16, +
+  XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX, +
+  XED_CPUID_GROUP_AMX_TRANSPOSE_FP16, +
+  XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS, +
+  XED_CPUID_GROUP_AMX_TRANSPOSE_TF32, +
  XED_CPUID_GROUP_APX_F,
  XED_CPUID_GROUP_APX_F_ADX, @@ -671,6 +819,8 @@
  XED_CPUID_GROUP_APX_F_MOVDIRI,
+  XED_CPUID_GROUP_APX_F_MSR_IMM, +
  XED_CPUID_GROUP_APX_F_POPCNT,
  XED_CPUID_GROUP_APX_F_RAO_INT, @@ -681,6 +831,16 @@
  XED_CPUID_GROUP_AVX,
+  XED_CPUID_GROUP_AVX10_2_RC_256_AVX10, +
+  XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10, +
+  XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10, +
+  XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10, +
+  XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10, +
  XED_CPUID_GROUP_AVX2,
  XED_CPUID_GROUP_AVX2GATHER, @@ -797,6 +957,14 @@
  XED_CPUID_GROUP_AVX512_BF16_512_AVX10,
+  XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10, +
  XED_CPUID_GROUP_AVX512_BITALG_128,
  XED_CPUID_GROUP_AVX512_BITALG_128_AVX10, @@ -809,6 +977,8 @@
  XED_CPUID_GROUP_AVX512_BITALG_512_AVX10,
+  XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10, +
  XED_CPUID_GROUP_AVX512_FP16_128,
  XED_CPUID_GROUP_AVX512_FP16_128N, @@ -825,6 +995,12 @@
  XED_CPUID_GROUP_AVX512_FP16_512_AVX10,
+  XED_CPUID_GROUP_AVX512_FP16_CONVERT_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_FP16_CONVERT_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_FP16_CONVERT_512_AVX10, +
  XED_CPUID_GROUP_AVX512_FP16_SCALAR,
  XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10, @@ -853,6 +1029,42 @@
  XED_CPUID_GROUP_AVX512_IFMA_512_AVX10,
+  XED_CPUID_GROUP_AVX512_MEDIAX_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_MEDIAX_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_MEDIAX_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_MINMAX_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_MINMAX_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_MINMAX_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_MINMAX_SCALAR_AVX10, +
+  XED_CPUID_GROUP_AVX512_MOVZXC_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_DS_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_DS_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_DS_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_SAT_CVT_DS_SCALAR_AVX10, +
  XED_CPUID_GROUP_AVX512_VAES_128,
  XED_CPUID_GROUP_AVX512_VAES_128_AVX10, @@ -901,6 +1113,24 @@
  XED_CPUID_GROUP_AVX512_VNNI_512_AVX10,
+  XED_CPUID_GROUP_AVX512_VNNI_FP16_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_FP16_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_FP16_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT16_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT16_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT16_512_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT8_128_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT8_256_AVX10, +
+  XED_CPUID_GROUP_AVX512_VNNI_INT8_512_AVX10, +
  XED_CPUID_GROUP_AVX512_VP2INTERSECT_128,
  XED_CPUID_GROUP_AVX512_VP2INTERSECT_256, @@ -1013,10 +1243,14 @@
  XED_CPUID_GROUP_MOVDIRI,
+  XED_CPUID_GROUP_MOVRS, +
  XED_CPUID_GROUP_MPX,
  XED_CPUID_GROUP_MSRLIST,
+  XED_CPUID_GROUP_MSR_IMM, +
  XED_CPUID_GROUP_PBNDKB,
  XED_CPUID_GROUP_PCLMULQDQ, @@ -1065,6 +1299,12 @@
  XED_CPUID_GROUP_SM4,
+  XED_CPUID_GROUP_SM4_128_AVX10, +
+  XED_CPUID_GROUP_SM4_256_AVX10, +
+  XED_CPUID_GROUP_SM4_512_AVX10, +
  XED_CPUID_GROUP_SMAP,
  XED_CPUID_GROUP_SMX, @@ -1171,6 +1411,34 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_AVX512_AVX10_DEFINED

+ +
+
+

@@ -121,7 +121,7 @@

- +
#define XED_FEATURE_VECTOR_MAX   6#define XED_FEATURE_VECTOR_MAX   7
diff --git a/ref-manual/xed-cpuid-group-enum_8h.html b/ref-manual/xed-cpuid-group-enum_8h.html index 2d0c47b..ac27829 100644 --- a/ref-manual/xed-cpuid-group-enum_8h.html +++ b/ref-manual/xed-cpuid-group-enum_8h.html @@ -97,16 +97,44 @@

 
#define XED_CPUID_GROUP_AES_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_AVX512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_BF16_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_BF16_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_COMPLEX_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_COMPLEX_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_FP16_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_FP16_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_FP8_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_INT8_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_INT8_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_MOVRS_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TF32_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TILE_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_BF16_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_FP16_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS_DEFINED   1
 
#define XED_CPUID_GROUP_AMX_TRANSPOSE_TF32_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_ADX_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_AMX_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_MOVDIRI_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_MSR_IMM_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_POPCNT_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_RAO_INT_DEFINED   1
 
#define XED_CPUID_GROUP_APX_F_VMX_DEFINED   1
 
#define XED_CPUID_GROUP_AVX10_2_RC_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX2_DEFINED   1
 
#define XED_CPUID_GROUP_AVX2GATHER_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BF16_512_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BITALG_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BITALG_128_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_128_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_512_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MEDIAX_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MEDIAX_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MEDIAX_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MINMAX_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MINMAX_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MINMAX_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MINMAX_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_MOVZXC_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_SCALAR_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VAES_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VAES_128_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_512_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_FP16_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_FP16_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_FP16_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT16_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT16_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT16_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT8_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT8_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VNNI_INT8_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VP2INTERSECT_128_DEFINED   1
 
#define XED_CPUID_GROUP_AVX512_VP2INTERSECT_256_DEFINED   1
 
#define XED_CPUID_GROUP_MOVDIRI_DEFINED   1
 
#define XED_CPUID_GROUP_MOVRS_DEFINED   1
 
#define XED_CPUID_GROUP_MPX_DEFINED   1
 
#define XED_CPUID_GROUP_MSR_IMM_DEFINED   1
 
#define XED_CPUID_GROUP_MSRLIST_DEFINED   1
 
#define XED_CPUID_GROUP_PBNDKB_DEFINED   1
 
#define XED_CPUID_GROUP_SM3_DEFINED   1
 
#define XED_CPUID_GROUP_SM4_128_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_SM4_256_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_SM4_512_AVX10_DEFINED   1
 
#define XED_CPUID_GROUP_SM4_DEFINED   1
 
#define XED_CPUID_GROUP_SMAP_DEFINED   1
+ + + +
#define XED_CPUID_GROUP_AMX_AVX512_AVX10_DEFINED   1
+
+ +
+ + +

◆ XED_CPUID_GROUP_AMX_BF16_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_BF16_AVX10_DEFINED   1
+
+
@@ -1185,6 +1453,20 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_COMPLEX_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_COMPLEX_AVX10_DEFINED   1
+
+
@@ -1199,6 +1481,20 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_FP16_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_FP16_AVX10_DEFINED   1
+
+
@@ -1213,6 +1509,34 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_FP8_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_FP8_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_INT8_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_INT8_AVX10_DEFINED   1
+
+
@@ -1227,6 +1551,34 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TF32_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TF32_DEFINED   1
+
+
@@ -1241,6 +1593,90 @@

+ + + +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_BF16_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_BF16_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_FP16_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_FP16_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AMX_TRANSPOSE_TF32_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AMX_TRANSPOSE_TF32_DEFINED   1
+
+
@@ -1535,6 +1971,20 @@

+ + + +

◆ XED_CPUID_GROUP_APX_F_MSR_IMM_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_APX_F_MSR_IMM_DEFINED   1
+
+
@@ -1593,106 +2043,176 @@

-

◆ XED_CPUID_GROUP_AVX2_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX10_2_RC_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX2_DEFINED   1#define XED_CPUID_GROUP_AVX10_2_RC_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX2GATHER_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX2GATHER_DEFINED   1#define XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED   1#define XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR_DEFINED   1#define XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_4VNNIW_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_4VNNIW_512_DEFINED   1#define XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BF16_128_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX2_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BF16_128_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX2_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BF16_128_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX2GATHER_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BF16_128_DEFINED   1#define XED_CPUID_GROUP_AVX2GATHER_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BF16_256_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_4FMAPS_SCALAR_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_4VNNIW_512_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_4VNNIW_512_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_128_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_128_AVX10_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_128_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_128_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_256_AVX10_DEFINED

@@ -1745,6 +2265,62 @@

+

+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10_DEFINED   1
+
+
@@ -1775,364 +2351,672 @@

-

◆ XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED

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#define XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED

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#define XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_128_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_128_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_128N_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_128N_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_256_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_256_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_512_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_512_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_CONVERT_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_128_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_CONVERT_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_CONVERT_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_CONVERT_512_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED

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#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_GFNI_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_GFNI_128_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_GFNI_128_DEFINED

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#define XED_CPUID_GROUP_AVX512_GFNI_128_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_GFNI_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_GFNI_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_GFNI_256_DEFINED

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#define XED_CPUID_GROUP_AVX512_GFNI_256_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_GFNI_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_GFNI_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_GFNI_512_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED   1#define XED_CPUID_GROUP_AVX512_GFNI_512_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_128_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_128_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_128_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_256_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_128_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_256_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_128N_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_128N_DEFINED   1#define XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_256_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MEDIAX_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_256_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_MEDIAX_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_256_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MEDIAX_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_256_DEFINED   1#define XED_CPUID_GROUP_AVX512_MEDIAX_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MEDIAX_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_MEDIAX_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MINMAX_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_512_DEFINED   1#define XED_CPUID_GROUP_AVX512_MINMAX_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MINMAX_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_MINMAX_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MINMAX_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_FP16_SCALAR_DEFINED   1#define XED_CPUID_GROUP_AVX512_MINMAX_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_128_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MINMAX_SCALAR_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_128_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_MINMAX_SCALAR_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_128_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_MOVZXC_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_128_DEFINED   1#define XED_CPUID_GROUP_AVX512_MOVZXC_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_256_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_256_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_256_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_256_DEFINED   1#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_512_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_512_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_GFNI_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_GFNI_512_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_128_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_256_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_IFMA_128_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_128_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_IFMA_128_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_256_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_DS_128_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_IFMA_256_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_128_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_256_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_DS_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_IFMA_256_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_256_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_512_AVX10_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_DS_512_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_IFMA_512_AVX10_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_512_AVX10_DEFINED   1
- -

◆ XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED

+ +

◆ XED_CPUID_GROUP_AVX512_SAT_CVT_DS_SCALAR_AVX10_DEFINED

- +
#define XED_CPUID_GROUP_AVX512_IFMA_512_DEFINED   1#define XED_CPUID_GROUP_AVX512_SAT_CVT_DS_SCALAR_AVX10_DEFINED   1
@@ -2473,6 +3357,132 @@

+

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◆ XED_CPUID_GROUP_AVX512_VNNI_FP16_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_FP16_128_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_FP16_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_FP16_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_FP16_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_FP16_512_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT16_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT16_128_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT16_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT16_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT16_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT16_512_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT8_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT8_128_AVX10_DEFINED   1
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+ +
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT8_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT8_256_AVX10_DEFINED   1
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◆ XED_CPUID_GROUP_AVX512_VNNI_INT8_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_AVX512_VNNI_INT8_512_AVX10_DEFINED   1
+
+
@@ -3957,6 +4967,20 @@

+ + + +

◆ XED_CPUID_GROUP_MOVRS_DEFINED

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#define XED_CPUID_GROUP_MOVRS_DEFINED   1
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+
@@ -3971,6 +4995,20 @@

+ + + +

◆ XED_CPUID_GROUP_MSR_IMM_DEFINED

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#define XED_CPUID_GROUP_MSR_IMM_DEFINED   1
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+
@@ -4307,6 +5345,48 @@

+ + + +

◆ XED_CPUID_GROUP_SM4_128_AVX10_DEFINED

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#define XED_CPUID_GROUP_SM4_128_AVX10_DEFINED   1
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+ +
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◆ XED_CPUID_GROUP_SM4_256_AVX10_DEFINED

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#define XED_CPUID_GROUP_SM4_256_AVX10_DEFINED   1
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+
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◆ XED_CPUID_GROUP_SM4_512_AVX10_DEFINED

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#define XED_CPUID_GROUP_SM4_512_AVX10_DEFINED   1
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+
@@ -4773,11 +5853,25 @@

EnumeratorXED_CPUID_GROUP_INVALID  XED_CPUID_GROUP_ADOX_ADCX  XED_CPUID_GROUP_AES  +XED_CPUID_GROUP_AMX_AVX512_AVX10  XED_CPUID_GROUP_AMX_BF16  +XED_CPUID_GROUP_AMX_BF16_AVX10  XED_CPUID_GROUP_AMX_COMPLEX  +XED_CPUID_GROUP_AMX_COMPLEX_AVX10  XED_CPUID_GROUP_AMX_FP16  +XED_CPUID_GROUP_AMX_FP16_AVX10  +XED_CPUID_GROUP_AMX_FP8  XED_CPUID_GROUP_AMX_INT8  +XED_CPUID_GROUP_AMX_INT8_AVX10  +XED_CPUID_GROUP_AMX_MOVRS  +XED_CPUID_GROUP_AMX_TF32  XED_CPUID_GROUP_AMX_TILE  +XED_CPUID_GROUP_AMX_TRANSPOSE  +XED_CPUID_GROUP_AMX_TRANSPOSE_BF16  +XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX  +XED_CPUID_GROUP_AMX_TRANSPOSE_FP16  +XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS  +XED_CPUID_GROUP_AMX_TRANSPOSE_TF32  XED_CPUID_GROUP_APX_F  XED_CPUID_GROUP_APX_F_ADX  XED_CPUID_GROUP_APX_F_AMX  @@ -4799,11 +5893,17 @@

XED_CPUID_GROUP_APX_F_MOVBE  XED_CPUID_GROUP_APX_F_MOVDIR64B  XED_CPUID_GROUP_APX_F_MOVDIRI  +XED_CPUID_GROUP_APX_F_MSR_IMM  XED_CPUID_GROUP_APX_F_POPCNT  XED_CPUID_GROUP_APX_F_RAO_INT  XED_CPUID_GROUP_APX_F_USER_MSR  XED_CPUID_GROUP_APX_F_VMX  XED_CPUID_GROUP_AVX  +XED_CPUID_GROUP_AVX10_2_RC_256_AVX10  +XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10  +XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10  +XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10  +XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10  XED_CPUID_GROUP_AVX2  XED_CPUID_GROUP_AVX2GATHER  XED_CPUID_GROUP_AVX512BW_128  @@ -4862,12 +5962,17 @@

XED_CPUID_GROUP_AVX512_BF16_256_AVX10  XED_CPUID_GROUP_AVX512_BF16_512  XED_CPUID_GROUP_AVX512_BF16_512_AVX10  +XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10  +XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10  +XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10  +XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10  XED_CPUID_GROUP_AVX512_BITALG_128  XED_CPUID_GROUP_AVX512_BITALG_128_AVX10  XED_CPUID_GROUP_AVX512_BITALG_256  XED_CPUID_GROUP_AVX512_BITALG_256_AVX10  XED_CPUID_GROUP_AVX512_BITALG_512  XED_CPUID_GROUP_AVX512_BITALG_512_AVX10  +XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10  XED_CPUID_GROUP_AVX512_FP16_128  XED_CPUID_GROUP_AVX512_FP16_128N  XED_CPUID_GROUP_AVX512_FP16_128N_AVX10  @@ -4876,6 +5981,9 @@

XED_CPUID_GROUP_AVX512_FP16_256_AVX10  XED_CPUID_GROUP_AVX512_FP16_512  XED_CPUID_GROUP_AVX512_FP16_512_AVX10  +XED_CPUID_GROUP_AVX512_FP16_CONVERT_128_AVX10  +XED_CPUID_GROUP_AVX512_FP16_CONVERT_256_AVX10  +XED_CPUID_GROUP_AVX512_FP16_CONVERT_512_AVX10  XED_CPUID_GROUP_AVX512_FP16_SCALAR  XED_CPUID_GROUP_AVX512_FP16_SCALAR_AVX10  XED_CPUID_GROUP_AVX512_GFNI_128  @@ -4890,6 +5998,24 @@

XED_CPUID_GROUP_AVX512_IFMA_256_AVX10  XED_CPUID_GROUP_AVX512_IFMA_512  XED_CPUID_GROUP_AVX512_IFMA_512_AVX10  +XED_CPUID_GROUP_AVX512_MEDIAX_128_AVX10  +XED_CPUID_GROUP_AVX512_MEDIAX_256_AVX10  +XED_CPUID_GROUP_AVX512_MEDIAX_512_AVX10  +XED_CPUID_GROUP_AVX512_MINMAX_128_AVX10  +XED_CPUID_GROUP_AVX512_MINMAX_256_AVX10  +XED_CPUID_GROUP_AVX512_MINMAX_512_AVX10  +XED_CPUID_GROUP_AVX512_MINMAX_SCALAR_AVX10  +XED_CPUID_GROUP_AVX512_MOVZXC_128_AVX10  +XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_128_AVX10  +XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_256_AVX10  +XED_CPUID_GROUP_AVX512_NE_CONVERT_FP8_512_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_128_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_256_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_512_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_DS_128_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_DS_256_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_DS_512_AVX10  +XED_CPUID_GROUP_AVX512_SAT_CVT_DS_SCALAR_AVX10  XED_CPUID_GROUP_AVX512_VAES_128  XED_CPUID_GROUP_AVX512_VAES_128_AVX10  XED_CPUID_GROUP_AVX512_VAES_256  @@ -4914,6 +6040,15 @@

XED_CPUID_GROUP_AVX512_VNNI_256_AVX10  XED_CPUID_GROUP_AVX512_VNNI_512  XED_CPUID_GROUP_AVX512_VNNI_512_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_FP16_128_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_FP16_256_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_FP16_512_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT16_128_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT16_256_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT16_512_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT8_128_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT8_256_AVX10  +XED_CPUID_GROUP_AVX512_VNNI_INT8_512_AVX10  XED_CPUID_GROUP_AVX512_VP2INTERSECT_128  XED_CPUID_GROUP_AVX512_VP2INTERSECT_256  XED_CPUID_GROUP_AVX512_VP2INTERSECT_512  @@ -4970,8 +6105,10 @@

XED_CPUID_GROUP_MOVBE  XED_CPUID_GROUP_MOVDIR64B  XED_CPUID_GROUP_MOVDIRI  +XED_CPUID_GROUP_MOVRS  XED_CPUID_GROUP_MPX  XED_CPUID_GROUP_MSRLIST  +XED_CPUID_GROUP_MSR_IMM  XED_CPUID_GROUP_PBNDKB  XED_CPUID_GROUP_PCLMULQDQ  XED_CPUID_GROUP_PCONFIG  @@ -4996,6 +6133,9 @@

XED_CPUID_GROUP_SHA512  XED_CPUID_GROUP_SM3  XED_CPUID_GROUP_SM4  +XED_CPUID_GROUP_SM4_128_AVX10  +XED_CPUID_GROUP_SM4_256_AVX10  +XED_CPUID_GROUP_SM4_512_AVX10  XED_CPUID_GROUP_SMAP  XED_CPUID_GROUP_SMX  XED_CPUID_GROUP_SNP  diff --git a/ref-manual/xed-cpuid-group-enum_8h.js b/ref-manual/xed-cpuid-group-enum_8h.js index 4e671c8..97dd1dd 100644 --- a/ref-manual/xed-cpuid-group-enum_8h.js +++ b/ref-manual/xed-cpuid-group-enum_8h.js @@ -2,11 +2,25 @@ var xed_cpuid_group_enum_8h = [ [ "XED_CPUID_GROUP_ADOX_ADCX_DEFINED", "xed-cpuid-group-enum_8h.html#abbbc008350b3dce46871e36488d88570", null ], [ "XED_CPUID_GROUP_AES_DEFINED", "xed-cpuid-group-enum_8h.html#aaab44e1b17e5ac2f3e8978d6f89d67ae", null ], + [ "XED_CPUID_GROUP_AMX_AVX512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a58499284177ca136b71e4d63ee07aa91", null ], + [ "XED_CPUID_GROUP_AMX_BF16_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a99c8a10cd8e07384a479a20582d950cb", null ], [ "XED_CPUID_GROUP_AMX_BF16_DEFINED", "xed-cpuid-group-enum_8h.html#aa9ce0fa10afd4b0b28d14c7cf2d1660a", null ], + [ "XED_CPUID_GROUP_AMX_COMPLEX_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a5a90fa45250c0a659abd45ae113eb8fe", null ], [ "XED_CPUID_GROUP_AMX_COMPLEX_DEFINED", "xed-cpuid-group-enum_8h.html#afd58d1fed597fc2be67a2531cdb86684", null ], + [ "XED_CPUID_GROUP_AMX_FP16_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#ad52a8bbd7e97042cbe03a34d57699ead", null ], [ "XED_CPUID_GROUP_AMX_FP16_DEFINED", "xed-cpuid-group-enum_8h.html#ae115e46651c0534847e912481a5ade31", null ], + [ "XED_CPUID_GROUP_AMX_FP8_DEFINED", "xed-cpuid-group-enum_8h.html#a0e4a5b47622b325d5225fd83479c269a", null ], + [ "XED_CPUID_GROUP_AMX_INT8_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a77392dd8dd6758d34a916e79818aad69", null ], [ "XED_CPUID_GROUP_AMX_INT8_DEFINED", "xed-cpuid-group-enum_8h.html#a416077f624dffcc3b897652cc04c0214", null ], + [ "XED_CPUID_GROUP_AMX_MOVRS_DEFINED", "xed-cpuid-group-enum_8h.html#a66785c36f6594e486390f2c9c21372e8", null ], + [ "XED_CPUID_GROUP_AMX_TF32_DEFINED", "xed-cpuid-group-enum_8h.html#abf5989d85914172d184264a56d81f708", null ], [ "XED_CPUID_GROUP_AMX_TILE_DEFINED", "xed-cpuid-group-enum_8h.html#a05f24d0c29cabef92019163147488a7d", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_BF16_DEFINED", "xed-cpuid-group-enum_8h.html#a1e75b3abc701cdb8982bbced4ebd1bdd", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_COMPLEX_DEFINED", "xed-cpuid-group-enum_8h.html#aca80122564a93cd44ced4f546f9ff0f1", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_DEFINED", "xed-cpuid-group-enum_8h.html#aee9c1c18cfca8c6f5f175eaeeede4395", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_FP16_DEFINED", "xed-cpuid-group-enum_8h.html#a253b2d1d533eeaf208dd0432259d5023", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_MOVRS_DEFINED", "xed-cpuid-group-enum_8h.html#a973445ec24368b39845b6f1d808dcb88", null ], + [ "XED_CPUID_GROUP_AMX_TRANSPOSE_TF32_DEFINED", "xed-cpuid-group-enum_8h.html#ab7bf1e004baaecf1d0bd1b1f0b8e67c0", null ], [ "XED_CPUID_GROUP_APX_F_ADX_DEFINED", "xed-cpuid-group-enum_8h.html#a86438ff9ddb00c086267da1fcf4d7d3c", null ], [ "XED_CPUID_GROUP_APX_F_AMX_DEFINED", "xed-cpuid-group-enum_8h.html#a3fe06f29fab72c250ecbab6d85556030", null ], [ "XED_CPUID_GROUP_APX_F_BMI1_DEFINED", "xed-cpuid-group-enum_8h.html#a9d09ff5717b21dc16181de79f1fa3028", null ], @@ -28,10 +42,16 @@ var xed_cpuid_group_enum_8h = [ "XED_CPUID_GROUP_APX_F_MOVBE_DEFINED", "xed-cpuid-group-enum_8h.html#aa120571ed17357620e3c2cceb6602d51", null ], [ "XED_CPUID_GROUP_APX_F_MOVDIR64B_DEFINED", "xed-cpuid-group-enum_8h.html#adbe3e8ad0fe4d2a3b11ff20fd75d01ba", null ], [ "XED_CPUID_GROUP_APX_F_MOVDIRI_DEFINED", "xed-cpuid-group-enum_8h.html#a1e53357dd75e260105a3cc03599b1a9c", null ], + [ "XED_CPUID_GROUP_APX_F_MSR_IMM_DEFINED", "xed-cpuid-group-enum_8h.html#a0684f970ad3e8cd31a95468e37cdc2ef", null ], [ "XED_CPUID_GROUP_APX_F_POPCNT_DEFINED", "xed-cpuid-group-enum_8h.html#a5ec4101d30d8b9d9ce6defd0f01edf51", null ], [ "XED_CPUID_GROUP_APX_F_RAO_INT_DEFINED", "xed-cpuid-group-enum_8h.html#a202bbc2fea59ae824b74fedd1837f5b7", null ], [ "XED_CPUID_GROUP_APX_F_USER_MSR_DEFINED", "xed-cpuid-group-enum_8h.html#a65130a8805e43195fbba17abfcbb09b9", null ], [ "XED_CPUID_GROUP_APX_F_VMX_DEFINED", "xed-cpuid-group-enum_8h.html#aeb9b7eb4773df2e2bc4464b21693c80b", null ], + [ "XED_CPUID_GROUP_AVX10_2_RC_256_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a789bbd616e07a79aea741d803ece5a8f", null ], + [ "XED_CPUID_GROUP_AVX10_2_RC_SCALAR_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a644d0fb4596110285bc0309b1169db10", null ], + [ "XED_CPUID_GROUP_AVX10_MOVRS_128_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a3b6c626c8cdaaa7c5452d505462c9b64", null ], + [ "XED_CPUID_GROUP_AVX10_MOVRS_256_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a1932758a45d2574bd9444911ab728bd6", null ], + [ "XED_CPUID_GROUP_AVX10_MOVRS_512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a418a8a6e70f2e380f070fefc47948c1d", null ], [ "XED_CPUID_GROUP_AVX2_DEFINED", "xed-cpuid-group-enum_8h.html#aeb614155ec7f6a4a6f892049ee8d88e3", null ], [ "XED_CPUID_GROUP_AVX2GATHER_DEFINED", "xed-cpuid-group-enum_8h.html#af2a68f85a8e86ca980ee20c1ba5daa14", null ], [ "XED_CPUID_GROUP_AVX512_4FMAPS_512_DEFINED", "xed-cpuid-group-enum_8h.html#ac219bac05e74a0ba87af60b06a9add0c", null ], @@ -43,12 +63,17 @@ var xed_cpuid_group_enum_8h = [ "XED_CPUID_GROUP_AVX512_BF16_256_DEFINED", "xed-cpuid-group-enum_8h.html#aa3d903251c0423eccd06def64ff1f05b", null ], [ "XED_CPUID_GROUP_AVX512_BF16_512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#afbfebd9eab48182b3dfa63f0a8f221ff", null ], [ "XED_CPUID_GROUP_AVX512_BF16_512_DEFINED", "xed-cpuid-group-enum_8h.html#a31b5ba79af5debe362789c94440d5b07", null ], + [ "XED_CPUID_GROUP_AVX512_BF16_NE_128_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a7f78d516369c063178a53f604b90457a", null ], + [ "XED_CPUID_GROUP_AVX512_BF16_NE_256_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a049cf036c85b0a06ccabc91a3be37721", null ], + [ "XED_CPUID_GROUP_AVX512_BF16_NE_512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a5321888d6c1e837b653d81618ae3bb38", null ], + [ "XED_CPUID_GROUP_AVX512_BF16_NE_SCALAR_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a1a029e5f21b5941c1ceba1d1f326746a", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_128_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#ac60c707dfbf785b56c49b6b8c20f5212", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_128_DEFINED", "xed-cpuid-group-enum_8h.html#a3fdcfea2ed55ccb1a2eb75a8e5ebe20b", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_256_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a86367674500d8d4f62f307f70ca468ac", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_256_DEFINED", "xed-cpuid-group-enum_8h.html#a2176b949a4ed3f08eec6a0b65402d0f4", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#aaf56acea3e2501e00b5bdb2b8d530cb0", null ], [ "XED_CPUID_GROUP_AVX512_BITALG_512_DEFINED", "xed-cpuid-group-enum_8h.html#aca764993e67d908e904cf62db0e9976e", null ], + [ "XED_CPUID_GROUP_AVX512_COM_EF_SCALAR_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a80f5187afa4bdc0982d64090a2aa3f4d", null ], [ "XED_CPUID_GROUP_AVX512_FP16_128_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#a16f97f1565110bf0ec7474140d860e77", null ], [ "XED_CPUID_GROUP_AVX512_FP16_128_DEFINED", "xed-cpuid-group-enum_8h.html#ab74ce72ad4bf9f97fdb9bbb70c73db26", null ], [ "XED_CPUID_GROUP_AVX512_FP16_128N_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#aedb1e80e3244a537b697cfbdc4903740", null ], @@ -57,6 +82,9 @@ var xed_cpuid_group_enum_8h = [ "XED_CPUID_GROUP_AVX512_FP16_256_DEFINED", "xed-cpuid-group-enum_8h.html#ae30f580ac77bd8fab498b252f2869486", null ], [ "XED_CPUID_GROUP_AVX512_FP16_512_AVX10_DEFINED", "xed-cpuid-group-enum_8h.html#af6a89aab803dfac1095b963bb31ab6d4", null ], [ "XED_CPUID_GROUP_AVX512_FP16_512_DEFINED", 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a/ref-manual/xed-cpuid-rec-enum_8h.html b/ref-manual/xed-cpuid-rec-enum_8h.html index fd528fd..46da91f 100644 --- a/ref-manual/xed-cpuid-rec-enum_8h.html +++ b/ref-manual/xed-cpuid-rec-enum_8h.html @@ -97,16 +97,34 @@   #define XED_CPUID_REC_AES_DEFINED   1   +#define XED_CPUID_REC_AMX_AVX512_DEFINED   1 +  #define XED_CPUID_REC_AMX_BF16_DEFINED   1   +#define XED_CPUID_REC_AMX_BF16_MIRRORED_DEFINED   1 +  #define XED_CPUID_REC_AMX_COMPLEX_DEFINED   1   +#define XED_CPUID_REC_AMX_COMPLEX_MIRRORED_DEFINED   1 +  #define XED_CPUID_REC_AMX_FP16_DEFINED   1   +#define XED_CPUID_REC_AMX_FP16_MIRRORED_DEFINED   1 +  +#define XED_CPUID_REC_AMX_FP8_DEFINED   1 +  #define XED_CPUID_REC_AMX_INT8_DEFINED   1   +#define XED_CPUID_REC_AMX_INT8_MIRRORED_DEFINED   1 +  +#define XED_CPUID_REC_AMX_MOVRS_DEFINED   1 +  +#define XED_CPUID_REC_AMX_TF32_DEFINED   1 +  #define XED_CPUID_REC_AMX_TILES_DEFINED   1   +#define XED_CPUID_REC_AMX_TRANSPOSE_DEFINED   1 +  #define XED_CPUID_REC_APX_F_DEFINED   1   #define XED_CPUID_REC_AVX10_128VL_DEFINED   1 @@ -119,6 +137,8 @@   #define XED_CPUID_REC_AVX10_VER1_DEFINED   1   +#define XED_CPUID_REC_AVX10_VER2_DEFINED   1 +  #define XED_CPUID_REC_AVX2_DEFINED   1   #define XED_CPUID_REC_AVX512_4FMAPS_DEFINED   1 @@ -243,8 +263,12 @@   #define XED_CPUID_REC_MOVEBE_DEFINED   1   +#define XED_CPUID_REC_MOVRS_DEFINED   1 +  #define XED_CPUID_REC_MPX_DEFINED   1   +#define XED_CPUID_REC_MSR_IMM_DEFINED   1 +  #define XED_CPUID_REC_MSRLIST_DEFINED   1   #define XED_CPUID_REC_OSPKU_DEFINED   1 @@ -369,16 +393,34 @@
  XED_CPUID_REC_AES,
+  XED_CPUID_REC_AMX_AVX512, +
  XED_CPUID_REC_AMX_BF16,
+  XED_CPUID_REC_AMX_BF16_MIRRORED, +
  XED_CPUID_REC_AMX_COMPLEX,
+  XED_CPUID_REC_AMX_COMPLEX_MIRRORED, +
  XED_CPUID_REC_AMX_FP16,
+  XED_CPUID_REC_AMX_FP16_MIRRORED, +
+  XED_CPUID_REC_AMX_FP8, +
  XED_CPUID_REC_AMX_INT8,
+  XED_CPUID_REC_AMX_INT8_MIRRORED, +
+  XED_CPUID_REC_AMX_MOVRS, +
+  XED_CPUID_REC_AMX_TF32, +
  XED_CPUID_REC_AMX_TILES,
+  XED_CPUID_REC_AMX_TRANSPOSE, +
  XED_CPUID_REC_APX_F,
  XED_CPUID_REC_AVX, @@ -393,6 +435,8 @@
  XED_CPUID_REC_AVX10_VER1,
+  XED_CPUID_REC_AVX10_VER2, +
  XED_CPUID_REC_AVX2,
  XED_CPUID_REC_AVX512BW, @@ -511,10 +555,14 @@
  XED_CPUID_REC_MOVEBE,
+  XED_CPUID_REC_MOVRS, +
  XED_CPUID_REC_MPX,
  XED_CPUID_REC_MSRLIST,
+  XED_CPUID_REC_MSR_IMM, +
  XED_CPUID_REC_OSPKU,
  XED_CPUID_REC_OSXSAVE, @@ -671,6 +719,20 @@

+ + + +

◆ XED_CPUID_REC_AMX_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_AVX512_DEFINED   1
+
+
@@ -685,6 +747,20 @@

+ + + +

◆ XED_CPUID_REC_AMX_BF16_MIRRORED_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_BF16_MIRRORED_DEFINED   1
+
+
@@ -699,6 +775,20 @@

+ + + +

◆ XED_CPUID_REC_AMX_COMPLEX_MIRRORED_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_COMPLEX_MIRRORED_DEFINED   1
+
+
@@ -713,6 +803,34 @@

+ + + +

◆ XED_CPUID_REC_AMX_FP16_MIRRORED_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_FP16_MIRRORED_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_REC_AMX_FP8_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_FP8_DEFINED   1
+
+
@@ -727,6 +845,48 @@

+ + + +

◆ XED_CPUID_REC_AMX_INT8_MIRRORED_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_INT8_MIRRORED_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_REC_AMX_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_CPUID_REC_AMX_TF32_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_TF32_DEFINED   1
+
+
@@ -741,6 +901,20 @@

+ + + +

◆ XED_CPUID_REC_AMX_TRANSPOSE_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AMX_TRANSPOSE_DEFINED   1
+
+
@@ -825,6 +999,20 @@

+ + + +

◆ XED_CPUID_REC_AVX10_VER2_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_AVX10_VER2_DEFINED   1
+
+
@@ -1693,6 +1881,20 @@

+ + + +

◆ XED_CPUID_REC_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_MOVRS_DEFINED   1
+
+
@@ -1707,6 +1909,20 @@

+ + + +

◆ XED_CPUID_REC_MSR_IMM_DEFINED

+ +
+
+ + + + +
#define XED_CPUID_REC_MSR_IMM_DEFINED   1
+
+
@@ -2523,11 +2739,20 @@

EnumeratorXED_CPUID_REC_INVALID  XED_CPUID_REC_ADOXADCX  XED_CPUID_REC_AES  +XED_CPUID_REC_AMX_AVX512  XED_CPUID_REC_AMX_BF16  +XED_CPUID_REC_AMX_BF16_MIRRORED  XED_CPUID_REC_AMX_COMPLEX  +XED_CPUID_REC_AMX_COMPLEX_MIRRORED  XED_CPUID_REC_AMX_FP16  +XED_CPUID_REC_AMX_FP16_MIRRORED  +XED_CPUID_REC_AMX_FP8  XED_CPUID_REC_AMX_INT8  +XED_CPUID_REC_AMX_INT8_MIRRORED  +XED_CPUID_REC_AMX_MOVRS  +XED_CPUID_REC_AMX_TF32  XED_CPUID_REC_AMX_TILES  +XED_CPUID_REC_AMX_TRANSPOSE  XED_CPUID_REC_APX_F  XED_CPUID_REC_AVX  XED_CPUID_REC_AVX10_128VL  @@ -2535,6 +2760,7 @@

XED_CPUID_REC_AVX10_512VL  XED_CPUID_REC_AVX10_ENABLED  XED_CPUID_REC_AVX10_VER1  +XED_CPUID_REC_AVX10_VER2  XED_CPUID_REC_AVX2  XED_CPUID_REC_AVX512BW  XED_CPUID_REC_AVX512CD  @@ -2594,8 +2820,10 @@

XED_CPUID_REC_MOVDIR64B  XED_CPUID_REC_MOVDIRI  XED_CPUID_REC_MOVEBE  +XED_CPUID_REC_MOVRS  XED_CPUID_REC_MPX  XED_CPUID_REC_MSRLIST  +XED_CPUID_REC_MSR_IMM  XED_CPUID_REC_OSPKU  XED_CPUID_REC_OSXSAVE  XED_CPUID_REC_PBNDKB  diff --git a/ref-manual/xed-cpuid-rec-enum_8h.js b/ref-manual/xed-cpuid-rec-enum_8h.js index 1da2d9d..8bb7901 100644 --- a/ref-manual/xed-cpuid-rec-enum_8h.js +++ b/ref-manual/xed-cpuid-rec-enum_8h.js @@ -2,17 +2,27 @@ var xed_cpuid_rec_enum_8h = [ [ "XED_CPUID_REC_ADOXADCX_DEFINED", "xed-cpuid-rec-enum_8h.html#aa9789c1d1fdc526975e05e34995cae22", null ], [ "XED_CPUID_REC_AES_DEFINED", "xed-cpuid-rec-enum_8h.html#ac241dce6dbdb5dc41425cb049be46af8", null ], + [ "XED_CPUID_REC_AMX_AVX512_DEFINED", "xed-cpuid-rec-enum_8h.html#a3879bbb3021ceadbd233153fd0f5a98a", null ], [ "XED_CPUID_REC_AMX_BF16_DEFINED", "xed-cpuid-rec-enum_8h.html#af80089d4fe93b96117c9183e327d921d", null ], + [ "XED_CPUID_REC_AMX_BF16_MIRRORED_DEFINED", "xed-cpuid-rec-enum_8h.html#a5c7e3e3dd64fe21265ce3d9f3200752e", null ], [ "XED_CPUID_REC_AMX_COMPLEX_DEFINED", "xed-cpuid-rec-enum_8h.html#a60bc4b458f0edf2cd6ca6e7e5a3c93bd", null ], + [ "XED_CPUID_REC_AMX_COMPLEX_MIRRORED_DEFINED", "xed-cpuid-rec-enum_8h.html#ab3b60b6005458fdcdaf73d7d860973bc", null ], [ "XED_CPUID_REC_AMX_FP16_DEFINED", "xed-cpuid-rec-enum_8h.html#ae21a94d3253b9af25857682037906fc5", null ], + [ "XED_CPUID_REC_AMX_FP16_MIRRORED_DEFINED", "xed-cpuid-rec-enum_8h.html#a37deaa7f4872d0474630a2dff36f186c", null ], + [ "XED_CPUID_REC_AMX_FP8_DEFINED", "xed-cpuid-rec-enum_8h.html#ad420a644be7b88f238b4cc54525e6dc6", null ], [ "XED_CPUID_REC_AMX_INT8_DEFINED", "xed-cpuid-rec-enum_8h.html#aeb394bf961c586ae37c9c50cc2455ed0", null ], + [ "XED_CPUID_REC_AMX_INT8_MIRRORED_DEFINED", "xed-cpuid-rec-enum_8h.html#ac09c1e80cf4bc324d00fcad9313ec566", null ], + [ "XED_CPUID_REC_AMX_MOVRS_DEFINED", "xed-cpuid-rec-enum_8h.html#a9241a223acbf6052e9a8089d623160e4", null ], + [ "XED_CPUID_REC_AMX_TF32_DEFINED", "xed-cpuid-rec-enum_8h.html#a711049e06c46df297b9608caa6f285ba", null ], [ "XED_CPUID_REC_AMX_TILES_DEFINED", "xed-cpuid-rec-enum_8h.html#aa3843c09b27483202b426fce52b12205", null ], + [ "XED_CPUID_REC_AMX_TRANSPOSE_DEFINED", "xed-cpuid-rec-enum_8h.html#a66f62ba113111cce602757e6718fe3fb", null ], [ "XED_CPUID_REC_APX_F_DEFINED", "xed-cpuid-rec-enum_8h.html#abe63bc3da1db2592bca36d10695cac20", null ], [ "XED_CPUID_REC_AVX10_128VL_DEFINED", "xed-cpuid-rec-enum_8h.html#a1b9d89104b52f107d1424393ba119cf9", null ], [ "XED_CPUID_REC_AVX10_256VL_DEFINED", "xed-cpuid-rec-enum_8h.html#a9a85c7b50ded44df0599e1669dbf9c4c", null ], [ "XED_CPUID_REC_AVX10_512VL_DEFINED", "xed-cpuid-rec-enum_8h.html#aefb586dba66da725151d4e1d8f9e8062", null ], [ "XED_CPUID_REC_AVX10_ENABLED_DEFINED", "xed-cpuid-rec-enum_8h.html#ae75b05b2ad9226c88b42e3532754a643", null ], [ "XED_CPUID_REC_AVX10_VER1_DEFINED", "xed-cpuid-rec-enum_8h.html#a378466e33d8fd8c77d1da10aecc0f7dd", null ], + [ "XED_CPUID_REC_AVX10_VER2_DEFINED", "xed-cpuid-rec-enum_8h.html#a95fbd0a8c565d3966eddce0d19255b89", null ], [ "XED_CPUID_REC_AVX2_DEFINED", "xed-cpuid-rec-enum_8h.html#a1d4df9b5fa5fbdfb9a85cea5ce17df64", null ], [ "XED_CPUID_REC_AVX512_4FMAPS_DEFINED", "xed-cpuid-rec-enum_8h.html#a231915ce1ec0f741dd619c9466035c96", null ], [ "XED_CPUID_REC_AVX512_4VNNIW_DEFINED", "xed-cpuid-rec-enum_8h.html#a454b369dd2909573774189107a037de3", null ], @@ -75,7 +85,9 @@ var xed_cpuid_rec_enum_8h = [ "XED_CPUID_REC_MOVDIR64B_DEFINED", "xed-cpuid-rec-enum_8h.html#a6fbc42608fa39c0e4aaf2a841585cbfd", null ], [ "XED_CPUID_REC_MOVDIRI_DEFINED", "xed-cpuid-rec-enum_8h.html#a1cfb942f37c1118a4be63c7d276ca1ac", null ], [ "XED_CPUID_REC_MOVEBE_DEFINED", "xed-cpuid-rec-enum_8h.html#af15104a25288bc003f54911b6f41d6fe", null ], + [ "XED_CPUID_REC_MOVRS_DEFINED", "xed-cpuid-rec-enum_8h.html#ad70095e7079257ca7dc7702f04b1fd87", null ], [ "XED_CPUID_REC_MPX_DEFINED", "xed-cpuid-rec-enum_8h.html#a453b081f682c99f91260d8a8ec295444", null ], + [ "XED_CPUID_REC_MSR_IMM_DEFINED", "xed-cpuid-rec-enum_8h.html#aa797993700b0e09590d6f987aac8086a", null ], [ "XED_CPUID_REC_MSRLIST_DEFINED", "xed-cpuid-rec-enum_8h.html#a54d379077eb91dbeb1e31fed5bd6417a", null ], [ "XED_CPUID_REC_OSPKU_DEFINED", "xed-cpuid-rec-enum_8h.html#a3a5b55efd050274ae20ca6978ac0f229", null ], [ "XED_CPUID_REC_OSXSAVE_DEFINED", "xed-cpuid-rec-enum_8h.html#a9e40c30e9661b7549d5640b819130f16", null ], @@ -137,11 +149,20 @@ var xed_cpuid_rec_enum_8h = [ "XED_CPUID_REC_INVALID", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ac68bb943f1c604c98be8281ac8cf3d32", null ], [ "XED_CPUID_REC_ADOXADCX", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a4eb2cbe77a012887206c9e173584904f", null ], [ "XED_CPUID_REC_AES", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058aae3a958546db35d25b0ca636cc45cf5e", null ], + [ "XED_CPUID_REC_AMX_AVX512", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a0180914717cf862b7cabbfe0d5aadd38", null ], [ "XED_CPUID_REC_AMX_BF16", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a543d3afdb34cb9cdd1d96a1b36d45851", null ], + [ "XED_CPUID_REC_AMX_BF16_MIRRORED", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ab939399e49e50d227b08122c7559c210", null ], [ "XED_CPUID_REC_AMX_COMPLEX", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a83e661fa3df5afd6333ef6e8c74660b8", null ], + [ "XED_CPUID_REC_AMX_COMPLEX_MIRRORED", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a5061b75c5279cef49120dad8e16d5557", null ], [ "XED_CPUID_REC_AMX_FP16", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a8542f7b45264ddd9925174279e15712d", null ], + [ "XED_CPUID_REC_AMX_FP16_MIRRORED", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ac155070731f1c93f33dbf92f879c09ba", null ], + [ "XED_CPUID_REC_AMX_FP8", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a3eff3f87efd24028826ee5c56c1bb3fa", null ], [ "XED_CPUID_REC_AMX_INT8", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a387d18714174dd9d7256fe3f2e347009", null ], + [ "XED_CPUID_REC_AMX_INT8_MIRRORED", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ab668d2b0075a0b8f8d164347bf324f4c", null ], + [ "XED_CPUID_REC_AMX_MOVRS", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a3e9bbe033cb7f9472cd686a32f652460", null ], + [ "XED_CPUID_REC_AMX_TF32", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ab34e7a4d44a0dbe40dd3295d01406881", null ], [ "XED_CPUID_REC_AMX_TILES", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ad473703dc03d0573361585c43473038f", null ], + [ "XED_CPUID_REC_AMX_TRANSPOSE", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a73265b928a31a087c256f4801f1be16c", null ], [ "XED_CPUID_REC_APX_F", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a9a0af1a8f8bc8e875ef4d20b6211e993", null ], [ "XED_CPUID_REC_AVX", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a07d972aaf8b4c186a2629b48afd26b60", null ], [ "XED_CPUID_REC_AVX10_128VL", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058af43f8e8f78525e50fa43c5392f1a37d2", null ], @@ -149,6 +170,7 @@ var xed_cpuid_rec_enum_8h = [ "XED_CPUID_REC_AVX10_512VL", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a5d1f22a4954d383cbc35dab032ac41a1", null ], [ "XED_CPUID_REC_AVX10_ENABLED", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a2f51869dc2a4b34c89b34d8727f88de7", null ], [ "XED_CPUID_REC_AVX10_VER1", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a8ea080642a8b6f509d9271edad766b76", null ], + [ "XED_CPUID_REC_AVX10_VER2", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a4af24183d1dccecdb55958b07eb0fb75", null ], [ "XED_CPUID_REC_AVX2", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a017999122d157f619fba68307708cc2f", null ], [ "XED_CPUID_REC_AVX512BW", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a58ffb6b8fd8c856dab138e526b7fa343", null ], [ "XED_CPUID_REC_AVX512CD", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a73a57a187e41ffdabe20f62a90d2faac", null ], @@ -208,8 +230,10 @@ var xed_cpuid_rec_enum_8h = [ "XED_CPUID_REC_MOVDIR64B", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058acbab05ce6619e48335d11dd105336fe1", null ], [ "XED_CPUID_REC_MOVDIRI", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a6de0b0a74fd1e44f0dcee67f00cff653", null ], [ "XED_CPUID_REC_MOVEBE", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a1fd8132e3ac5e3a23ac10cda743ea9fa", null ], + [ "XED_CPUID_REC_MOVRS", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a1a2a8ec26fa3e15d2180b720485ac451", null ], [ "XED_CPUID_REC_MPX", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a60534c0b4130fb25556099c4ff584ffe", null ], [ "XED_CPUID_REC_MSRLIST", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a22b0309fdf1e22bc16fc75e56bdd2f2e", null ], + [ "XED_CPUID_REC_MSR_IMM", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058ac9c4ff043ced55251c67c1d684f9ad39", null ], [ "XED_CPUID_REC_OSPKU", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a69defd50da4f2dd806a27f25cea31b04", null ], [ "XED_CPUID_REC_OSXSAVE", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a48f68af8558e3375c5723a6cbe3778c8", null ], [ "XED_CPUID_REC_PBNDKB", "xed-cpuid-rec-enum_8h.html#acbe20513635ed778d430014768634058a32187873eddb629f0a27c671ad07e46f", null ], diff --git a/ref-manual/xed-encoder-gen-defs_8h.html b/ref-manual/xed-encoder-gen-defs_8h.html index 9dff638..345a943 100644 --- a/ref-manual/xed-encoder-gen-defs_8h.html +++ b/ref-manual/xed-encoder-gen-defs_8h.html @@ -90,15 +90,15 @@ - + - + - + - + - + @@ -113,7 +113,7 @@

Macros

#define XED_ENC_GROUPS   567
#define XED_ENC_GROUPS   599
 
#define XED_ENCODE_FB_VALUES_TABLE_SIZE   9819
#define XED_ENCODE_FB_VALUES_TABLE_SIZE   10936
 
#define XED_ENCODE_MAX_EMIT_PATTERNS   226
#define XED_ENCODE_MAX_EMIT_PATTERNS   210
 
#define XED_ENCODE_MAX_FB_PATTERNS   166
#define XED_ENCODE_MAX_FB_PATTERNS   169
 
#define XED_ENCODE_MAX_IFORMS   10215
#define XED_ENCODE_MAX_IFORMS   11222
 
#define XED_ENCODE_ORDER_MAX_ENTRIES   37
 
- +
#define XED_ENC_GROUPS   567#define XED_ENC_GROUPS   599
+ + + + @@ -111,6 +115,12 @@ + + + + + + @@ -215,6 +225,10 @@ + + + + @@ -229,6 +243,10 @@ + + + + @@ -259,6 +277,10 @@
  
XED_EXCEPTION_AMX_E1,
+  XED_EXCEPTION_AMX_E10, +
+  XED_EXCEPTION_AMX_E11, +
  XED_EXCEPTION_AMX_E1_EVEX,
  XED_EXCEPTION_AMX_E2, @@ -275,6 +297,12 @@
  XED_EXCEPTION_AMX_E6,
+  XED_EXCEPTION_AMX_E7_EVEX, +
+  XED_EXCEPTION_AMX_E8_EVEX, +
+  XED_EXCEPTION_AMX_E9, +
  XED_EXCEPTION_APX_EVEX_BMI,
  XED_EXCEPTION_APX_EVEX_CCMP, @@ -375,6 +403,10 @@
  XED_EXCEPTION_AVX_TYPE_8,
+  XED_EXCEPTION_LEGACY_MOVRS, +
+  XED_EXCEPTION_LEGACY_PREFETCH, +
  XED_EXCEPTION_LEGACY_RAO_INT,
  XED_EXCEPTION_MMX_FP, @@ -389,6 +421,10 @@
  XED_EXCEPTION_MMX_NOMEM,
+  XED_EXCEPTION_MSR_IMM_EVEX, +
+  XED_EXCEPTION_MSR_IMM_VEX, +
  XED_EXCEPTION_SSE_TYPE_1,
  XED_EXCEPTION_SSE_TYPE_2, @@ -429,6 +465,34 @@

Macros

#define XED_EXCEPTION_AMX_E10_DEFINED   1
 
#define XED_EXCEPTION_AMX_E11_DEFINED   1
 
#define XED_EXCEPTION_AMX_E1_DEFINED   1
 
#define XED_EXCEPTION_AMX_E1_EVEX_DEFINED   1
 
#define XED_EXCEPTION_AMX_E6_DEFINED   1
 
#define XED_EXCEPTION_AMX_E7_EVEX_DEFINED   1
 
#define XED_EXCEPTION_AMX_E8_EVEX_DEFINED   1
 
#define XED_EXCEPTION_AMX_E9_DEFINED   1
 
#define XED_EXCEPTION_APX_EVEX_BMI_DEFINED   1
 
#define XED_EXCEPTION_APX_EVEX_CCMP_DEFINED   1
 
#define XED_EXCEPTION_LAST_DEFINED   1
 
#define XED_EXCEPTION_LEGACY_MOVRS_DEFINED   1
 
#define XED_EXCEPTION_LEGACY_PREFETCH_DEFINED   1
 
#define XED_EXCEPTION_LEGACY_RAO_INT_DEFINED   1
 
#define XED_EXCEPTION_MMX_FP_16ALIGN_DEFINED   1
 
#define XED_EXCEPTION_MMX_NOMEM_DEFINED   1
 
#define XED_EXCEPTION_MSR_IMM_EVEX_DEFINED   1
 
#define XED_EXCEPTION_MSR_IMM_VEX_DEFINED   1
 
#define XED_EXCEPTION_SSE_TYPE_1_DEFINED   1
 
#define XED_EXCEPTION_SSE_TYPE_2_DEFINED   1
 

Macro Definition Documentation

+ +

◆ XED_EXCEPTION_AMX_E10_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_AMX_E10_DEFINED   1
+
+ +
+
+ +

◆ XED_EXCEPTION_AMX_E11_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_AMX_E11_DEFINED   1
+
+ +
+

◆ XED_EXCEPTION_AMX_E1_DEFINED

@@ -553,6 +617,48 @@

+ + + +

◆ XED_EXCEPTION_AMX_E7_EVEX_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_AMX_E7_EVEX_DEFINED   1
+
+ +
+
+ +

◆ XED_EXCEPTION_AMX_E8_EVEX_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_AMX_E8_EVEX_DEFINED   1
+
+ +
+
+ +

◆ XED_EXCEPTION_AMX_E9_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_AMX_E9_DEFINED   1
+
+
@@ -1281,6 +1387,34 @@

+ + + +

◆ XED_EXCEPTION_LEGACY_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_LEGACY_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_EXCEPTION_LEGACY_PREFETCH_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_LEGACY_PREFETCH_DEFINED   1
+
+
@@ -1379,6 +1513,34 @@

+ + + +

◆ XED_EXCEPTION_MSR_IMM_EVEX_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_MSR_IMM_EVEX_DEFINED   1
+
+ +
+
+ +

◆ XED_EXCEPTION_MSR_IMM_VEX_DEFINED

+ +
+
+ + + + +
#define XED_EXCEPTION_MSR_IMM_VEX_DEFINED   1
+
+
@@ -1550,6 +1712,8 @@

EnumeratorXED_EXCEPTION_INVALID  XED_EXCEPTION_AMX_E1  +XED_EXCEPTION_AMX_E10  +XED_EXCEPTION_AMX_E11  XED_EXCEPTION_AMX_E1_EVEX  XED_EXCEPTION_AMX_E2  XED_EXCEPTION_AMX_E2_EVEX  @@ -1558,6 +1722,9 @@

XED_EXCEPTION_AMX_E4  XED_EXCEPTION_AMX_E5  XED_EXCEPTION_AMX_E6  +XED_EXCEPTION_AMX_E7_EVEX  +XED_EXCEPTION_AMX_E8_EVEX  +XED_EXCEPTION_AMX_E9  XED_EXCEPTION_APX_EVEX_BMI  XED_EXCEPTION_APX_EVEX_CCMP  XED_EXCEPTION_APX_EVEX_CET_WRSS  @@ -1608,6 +1775,8 @@

XED_EXCEPTION_AVX_TYPE_6  XED_EXCEPTION_AVX_TYPE_7  XED_EXCEPTION_AVX_TYPE_8  +XED_EXCEPTION_LEGACY_MOVRS  +XED_EXCEPTION_LEGACY_PREFETCH  XED_EXCEPTION_LEGACY_RAO_INT  XED_EXCEPTION_MMX_FP  XED_EXCEPTION_MMX_FP_16ALIGN  @@ -1615,6 +1784,8 @@

XED_EXCEPTION_MMX_NOFP  XED_EXCEPTION_MMX_NOFP2  XED_EXCEPTION_MMX_NOMEM  +XED_EXCEPTION_MSR_IMM_EVEX  +XED_EXCEPTION_MSR_IMM_VEX  XED_EXCEPTION_SSE_TYPE_1  XED_EXCEPTION_SSE_TYPE_2  XED_EXCEPTION_SSE_TYPE_2D  diff --git a/ref-manual/xed-exception-enum_8h.js b/ref-manual/xed-exception-enum_8h.js index ca44269..faa1b7c 100644 --- a/ref-manual/xed-exception-enum_8h.js +++ b/ref-manual/xed-exception-enum_8h.js @@ -1,5 +1,7 @@ var xed_exception_enum_8h = [ + [ "XED_EXCEPTION_AMX_E10_DEFINED", "xed-exception-enum_8h.html#ab28045861cf05cb93ce338d7f86ffd94", null ], + [ "XED_EXCEPTION_AMX_E11_DEFINED", "xed-exception-enum_8h.html#af3a5e926b7ee96f45c1722fd29e5e464", null ], [ "XED_EXCEPTION_AMX_E1_DEFINED", "xed-exception-enum_8h.html#a65212ff235d142d995f5613f5cfb9782", null ], [ "XED_EXCEPTION_AMX_E1_EVEX_DEFINED", "xed-exception-enum_8h.html#a98584b1d486e7b438ea47e9f17c83978", null ], [ "XED_EXCEPTION_AMX_E2_DEFINED", "xed-exception-enum_8h.html#a9ce51e35bb8e178baf0adb129178e462", null ], @@ -9,6 +11,9 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_AMX_E4_DEFINED", "xed-exception-enum_8h.html#a27e90288b92404da4e6d25ebf224339a", null ], [ "XED_EXCEPTION_AMX_E5_DEFINED", "xed-exception-enum_8h.html#aa018e4736ceb007e802f628591457566", null ], [ "XED_EXCEPTION_AMX_E6_DEFINED", "xed-exception-enum_8h.html#a9754bb12a1d887d7828fd08e2941bb49", null ], + [ "XED_EXCEPTION_AMX_E7_EVEX_DEFINED", "xed-exception-enum_8h.html#a537409bcd010c663ffd90027b90a7b22", null ], + [ "XED_EXCEPTION_AMX_E8_EVEX_DEFINED", "xed-exception-enum_8h.html#afe67df78a64fdd3cabef90f719d28fe3", null ], + [ "XED_EXCEPTION_AMX_E9_DEFINED", "xed-exception-enum_8h.html#a7138f8abb6be5643ca7de9c0be443527", null ], [ "XED_EXCEPTION_APX_EVEX_BMI_DEFINED", "xed-exception-enum_8h.html#a1425e837f2d283b653b5f16d50c3f092", null ], [ "XED_EXCEPTION_APX_EVEX_CCMP_DEFINED", "xed-exception-enum_8h.html#a74f86ffc0d869493d7811e780f94bce5", null ], [ "XED_EXCEPTION_APX_EVEX_CET_WRSS_DEFINED", "xed-exception-enum_8h.html#aa2e21df9f2f93d6c86ca5989bb434688", null ], @@ -61,6 +66,8 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_AVX_TYPE_8_DEFINED", "xed-exception-enum_8h.html#a1bf9e057b417925f1a68e56fff88dda9", null ], [ "XED_EXCEPTION_INVALID_DEFINED", "xed-exception-enum_8h.html#a4466123bdb987403008132c233125885", null ], [ "XED_EXCEPTION_LAST_DEFINED", "xed-exception-enum_8h.html#a99feeb805b8a8fa4afde1efbb33f967d", null ], + [ "XED_EXCEPTION_LEGACY_MOVRS_DEFINED", "xed-exception-enum_8h.html#a19209292f366402bca1516ae5d94ba99", null ], + [ "XED_EXCEPTION_LEGACY_PREFETCH_DEFINED", "xed-exception-enum_8h.html#a1dc1f851abd45aead812ecb177729a5d", null ], [ "XED_EXCEPTION_LEGACY_RAO_INT_DEFINED", "xed-exception-enum_8h.html#a6a126827490129dac05c883f3a7381f2", null ], [ "XED_EXCEPTION_MMX_FP_16ALIGN_DEFINED", "xed-exception-enum_8h.html#a5b630972b8992681cefdf1006bd1b976", null ], [ "XED_EXCEPTION_MMX_FP_DEFINED", "xed-exception-enum_8h.html#ad19e0730a09f707c09d4c9567d16eb55", null ], @@ -68,6 +75,8 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_MMX_NOFP2_DEFINED", "xed-exception-enum_8h.html#a45183d10b24e47bbb1015ffd16f7e8bc", null ], [ "XED_EXCEPTION_MMX_NOFP_DEFINED", "xed-exception-enum_8h.html#ac1411303d127206403f3d91b42c8b33b", null ], [ "XED_EXCEPTION_MMX_NOMEM_DEFINED", "xed-exception-enum_8h.html#a3a3539bef76cc887da5e472685bb68f7", null ], + [ "XED_EXCEPTION_MSR_IMM_EVEX_DEFINED", "xed-exception-enum_8h.html#a41e94849012a919a25645a0f6e4705df", null ], + [ "XED_EXCEPTION_MSR_IMM_VEX_DEFINED", "xed-exception-enum_8h.html#abe665034493c5c21f8ec3965c2368f68", null ], [ "XED_EXCEPTION_SSE_TYPE_1_DEFINED", "xed-exception-enum_8h.html#a5e502d830ade6ab5df0402a4192e876c", null ], [ "XED_EXCEPTION_SSE_TYPE_2_DEFINED", "xed-exception-enum_8h.html#a46ff605b68d0422cbc11620c039e533d", null ], [ "XED_EXCEPTION_SSE_TYPE_2D_DEFINED", "xed-exception-enum_8h.html#a238b855cb9df86913bd65d9c6e0cd7eb", null ], @@ -82,6 +91,8 @@ var xed_exception_enum_8h = [ "xed_exception_enum_t", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4d", [ [ "XED_EXCEPTION_INVALID", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dac46edbcf63abdf12eb19682d92a7825f", null ], [ "XED_EXCEPTION_AMX_E1", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da7a7d97525bd9d00da1618af56ec1be18", null ], + [ "XED_EXCEPTION_AMX_E10", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da788eb3de960c66f11838716bd31207b5", null ], + [ "XED_EXCEPTION_AMX_E11", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4daf79024f057b1fc90b894ffa4e3b0b5fc", null ], [ "XED_EXCEPTION_AMX_E1_EVEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4daf7c506764913555f3e019a4321199dee", null ], [ "XED_EXCEPTION_AMX_E2", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da7dd3d2746c962bae7fd79ab502583272", null ], [ "XED_EXCEPTION_AMX_E2_EVEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da00e5a6a929078c785fbf099c4cc465f5", null ], @@ -90,6 +101,9 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_AMX_E4", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dae113bb9e3b3a412543f3a5a75c346232", null ], [ "XED_EXCEPTION_AMX_E5", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da1364220a15e3cb6a3955acddd1ed00be", null ], [ "XED_EXCEPTION_AMX_E6", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4daca284bdec6a5e6a10ead9181d5996265", null ], + [ "XED_EXCEPTION_AMX_E7_EVEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dac67081661b5db9435f32778b4c895fae", null ], + [ "XED_EXCEPTION_AMX_E8_EVEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da9d8da9dc1bb8b0c2c636c2a70891620f", null ], + [ "XED_EXCEPTION_AMX_E9", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da8c5d0a50008b698c71828db64d7e567d", null ], [ "XED_EXCEPTION_APX_EVEX_BMI", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da4b13bcbf6958c2d5a02050f4ac191d6e", null ], [ "XED_EXCEPTION_APX_EVEX_CCMP", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da88bceb97fe108755dc7fb5b6d2eecc0d", null ], [ "XED_EXCEPTION_APX_EVEX_CET_WRSS", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dac85d1be3dc0ba50c36035ffc9e0a538c", null ], @@ -140,6 +154,8 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_AVX_TYPE_6", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da77ffc22ac13cb3ba7aebf2a7a4344fa1", null ], [ "XED_EXCEPTION_AVX_TYPE_7", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dab354d162a5b646c4d7f202bf62ca78bd", null ], [ "XED_EXCEPTION_AVX_TYPE_8", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dae8e27600a3ccffefc4de3027a0627660", null ], + [ "XED_EXCEPTION_LEGACY_MOVRS", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dad3712480f23594c4241568416dc88b21", null ], + [ "XED_EXCEPTION_LEGACY_PREFETCH", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dabf4d66320dfe5db319395c201dd4f83b", null ], [ "XED_EXCEPTION_LEGACY_RAO_INT", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da40d72e0bf6aaebed8ce22ba93bf8e9bd", null ], [ "XED_EXCEPTION_MMX_FP", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da696d5d49505df07f8c932001df5eff73", null ], [ "XED_EXCEPTION_MMX_FP_16ALIGN", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da21ebfa6f2d3826cf4dd30bfc5773bfe4", null ], @@ -147,6 +163,8 @@ var xed_exception_enum_8h = [ "XED_EXCEPTION_MMX_NOFP", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da76832dddb40cbfa180d8eabb10930c72", null ], [ "XED_EXCEPTION_MMX_NOFP2", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dae3873f805357e5482ac88847121df3a6", null ], [ "XED_EXCEPTION_MMX_NOMEM", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da2071004b826063a614c94bc413f09c6b", null ], + [ "XED_EXCEPTION_MSR_IMM_EVEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dac12a8bea727ebbd30d83952daed71930", null ], + [ "XED_EXCEPTION_MSR_IMM_VEX", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dae23562dfbb900c4488bd2a3efaf7c72d", null ], [ "XED_EXCEPTION_SSE_TYPE_1", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dabba934609f4d869bf86c488162ad3d4f", null ], [ "XED_EXCEPTION_SSE_TYPE_2", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4dab8a0bd648a322f9f14ca979eb04310fa", null ], [ "XED_EXCEPTION_SSE_TYPE_2D", "xed-exception-enum_8h.html#a49126b5e9b22f54161f21c31248faf4da74273754d2cd71feb730233c1a0c52fa", null ], diff --git a/ref-manual/xed-extension-enum_8h.html b/ref-manual/xed-extension-enum_8h.html index adf31ed..6e7249a 100644 --- a/ref-manual/xed-extension-enum_8h.html +++ b/ref-manual/xed-extension-enum_8h.html @@ -195,8 +195,12 @@   #define XED_EXTENSION_MOVDIR_DEFINED   1   +#define XED_EXTENSION_MOVRS_DEFINED   1 +  #define XED_EXTENSION_MPX_DEFINED   1   +#define XED_EXTENSION_MSR_IMM_DEFINED   1 +  #define XED_EXTENSION_MSRLIST_DEFINED   1   #define XED_EXTENSION_PAUSE_DEFINED   1 @@ -411,10 +415,14 @@
  XED_EXTENSION_MOVDIR,
+  XED_EXTENSION_MOVRS, +
  XED_EXTENSION_MPX,
  XED_EXTENSION_MSRLIST,
+  XED_EXTENSION_MSR_IMM, +
  XED_EXTENSION_PAUSE,
  XED_EXTENSION_PBNDKB, @@ -1253,6 +1261,20 @@

+ + + +

◆ XED_EXTENSION_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_EXTENSION_MOVRS_DEFINED   1
+
+
@@ -1267,6 +1289,20 @@

+ + + +

◆ XED_EXTENSION_MSR_IMM_DEFINED

+ +
+
+ + + + +
#define XED_EXTENSION_MSR_IMM_DEFINED   1
+
+
@@ -2102,8 +2138,10 @@

XED_EXTENSION_MONITORX  XED_EXTENSION_MOVBE  XED_EXTENSION_MOVDIR  +XED_EXTENSION_MOVRS  XED_EXTENSION_MPX  XED_EXTENSION_MSRLIST  +XED_EXTENSION_MSR_IMM  XED_EXTENSION_PAUSE  XED_EXTENSION_PBNDKB  XED_EXTENSION_PCLMULQDQ  diff --git a/ref-manual/xed-extension-enum_8h.js b/ref-manual/xed-extension-enum_8h.js index 1fbc5cb..e90a132 100644 --- a/ref-manual/xed-extension-enum_8h.js +++ b/ref-manual/xed-extension-enum_8h.js @@ -51,7 +51,9 @@ var xed_extension_enum_8h = [ "XED_EXTENSION_MONITORX_DEFINED", "xed-extension-enum_8h.html#a4abddc4065c81b90480de8a7472748db", null ], [ "XED_EXTENSION_MOVBE_DEFINED", "xed-extension-enum_8h.html#abdef0cb0f50fdbe752bfc578527d5e48", null ], [ "XED_EXTENSION_MOVDIR_DEFINED", "xed-extension-enum_8h.html#a110f1f69e43b01e4ff187f251ba68929", null ], + [ "XED_EXTENSION_MOVRS_DEFINED", "xed-extension-enum_8h.html#af369db97fd9072259bf27fa3e31064b9", null ], [ "XED_EXTENSION_MPX_DEFINED", "xed-extension-enum_8h.html#a6f79eaddd3f0c47f89c4d9f807c5d7ee", null ], + [ "XED_EXTENSION_MSR_IMM_DEFINED", "xed-extension-enum_8h.html#adcf80d2cd64660857cb882d4570fcf68", null ], [ "XED_EXTENSION_MSRLIST_DEFINED", "xed-extension-enum_8h.html#a159dee9a5f97afd82d4c22531653d9ea", null ], [ "XED_EXTENSION_PAUSE_DEFINED", "xed-extension-enum_8h.html#a349409109d54511bc22bc80865e2047e", null ], [ "XED_EXTENSION_PBNDKB_DEFINED", "xed-extension-enum_8h.html#a38a1eab96f022ded28bd3e958558ed04", null ], @@ -158,8 +160,10 @@ var xed_extension_enum_8h = [ "XED_EXTENSION_MONITORX", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a556b1e7129fdbc42e2f8f0a6ddf1a09f", null ], [ "XED_EXTENSION_MOVBE", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a4530b677a64ddce4a726500b4d06392f", null ], [ "XED_EXTENSION_MOVDIR", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a25270e2d3410ef4e5cff419c7f897253", null ], + [ "XED_EXTENSION_MOVRS", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916aa0843152c29007b42dafe46e16d3bf25", null ], [ "XED_EXTENSION_MPX", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916ab487da25cf712a96e09ae7ea886d8e57", null ], [ "XED_EXTENSION_MSRLIST", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a838ef9e85cfc2450abf767f62dae101d", null ], + [ "XED_EXTENSION_MSR_IMM", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a79353d1c6ae581d425262c7d92e1ed55", null ], [ "XED_EXTENSION_PAUSE", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a23c26baffc2a862c75d8d65d19dfcfc1", null ], [ "XED_EXTENSION_PBNDKB", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916a7a1590c751711805b08d640d17262b08", null ], [ "XED_EXTENSION_PCLMULQDQ", "xed-extension-enum_8h.html#ae7b9f64cdf123c5fda22bd10d5db9916ae5ac045f137f483be8f5356abc16f728", null ], diff --git a/ref-manual/xed-gen-table-defs_8h.html b/ref-manual/xed-gen-table-defs_8h.html index d45f508..a72abc0 100644 --- a/ref-manual/xed-gen-table-defs_8h.html +++ b/ref-manual/xed-gen-table-defs_8h.html @@ -102,17 +102,17 @@   #define XED_MAX_IFORMS_PER_ICLASS   48   -#define XED_MAX_INST_TABLE_NODES   10235 +#define XED_MAX_INST_TABLE_NODES   11201   #define XED_MAX_MAP_EVEX   7   #define XED_MAX_MAP_VEX   7   -#define XED_MAX_OPERAND_SEQUENCES   10112 +#define XED_MAX_OPERAND_SEQUENCES   11186   -#define XED_MAX_OPERAND_TABLE_NODES   1679 +#define XED_MAX_OPERAND_TABLE_NODES   1787   -#define XED_MAX_REQUIRED_ATTRIBUTES   262 +#define XED_MAX_REQUIRED_ATTRIBUTES   286   #define XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES   149   @@ -211,7 +211,7 @@

- +
#define XED_MAX_INST_TABLE_NODES   10235#define XED_MAX_INST_TABLE_NODES   11201
diff --git a/ref-manual/xed-iclass-enum_8h.html b/ref-manual/xed-iclass-enum_8h.html index 8ccb060..cc8b587 100644 --- a/ref-manual/xed-iclass-enum_8h.html +++ b/ref-manual/xed-iclass-enum_8h.html @@ -1155,6 +1155,8 @@   #define XED_ICLASS_MOVQ_DEFINED   1   +#define XED_ICLASS_MOVRS_DEFINED   1 +  #define XED_ICLASS_MOVSB_DEFINED   1   #define XED_ICLASS_MOVSD_DEFINED   1 @@ -1505,6 +1507,8 @@   #define XED_ICLASS_PREFETCHNTA_DEFINED   1   +#define XED_ICLASS_PREFETCHRST2_DEFINED   1 +  #define XED_ICLASS_PREFETCHT0_DEFINED   1   #define XED_ICLASS_PREFETCHT1_DEFINED   1 @@ -1941,14 +1945,48 @@   #define XED_ICLASS_T1MSKC_DEFINED   1   +#define XED_ICLASS_T2RPNTLVWZ0_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ0RS_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ0RST1_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ0T1_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ1_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ1RS_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ1RST1_DEFINED   1 +  +#define XED_ICLASS_T2RPNTLVWZ1T1_DEFINED   1 +  #define XED_ICLASS_TCMMIMFP16PS_DEFINED   1   #define XED_ICLASS_TCMMRLFP16PS_DEFINED   1   +#define XED_ICLASS_TCONJTCMMIMFP16PS_DEFINED   1 +  +#define XED_ICLASS_TCONJTFP16_DEFINED   1 +  +#define XED_ICLASS_TCVTROWD2PS_DEFINED   1 +  +#define XED_ICLASS_TCVTROWPS2PBF16H_DEFINED   1 +  +#define XED_ICLASS_TCVTROWPS2PBF16L_DEFINED   1 +  +#define XED_ICLASS_TCVTROWPS2PHH_DEFINED   1 +  +#define XED_ICLASS_TCVTROWPS2PHL_DEFINED   1 +  #define XED_ICLASS_TDCALL_DEFINED   1   #define XED_ICLASS_TDPBF16PS_DEFINED   1   +#define XED_ICLASS_TDPBF8PS_DEFINED   1 +  +#define XED_ICLASS_TDPBHF8PS_DEFINED   1 +  #define XED_ICLASS_TDPBSSD_DEFINED   1   #define XED_ICLASS_TDPBSUD_DEFINED   1 @@ -1959,14 +1997,24 @@   #define XED_ICLASS_TDPFP16PS_DEFINED   1   +#define XED_ICLASS_TDPHBF8PS_DEFINED   1 +  +#define XED_ICLASS_TDPHF8PS_DEFINED   1 +  #define XED_ICLASS_TEST_DEFINED   1   #define XED_ICLASS_TESTUI_DEFINED   1   #define XED_ICLASS_TILELOADD_DEFINED   1   +#define XED_ICLASS_TILELOADDRS_DEFINED   1 +  +#define XED_ICLASS_TILELOADDRST1_DEFINED   1 +  #define XED_ICLASS_TILELOADDT1_DEFINED   1   +#define XED_ICLASS_TILEMOVROW_DEFINED   1 +  #define XED_ICLASS_TILERELEASE_DEFINED   1   #define XED_ICLASS_TILESTORED_DEFINED   1 @@ -1975,8 +2023,22 @@   #define XED_ICLASS_TLBSYNC_DEFINED   1   +#define XED_ICLASS_TMMULTF32PS_DEFINED   1 +  #define XED_ICLASS_TPAUSE_DEFINED   1   +#define XED_ICLASS_TTCMMIMFP16PS_DEFINED   1 +  +#define XED_ICLASS_TTCMMRLFP16PS_DEFINED   1 +  +#define XED_ICLASS_TTDPBF16PS_DEFINED   1 +  +#define XED_ICLASS_TTDPFP16PS_DEFINED   1 +  +#define XED_ICLASS_TTMMULTF32PS_DEFINED   1 +  +#define XED_ICLASS_TTRANSPOSED_DEFINED   1 +  #define XED_ICLASS_TZCNT_DEFINED   1   #define XED_ICLASS_TZMSK_DEFINED   1 @@ -2017,6 +2079,8 @@   #define XED_ICLASS_V4FNMADDSS_DEFINED   1   +#define XED_ICLASS_VADDNEPBF16_DEFINED   1 +  #define XED_ICLASS_VADDPD_DEFINED   1   #define XED_ICLASS_VADDPH_DEFINED   1 @@ -2101,6 +2165,8 @@   #define XED_ICLASS_VBROADCASTSS_DEFINED   1   +#define XED_ICLASS_VCMPPBF16_DEFINED   1 +  #define XED_ICLASS_VCMPPD_DEFINED   1   #define XED_ICLASS_VCMPPH_DEFINED   1 @@ -2123,14 +2189,46 @@   #define XED_ICLASS_VCOMPRESSPS_DEFINED   1   +#define XED_ICLASS_VCOMSBF16_DEFINED   1 +  +#define XED_ICLASS_VCOMXSD_DEFINED   1 +  +#define XED_ICLASS_VCOMXSH_DEFINED   1 +  +#define XED_ICLASS_VCOMXSS_DEFINED   1 +  +#define XED_ICLASS_VCVT2PS2PHX_DEFINED   1 +  +#define XED_ICLASS_VCVTBIASPH2BF8_DEFINED   1 +  +#define XED_ICLASS_VCVTBIASPH2BF8S_DEFINED   1 +  +#define XED_ICLASS_VCVTBIASPH2HF8_DEFINED   1 +  +#define XED_ICLASS_VCVTBIASPH2HF8S_DEFINED   1 +  #define XED_ICLASS_VCVTDQ2PD_DEFINED   1   #define XED_ICLASS_VCVTDQ2PH_DEFINED   1   #define XED_ICLASS_VCVTDQ2PS_DEFINED   1   +#define XED_ICLASS_VCVTHF82PH_DEFINED   1 +  +#define XED_ICLASS_VCVTNE2PH2BF8_DEFINED   1 +  +#define XED_ICLASS_VCVTNE2PH2BF8S_DEFINED   1 +  +#define XED_ICLASS_VCVTNE2PH2HF8_DEFINED   1 +  +#define XED_ICLASS_VCVTNE2PH2HF8S_DEFINED   1 +  #define XED_ICLASS_VCVTNE2PS2BF16_DEFINED   1   +#define XED_ICLASS_VCVTNEBF162IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTNEBF162IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTNEEBF162PS_DEFINED   1   #define XED_ICLASS_VCVTNEEPH2PS_DEFINED   1 @@ -2139,6 +2237,14 @@   #define XED_ICLASS_VCVTNEOPH2PS_DEFINED   1   +#define XED_ICLASS_VCVTNEPH2BF8_DEFINED   1 +  +#define XED_ICLASS_VCVTNEPH2BF8S_DEFINED   1 +  +#define XED_ICLASS_VCVTNEPH2HF8_DEFINED   1 +  +#define XED_ICLASS_VCVTNEPH2HF8S_DEFINED   1 +  #define XED_ICLASS_VCVTNEPS2BF16_DEFINED   1   #define XED_ICLASS_VCVTPD2DQ_DEFINED   1 @@ -2155,6 +2261,10 @@   #define XED_ICLASS_VCVTPH2DQ_DEFINED   1   +#define XED_ICLASS_VCVTPH2IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTPH2IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTPH2PD_DEFINED   1   #define XED_ICLASS_VCVTPH2PS_DEFINED   1 @@ -2173,6 +2283,10 @@   #define XED_ICLASS_VCVTPS2DQ_DEFINED   1   +#define XED_ICLASS_VCVTPS2IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTPS2IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTPS2PD_DEFINED   1   #define XED_ICLASS_VCVTPS2PH_DEFINED   1 @@ -2221,16 +2335,32 @@   #define XED_ICLASS_VCVTSS2USI_DEFINED   1   +#define XED_ICLASS_VCVTTNEBF162IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTTNEBF162IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTTPD2DQ_DEFINED   1   +#define XED_ICLASS_VCVTTPD2DQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPD2QQ_DEFINED   1   +#define XED_ICLASS_VCVTTPD2QQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPD2UDQ_DEFINED   1   +#define XED_ICLASS_VCVTTPD2UDQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPD2UQQ_DEFINED   1   +#define XED_ICLASS_VCVTTPD2UQQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPH2DQ_DEFINED   1   +#define XED_ICLASS_VCVTTPH2IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTTPH2IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTTPH2QQ_DEFINED   1   #define XED_ICLASS_VCVTTPH2UDQ_DEFINED   1 @@ -2243,24 +2373,44 @@   #define XED_ICLASS_VCVTTPS2DQ_DEFINED   1   +#define XED_ICLASS_VCVTTPS2DQS_DEFINED   1 +  +#define XED_ICLASS_VCVTTPS2IBS_DEFINED   1 +  +#define XED_ICLASS_VCVTTPS2IUBS_DEFINED   1 +  #define XED_ICLASS_VCVTTPS2QQ_DEFINED   1   +#define XED_ICLASS_VCVTTPS2QQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPS2UDQ_DEFINED   1   +#define XED_ICLASS_VCVTTPS2UDQS_DEFINED   1 +  #define XED_ICLASS_VCVTTPS2UQQ_DEFINED   1   +#define XED_ICLASS_VCVTTPS2UQQS_DEFINED   1 +  #define XED_ICLASS_VCVTTSD2SI_DEFINED   1   +#define XED_ICLASS_VCVTTSD2SIS_DEFINED   1 +  #define XED_ICLASS_VCVTTSD2USI_DEFINED   1   +#define XED_ICLASS_VCVTTSD2USIS_DEFINED   1 +  #define XED_ICLASS_VCVTTSH2SI_DEFINED   1   #define XED_ICLASS_VCVTTSH2USI_DEFINED   1   #define XED_ICLASS_VCVTTSS2SI_DEFINED   1   +#define XED_ICLASS_VCVTTSS2SIS_DEFINED   1 +  #define XED_ICLASS_VCVTTSS2USI_DEFINED   1   +#define XED_ICLASS_VCVTTSS2USIS_DEFINED   1 +  #define XED_ICLASS_VCVTUDQ2PD_DEFINED   1   #define XED_ICLASS_VCVTUDQ2PH_DEFINED   1 @@ -2285,6 +2435,8 @@   #define XED_ICLASS_VDBPSADBW_DEFINED   1   +#define XED_ICLASS_VDIVNEPBF16_DEFINED   1 +  #define XED_ICLASS_VDIVPD_DEFINED   1   #define XED_ICLASS_VDIVPH_DEFINED   1 @@ -2301,6 +2453,8 @@   #define XED_ICLASS_VDPPD_DEFINED   1   +#define XED_ICLASS_VDPPHPS_DEFINED   1 +  #define XED_ICLASS_VDPPS_DEFINED   1   #define XED_ICLASS_VERR_DEFINED   1 @@ -2353,6 +2507,8 @@   #define XED_ICLASS_VFIXUPIMMSS_DEFINED   1   +#define XED_ICLASS_VFMADD132NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMADD132PD_DEFINED   1   #define XED_ICLASS_VFMADD132PH_DEFINED   1 @@ -2365,6 +2521,8 @@   #define XED_ICLASS_VFMADD132SS_DEFINED   1   +#define XED_ICLASS_VFMADD213NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMADD213PD_DEFINED   1   #define XED_ICLASS_VFMADD213PH_DEFINED   1 @@ -2377,6 +2535,8 @@   #define XED_ICLASS_VFMADD213SS_DEFINED   1   +#define XED_ICLASS_VFMADD231NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMADD231PD_DEFINED   1   #define XED_ICLASS_VFMADD231PH_DEFINED   1 @@ -2423,6 +2583,8 @@   #define XED_ICLASS_VFMADDSUBPS_DEFINED   1   +#define XED_ICLASS_VFMSUB132NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMSUB132PD_DEFINED   1   #define XED_ICLASS_VFMSUB132PH_DEFINED   1 @@ -2435,6 +2597,8 @@   #define XED_ICLASS_VFMSUB132SS_DEFINED   1   +#define XED_ICLASS_VFMSUB213NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMSUB213PD_DEFINED   1   #define XED_ICLASS_VFMSUB213PH_DEFINED   1 @@ -2447,6 +2611,8 @@   #define XED_ICLASS_VFMSUB213SS_DEFINED   1   +#define XED_ICLASS_VFMSUB231NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFMSUB231PD_DEFINED   1   #define XED_ICLASS_VFMSUB231PH_DEFINED   1 @@ -2493,6 +2659,8 @@   #define XED_ICLASS_VFMULCSH_DEFINED   1   +#define XED_ICLASS_VFNMADD132NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMADD132PD_DEFINED   1   #define XED_ICLASS_VFNMADD132PH_DEFINED   1 @@ -2505,6 +2673,8 @@   #define XED_ICLASS_VFNMADD132SS_DEFINED   1   +#define XED_ICLASS_VFNMADD213NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMADD213PD_DEFINED   1   #define XED_ICLASS_VFNMADD213PH_DEFINED   1 @@ -2517,6 +2687,8 @@   #define XED_ICLASS_VFNMADD213SS_DEFINED   1   +#define XED_ICLASS_VFNMADD231NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMADD231PD_DEFINED   1   #define XED_ICLASS_VFNMADD231PH_DEFINED   1 @@ -2537,6 +2709,8 @@   #define XED_ICLASS_VFNMADDSS_DEFINED   1   +#define XED_ICLASS_VFNMSUB132NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMSUB132PD_DEFINED   1   #define XED_ICLASS_VFNMSUB132PH_DEFINED   1 @@ -2549,6 +2723,8 @@   #define XED_ICLASS_VFNMSUB132SS_DEFINED   1   +#define XED_ICLASS_VFNMSUB213NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMSUB213PD_DEFINED   1   #define XED_ICLASS_VFNMSUB213PH_DEFINED   1 @@ -2561,6 +2737,8 @@   #define XED_ICLASS_VFNMSUB213SS_DEFINED   1   +#define XED_ICLASS_VFNMSUB231NEPBF16_DEFINED   1 +  #define XED_ICLASS_VFNMSUB231PD_DEFINED   1   #define XED_ICLASS_VFNMSUB231PH_DEFINED   1 @@ -2581,6 +2759,8 @@   #define XED_ICLASS_VFNMSUBSS_DEFINED   1   +#define XED_ICLASS_VFPCLASSPBF16_DEFINED   1 +  #define XED_ICLASS_VFPCLASSPD_DEFINED   1   #define XED_ICLASS_VFPCLASSPH_DEFINED   1 @@ -2625,6 +2805,8 @@   #define XED_ICLASS_VGATHERQPS_DEFINED   1   +#define XED_ICLASS_VGETEXPPBF16_DEFINED   1 +  #define XED_ICLASS_VGETEXPPD_DEFINED   1   #define XED_ICLASS_VGETEXPPH_DEFINED   1 @@ -2637,6 +2819,8 @@   #define XED_ICLASS_VGETEXPSS_DEFINED   1   +#define XED_ICLASS_VGETMANTPBF16_DEFINED   1 +  #define XED_ICLASS_VGETMANTPD_DEFINED   1   #define XED_ICLASS_VGETMANTPH_DEFINED   1 @@ -2695,6 +2879,8 @@   #define XED_ICLASS_VMASKMOVPS_DEFINED   1   +#define XED_ICLASS_VMAXPBF16_DEFINED   1 +  #define XED_ICLASS_VMAXPD_DEFINED   1   #define XED_ICLASS_VMAXPH_DEFINED   1 @@ -2713,6 +2899,22 @@   #define XED_ICLASS_VMFUNC_DEFINED   1   +#define XED_ICLASS_VMINMAXNEPBF16_DEFINED   1 +  +#define XED_ICLASS_VMINMAXPD_DEFINED   1 +  +#define XED_ICLASS_VMINMAXPH_DEFINED   1 +  +#define XED_ICLASS_VMINMAXPS_DEFINED   1 +  +#define XED_ICLASS_VMINMAXSD_DEFINED   1 +  +#define XED_ICLASS_VMINMAXSH_DEFINED   1 +  +#define XED_ICLASS_VMINMAXSS_DEFINED   1 +  +#define XED_ICLASS_VMINPBF16_DEFINED   1 +  #define XED_ICLASS_VMINPD_DEFINED   1   #define XED_ICLASS_VMINPH_DEFINED   1 @@ -2781,6 +2983,14 @@   #define XED_ICLASS_VMOVQ_DEFINED   1   +#define XED_ICLASS_VMOVRSB_DEFINED   1 +  +#define XED_ICLASS_VMOVRSD_DEFINED   1 +  +#define XED_ICLASS_VMOVRSQ_DEFINED   1 +  +#define XED_ICLASS_VMOVRSW_DEFINED   1 +  #define XED_ICLASS_VMOVSD_DEFINED   1   #define XED_ICLASS_VMOVSH_DEFINED   1 @@ -2811,6 +3021,8 @@   #define XED_ICLASS_VMSAVE_DEFINED   1   +#define XED_ICLASS_VMULNEPBF16_DEFINED   1 +  #define XED_ICLASS_VMULPD_DEFINED   1   #define XED_ICLASS_VMULPH_DEFINED   1 @@ -3551,6 +3763,8 @@   #define XED_ICLASS_VRCP28SS_DEFINED   1   +#define XED_ICLASS_VRCPPBF16_DEFINED   1 +  #define XED_ICLASS_VRCPPH_DEFINED   1   #define XED_ICLASS_VRCPPS_DEFINED   1 @@ -3559,6 +3773,8 @@   #define XED_ICLASS_VRCPSS_DEFINED   1   +#define XED_ICLASS_VREDUCENEPBF16_DEFINED   1 +  #define XED_ICLASS_VREDUCEPD_DEFINED   1   #define XED_ICLASS_VREDUCEPH_DEFINED   1 @@ -3571,6 +3787,8 @@   #define XED_ICLASS_VREDUCESS_DEFINED   1   +#define XED_ICLASS_VRNDSCALENEPBF16_DEFINED   1 +  #define XED_ICLASS_VRNDSCALEPD_DEFINED   1   #define XED_ICLASS_VRNDSCALEPH_DEFINED   1 @@ -3607,6 +3825,8 @@   #define XED_ICLASS_VRSQRT28SS_DEFINED   1   +#define XED_ICLASS_VRSQRTPBF16_DEFINED   1 +  #define XED_ICLASS_VRSQRTPH_DEFINED   1   #define XED_ICLASS_VRSQRTPS_DEFINED   1 @@ -3615,6 +3835,8 @@   #define XED_ICLASS_VRSQRTSS_DEFINED   1   +#define XED_ICLASS_VSCALEFPBF16_DEFINED   1 +  #define XED_ICLASS_VSCALEFPD_DEFINED   1   #define XED_ICLASS_VSCALEFPH_DEFINED   1 @@ -3679,6 +3901,8 @@   #define XED_ICLASS_VSM4RNDS4_DEFINED   1   +#define XED_ICLASS_VSQRTNEPBF16_DEFINED   1 +  #define XED_ICLASS_VSQRTPD_DEFINED   1   #define XED_ICLASS_VSQRTPH_DEFINED   1 @@ -3693,6 +3917,8 @@   #define XED_ICLASS_VSTMXCSR_DEFINED   1   +#define XED_ICLASS_VSUBNEPBF16_DEFINED   1 +  #define XED_ICLASS_VSUBPD_DEFINED   1   #define XED_ICLASS_VSUBPH_DEFINED   1 @@ -3715,6 +3941,12 @@   #define XED_ICLASS_VUCOMISS_DEFINED   1   +#define XED_ICLASS_VUCOMXSD_DEFINED   1 +  +#define XED_ICLASS_VUCOMXSH_DEFINED   1 +  +#define XED_ICLASS_VUCOMXSS_DEFINED   1 +  #define XED_ICLASS_VUNPCKHPD_DEFINED   1   #define XED_ICLASS_VUNPCKHPS_DEFINED   1 @@ -4873,6 +5105,8 @@
  XED_ICLASS_MOVQ2DQ,
+  XED_ICLASS_MOVRS, +
  XED_ICLASS_MOVSB,
  XED_ICLASS_MOVSD, @@ -5223,6 +5457,8 @@
  XED_ICLASS_PREFETCHNTA,
+  XED_ICLASS_PREFETCHRST2, +
  XED_ICLASS_PREFETCHT0,
  XED_ICLASS_PREFETCHT1, @@ -5663,14 +5899,48 @@
  XED_ICLASS_T1MSKC,
+  XED_ICLASS_T2RPNTLVWZ0, +
+  XED_ICLASS_T2RPNTLVWZ0RS, +
+  XED_ICLASS_T2RPNTLVWZ0RST1, +
+  XED_ICLASS_T2RPNTLVWZ0T1, +
+  XED_ICLASS_T2RPNTLVWZ1, +
+  XED_ICLASS_T2RPNTLVWZ1RS, +
+  XED_ICLASS_T2RPNTLVWZ1RST1, +
+  XED_ICLASS_T2RPNTLVWZ1T1, +
  XED_ICLASS_TCMMIMFP16PS,
  XED_ICLASS_TCMMRLFP16PS,
+  XED_ICLASS_TCONJTCMMIMFP16PS, +
+  XED_ICLASS_TCONJTFP16, +
+  XED_ICLASS_TCVTROWD2PS, +
+  XED_ICLASS_TCVTROWPS2PBF16H, +
+  XED_ICLASS_TCVTROWPS2PBF16L, +
+  XED_ICLASS_TCVTROWPS2PHH, +
+  XED_ICLASS_TCVTROWPS2PHL, +
  XED_ICLASS_TDCALL,
  XED_ICLASS_TDPBF16PS,
+  XED_ICLASS_TDPBF8PS, +
+  XED_ICLASS_TDPBHF8PS, +
  XED_ICLASS_TDPBSSD,
  XED_ICLASS_TDPBSUD, @@ -5681,14 +5951,24 @@
  XED_ICLASS_TDPFP16PS,
+  XED_ICLASS_TDPHBF8PS, +
+  XED_ICLASS_TDPHF8PS, +
  XED_ICLASS_TEST,
  XED_ICLASS_TESTUI,
  XED_ICLASS_TILELOADD,
+  XED_ICLASS_TILELOADDRS, +
+  XED_ICLASS_TILELOADDRST1, +
  XED_ICLASS_TILELOADDT1,
+  XED_ICLASS_TILEMOVROW, +
  XED_ICLASS_TILERELEASE,
  XED_ICLASS_TILESTORED, @@ -5697,8 +5977,22 @@
  XED_ICLASS_TLBSYNC,
+  XED_ICLASS_TMMULTF32PS, +
  XED_ICLASS_TPAUSE,
+  XED_ICLASS_TTCMMIMFP16PS, +
+  XED_ICLASS_TTCMMRLFP16PS, +
+  XED_ICLASS_TTDPBF16PS, +
+  XED_ICLASS_TTDPFP16PS, +
+  XED_ICLASS_TTMMULTF32PS, +
+  XED_ICLASS_TTRANSPOSED, +
  XED_ICLASS_TZCNT,
  XED_ICLASS_TZMSK, @@ -5739,6 +6033,8 @@
  XED_ICLASS_V4FNMADDSS,
+  XED_ICLASS_VADDNEPBF16, +
  XED_ICLASS_VADDPD,
  XED_ICLASS_VADDPH, @@ -5823,6 +6119,8 @@
  XED_ICLASS_VBROADCASTSS,
+  XED_ICLASS_VCMPPBF16, +
  XED_ICLASS_VCMPPD,
  XED_ICLASS_VCMPPH, @@ -5845,14 +6143,46 @@
  XED_ICLASS_VCOMPRESSPS,
+  XED_ICLASS_VCOMSBF16, +
+  XED_ICLASS_VCOMXSD, +
+  XED_ICLASS_VCOMXSH, +
+  XED_ICLASS_VCOMXSS, +
+  XED_ICLASS_VCVT2PS2PHX, +
+  XED_ICLASS_VCVTBIASPH2BF8, +
+  XED_ICLASS_VCVTBIASPH2BF8S, +
+  XED_ICLASS_VCVTBIASPH2HF8, +
+  XED_ICLASS_VCVTBIASPH2HF8S, +
  XED_ICLASS_VCVTDQ2PD,
  XED_ICLASS_VCVTDQ2PH,
  XED_ICLASS_VCVTDQ2PS,
+  XED_ICLASS_VCVTHF82PH, +
+  XED_ICLASS_VCVTNE2PH2BF8, +
+  XED_ICLASS_VCVTNE2PH2BF8S, +
+  XED_ICLASS_VCVTNE2PH2HF8, +
+  XED_ICLASS_VCVTNE2PH2HF8S, +
  XED_ICLASS_VCVTNE2PS2BF16,
+  XED_ICLASS_VCVTNEBF162IBS, +
+  XED_ICLASS_VCVTNEBF162IUBS, +
  XED_ICLASS_VCVTNEEBF162PS,
  XED_ICLASS_VCVTNEEPH2PS, @@ -5861,6 +6191,14 @@
  XED_ICLASS_VCVTNEOPH2PS,
+  XED_ICLASS_VCVTNEPH2BF8, +
+  XED_ICLASS_VCVTNEPH2BF8S, +
+  XED_ICLASS_VCVTNEPH2HF8, +
+  XED_ICLASS_VCVTNEPH2HF8S, +
  XED_ICLASS_VCVTNEPS2BF16,
  XED_ICLASS_VCVTPD2DQ, @@ -5877,6 +6215,10 @@
  XED_ICLASS_VCVTPH2DQ,
+  XED_ICLASS_VCVTPH2IBS, +
+  XED_ICLASS_VCVTPH2IUBS, +
  XED_ICLASS_VCVTPH2PD,
  XED_ICLASS_VCVTPH2PS, @@ -5895,6 +6237,10 @@
  XED_ICLASS_VCVTPS2DQ,
+  XED_ICLASS_VCVTPS2IBS, +
+  XED_ICLASS_VCVTPS2IUBS, +
  XED_ICLASS_VCVTPS2PD,
  XED_ICLASS_VCVTPS2PH, @@ -5943,16 +6289,32 @@
  XED_ICLASS_VCVTSS2USI,
+  XED_ICLASS_VCVTTNEBF162IBS, +
+  XED_ICLASS_VCVTTNEBF162IUBS, +
  XED_ICLASS_VCVTTPD2DQ,
+  XED_ICLASS_VCVTTPD2DQS, +
  XED_ICLASS_VCVTTPD2QQ,
+  XED_ICLASS_VCVTTPD2QQS, +
  XED_ICLASS_VCVTTPD2UDQ,
+  XED_ICLASS_VCVTTPD2UDQS, +
  XED_ICLASS_VCVTTPD2UQQ,
+  XED_ICLASS_VCVTTPD2UQQS, +
  XED_ICLASS_VCVTTPH2DQ,
+  XED_ICLASS_VCVTTPH2IBS, +
+  XED_ICLASS_VCVTTPH2IUBS, +
  XED_ICLASS_VCVTTPH2QQ,
  XED_ICLASS_VCVTTPH2UDQ, @@ -5965,24 +6327,44 @@
  XED_ICLASS_VCVTTPS2DQ,
+  XED_ICLASS_VCVTTPS2DQS, +
+  XED_ICLASS_VCVTTPS2IBS, +
+  XED_ICLASS_VCVTTPS2IUBS, +
  XED_ICLASS_VCVTTPS2QQ,
+  XED_ICLASS_VCVTTPS2QQS, +
  XED_ICLASS_VCVTTPS2UDQ,
+  XED_ICLASS_VCVTTPS2UDQS, +
  XED_ICLASS_VCVTTPS2UQQ,
+  XED_ICLASS_VCVTTPS2UQQS, +
  XED_ICLASS_VCVTTSD2SI,
+  XED_ICLASS_VCVTTSD2SIS, +
  XED_ICLASS_VCVTTSD2USI,
+  XED_ICLASS_VCVTTSD2USIS, +
  XED_ICLASS_VCVTTSH2SI,
  XED_ICLASS_VCVTTSH2USI,
  XED_ICLASS_VCVTTSS2SI,
+  XED_ICLASS_VCVTTSS2SIS, +
  XED_ICLASS_VCVTTSS2USI,
+  XED_ICLASS_VCVTTSS2USIS, +
  XED_ICLASS_VCVTUDQ2PD,
  XED_ICLASS_VCVTUDQ2PH, @@ -6007,6 +6389,8 @@
  XED_ICLASS_VDBPSADBW,
+  XED_ICLASS_VDIVNEPBF16, +
  XED_ICLASS_VDIVPD,
  XED_ICLASS_VDIVPH, @@ -6023,6 +6407,8 @@
  XED_ICLASS_VDPPD,
+  XED_ICLASS_VDPPHPS, +
  XED_ICLASS_VDPPS,
  XED_ICLASS_VERR, @@ -6075,6 +6461,8 @@
  XED_ICLASS_VFIXUPIMMSS,
+  XED_ICLASS_VFMADD132NEPBF16, +
  XED_ICLASS_VFMADD132PD,
  XED_ICLASS_VFMADD132PH, @@ -6087,6 +6475,8 @@
  XED_ICLASS_VFMADD132SS,
+  XED_ICLASS_VFMADD213NEPBF16, +
  XED_ICLASS_VFMADD213PD,
  XED_ICLASS_VFMADD213PH, @@ -6099,6 +6489,8 @@
  XED_ICLASS_VFMADD213SS,
+  XED_ICLASS_VFMADD231NEPBF16, +
  XED_ICLASS_VFMADD231PD,
  XED_ICLASS_VFMADD231PH, @@ -6145,6 +6537,8 @@
  XED_ICLASS_VFMADDSUBPS,
+  XED_ICLASS_VFMSUB132NEPBF16, +
  XED_ICLASS_VFMSUB132PD,
  XED_ICLASS_VFMSUB132PH, @@ -6157,6 +6551,8 @@
  XED_ICLASS_VFMSUB132SS,
+  XED_ICLASS_VFMSUB213NEPBF16, +
  XED_ICLASS_VFMSUB213PD,
  XED_ICLASS_VFMSUB213PH, @@ -6169,6 +6565,8 @@
  XED_ICLASS_VFMSUB213SS,
+  XED_ICLASS_VFMSUB231NEPBF16, +
  XED_ICLASS_VFMSUB231PD,
  XED_ICLASS_VFMSUB231PH, @@ -6215,6 +6613,8 @@
  XED_ICLASS_VFMULCSH,
+  XED_ICLASS_VFNMADD132NEPBF16, +
  XED_ICLASS_VFNMADD132PD,
  XED_ICLASS_VFNMADD132PH, @@ -6227,6 +6627,8 @@
  XED_ICLASS_VFNMADD132SS,
+  XED_ICLASS_VFNMADD213NEPBF16, +
  XED_ICLASS_VFNMADD213PD,
  XED_ICLASS_VFNMADD213PH, @@ -6239,6 +6641,8 @@
  XED_ICLASS_VFNMADD213SS,
+  XED_ICLASS_VFNMADD231NEPBF16, +
  XED_ICLASS_VFNMADD231PD,
  XED_ICLASS_VFNMADD231PH, @@ -6259,6 +6663,8 @@
  XED_ICLASS_VFNMADDSS,
+  XED_ICLASS_VFNMSUB132NEPBF16, +
  XED_ICLASS_VFNMSUB132PD,
  XED_ICLASS_VFNMSUB132PH, @@ -6271,6 +6677,8 @@
  XED_ICLASS_VFNMSUB132SS,
+  XED_ICLASS_VFNMSUB213NEPBF16, +
  XED_ICLASS_VFNMSUB213PD,
  XED_ICLASS_VFNMSUB213PH, @@ -6283,6 +6691,8 @@
  XED_ICLASS_VFNMSUB213SS,
+  XED_ICLASS_VFNMSUB231NEPBF16, +
  XED_ICLASS_VFNMSUB231PD,
  XED_ICLASS_VFNMSUB231PH, @@ -6303,6 +6713,8 @@
  XED_ICLASS_VFNMSUBSS,
+  XED_ICLASS_VFPCLASSPBF16, +
  XED_ICLASS_VFPCLASSPD,
  XED_ICLASS_VFPCLASSPH, @@ -6347,6 +6759,8 @@
  XED_ICLASS_VGATHERQPS,
+  XED_ICLASS_VGETEXPPBF16, +
  XED_ICLASS_VGETEXPPD,
  XED_ICLASS_VGETEXPPH, @@ -6359,6 +6773,8 @@
  XED_ICLASS_VGETEXPSS,
+  XED_ICLASS_VGETMANTPBF16, +
  XED_ICLASS_VGETMANTPD,
  XED_ICLASS_VGETMANTPH, @@ -6417,6 +6833,8 @@
  XED_ICLASS_VMASKMOVPS,
+  XED_ICLASS_VMAXPBF16, +
  XED_ICLASS_VMAXPD,
  XED_ICLASS_VMAXPH, @@ -6435,6 +6853,22 @@
  XED_ICLASS_VMFUNC,
+  XED_ICLASS_VMINMAXNEPBF16, +
+  XED_ICLASS_VMINMAXPD, +
+  XED_ICLASS_VMINMAXPH, +
+  XED_ICLASS_VMINMAXPS, +
+  XED_ICLASS_VMINMAXSD, +
+  XED_ICLASS_VMINMAXSH, +
+  XED_ICLASS_VMINMAXSS, +
+  XED_ICLASS_VMINPBF16, +
  XED_ICLASS_VMINPD,
  XED_ICLASS_VMINPH, @@ -6503,6 +6937,14 @@
  XED_ICLASS_VMOVQ,
+  XED_ICLASS_VMOVRSB, +
+  XED_ICLASS_VMOVRSD, +
+  XED_ICLASS_VMOVRSQ, +
+  XED_ICLASS_VMOVRSW, +
  XED_ICLASS_VMOVSD,
  XED_ICLASS_VMOVSH, @@ -6533,6 +6975,8 @@
  XED_ICLASS_VMSAVE,
+  XED_ICLASS_VMULNEPBF16, +
  XED_ICLASS_VMULPD,
  XED_ICLASS_VMULPH, @@ -7273,6 +7717,8 @@
  XED_ICLASS_VRCP28SS,
+  XED_ICLASS_VRCPPBF16, +
  XED_ICLASS_VRCPPH,
  XED_ICLASS_VRCPPS, @@ -7281,6 +7727,8 @@
  XED_ICLASS_VRCPSS,
+  XED_ICLASS_VREDUCENEPBF16, +
  XED_ICLASS_VREDUCEPD,
  XED_ICLASS_VREDUCEPH, @@ -7293,6 +7741,8 @@
  XED_ICLASS_VREDUCESS,
+  XED_ICLASS_VRNDSCALENEPBF16, +
  XED_ICLASS_VRNDSCALEPD,
  XED_ICLASS_VRNDSCALEPH, @@ -7329,6 +7779,8 @@
  XED_ICLASS_VRSQRT28SS,
+  XED_ICLASS_VRSQRTPBF16, +
  XED_ICLASS_VRSQRTPH,
  XED_ICLASS_VRSQRTPS, @@ -7337,6 +7789,8 @@
  XED_ICLASS_VRSQRTSS,
+  XED_ICLASS_VSCALEFPBF16, +
  XED_ICLASS_VSCALEFPD,
  XED_ICLASS_VSCALEFPH, @@ -7401,6 +7855,8 @@
  XED_ICLASS_VSM4RNDS4,
+  XED_ICLASS_VSQRTNEPBF16, +
  XED_ICLASS_VSQRTPD,
  XED_ICLASS_VSQRTPH, @@ -7415,6 +7871,8 @@
  XED_ICLASS_VSTMXCSR,
+  XED_ICLASS_VSUBNEPBF16, +
  XED_ICLASS_VSUBPD,
  XED_ICLASS_VSUBPH, @@ -7437,6 +7895,12 @@
  XED_ICLASS_VUCOMISS,
+  XED_ICLASS_VUCOMXSD, +
+  XED_ICLASS_VUCOMXSH, +
+  XED_ICLASS_VUCOMXSS, +
  XED_ICLASS_VUNPCKHPD,
  XED_ICLASS_VUNPCKHPS, @@ -14985,6 +15449,20 @@

+

+ + +

◆ XED_ICLASS_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_MOVRS_DEFINED   1
+
+
@@ -17435,6 +17913,20 @@

+ + + +

◆ XED_ICLASS_PREFETCHRST2_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_PREFETCHRST2_DEFINED   1
+
+
@@ -20487,6 +20979,118 @@

+ + + +

◆ XED_ICLASS_T2RPNTLVWZ0_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ0_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ0RS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ0RS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ0RST1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ0RST1_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ0T1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ0T1_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ1_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ1RS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ1RS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ1RST1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ1RST1_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_T2RPNTLVWZ1T1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_T2RPNTLVWZ1T1_DEFINED   1
+
+
@@ -20515,6 +21119,104 @@

+ + + +

◆ XED_ICLASS_TCONJTCMMIMFP16PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCONJTCMMIMFP16PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCONJTFP16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCONJTFP16_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCVTROWD2PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCVTROWD2PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCVTROWPS2PBF16H_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCVTROWPS2PBF16H_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCVTROWPS2PBF16L_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCVTROWPS2PBF16L_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCVTROWPS2PHH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCVTROWPS2PHH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TCVTROWPS2PHL_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TCVTROWPS2PHL_DEFINED   1
+
+
@@ -20543,6 +21245,34 @@

+ + + +

◆ XED_ICLASS_TDPBF8PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TDPBF8PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TDPBHF8PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TDPBHF8PS_DEFINED   1
+
+
@@ -20613,6 +21343,34 @@

+ + + +

◆ XED_ICLASS_TDPHBF8PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TDPHBF8PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TDPHF8PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TDPHF8PS_DEFINED   1
+
+
@@ -20655,6 +21413,34 @@

+ + + +

◆ XED_ICLASS_TILELOADDRS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TILELOADDRS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TILELOADDRST1_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TILELOADDRST1_DEFINED   1
+
+
@@ -20669,6 +21455,20 @@

+ + + +

◆ XED_ICLASS_TILEMOVROW_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TILEMOVROW_DEFINED   1
+
+
@@ -20725,6 +21525,20 @@

+ + + +

◆ XED_ICLASS_TMMULTF32PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TMMULTF32PS_DEFINED   1
+
+
@@ -20739,6 +21553,90 @@

+ + + +

◆ XED_ICLASS_TTCMMIMFP16PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTCMMIMFP16PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TTCMMRLFP16PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTCMMRLFP16PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TTDPBF16PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTDPBF16PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TTDPFP16PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTDPFP16PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TTMMULTF32PS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTMMULTF32PS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_TTRANSPOSED_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_TTRANSPOSED_DEFINED   1
+
+
@@ -21019,6 +21917,20 @@

+ + + +

◆ XED_ICLASS_VADDNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VADDNEPBF16_DEFINED   1
+
+
@@ -21607,6 +22519,20 @@

+ + + +

◆ XED_ICLASS_VCMPPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCMPPBF16_DEFINED   1
+
+
@@ -21761,6 +22687,132 @@

+ + + +

◆ XED_ICLASS_VCOMSBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCOMSBF16_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCOMXSD_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCOMXSD_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCOMXSH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCOMXSH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCOMXSS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCOMXSS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVT2PS2PHX_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVT2PS2PHX_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTBIASPH2BF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTBIASPH2BF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTBIASPH2BF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTBIASPH2BF8S_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTBIASPH2HF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTBIASPH2HF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTBIASPH2HF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTBIASPH2HF8S_DEFINED   1
+
+
@@ -21803,6 +22855,76 @@

+ + + +

◆ XED_ICLASS_VCVTHF82PH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTHF82PH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNE2PH2BF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNE2PH2BF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNE2PH2BF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNE2PH2BF8S_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNE2PH2HF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNE2PH2HF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNE2PH2HF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNE2PH2HF8S_DEFINED   1
+
+
@@ -21817,6 +22939,34 @@

+ + + +

◆ XED_ICLASS_VCVTNEBF162IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEBF162IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNEBF162IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEBF162IUBS_DEFINED   1
+
+
@@ -21873,6 +23023,62 @@

+ + + +

◆ XED_ICLASS_VCVTNEPH2BF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEPH2BF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNEPH2BF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEPH2BF8S_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNEPH2HF8_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEPH2HF8_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTNEPH2HF8S_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTNEPH2HF8S_DEFINED   1
+
+
@@ -21985,6 +23191,34 @@

+ + + +

◆ XED_ICLASS_VCVTPH2IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTPH2IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTPH2IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTPH2IUBS_DEFINED   1
+
+
@@ -22111,6 +23345,34 @@

+ + + +

◆ XED_ICLASS_VCVTPS2IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTPS2IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTPS2IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTPS2IUBS_DEFINED   1
+
+
@@ -22447,6 +23709,34 @@

+ + + +

◆ XED_ICLASS_VCVTTNEBF162IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTNEBF162IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTTNEBF162IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTNEBF162IUBS_DEFINED   1
+
+
@@ -22461,6 +23751,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPD2DQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPD2DQS_DEFINED   1
+
+
@@ -22475,6 +23779,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPD2QQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPD2QQS_DEFINED   1
+
+
@@ -22489,6 +23807,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPD2UDQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPD2UDQS_DEFINED   1
+
+
@@ -22503,6 +23835,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPD2UQQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPD2UQQS_DEFINED   1
+
+
@@ -22517,6 +23863,34 @@

+ + + +

◆ XED_ICLASS_VCVTTPH2IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPH2IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTTPH2IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPH2IUBS_DEFINED   1
+
+
@@ -22601,6 +23975,48 @@

+ + + +

◆ XED_ICLASS_VCVTTPS2DQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2DQS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTTPS2IBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2IBS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VCVTTPS2IUBS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2IUBS_DEFINED   1
+
+
@@ -22615,6 +24031,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPS2QQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2QQS_DEFINED   1
+
+
@@ -22629,6 +24059,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPS2UDQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2UDQS_DEFINED   1
+
+
@@ -22643,6 +24087,20 @@

+ + + +

◆ XED_ICLASS_VCVTTPS2UQQS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTPS2UQQS_DEFINED   1
+
+
@@ -22657,6 +24115,20 @@

+ + + +

◆ XED_ICLASS_VCVTTSD2SIS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTSD2SIS_DEFINED   1
+
+
@@ -22671,6 +24143,20 @@

+ + + +

◆ XED_ICLASS_VCVTTSD2USIS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTSD2USIS_DEFINED   1
+
+
@@ -22713,6 +24199,20 @@

+ + + +

◆ XED_ICLASS_VCVTTSS2SIS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTSS2SIS_DEFINED   1
+
+
@@ -22727,6 +24227,20 @@

+ + + +

◆ XED_ICLASS_VCVTTSS2USIS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VCVTTSS2USIS_DEFINED   1
+
+
@@ -22895,6 +24409,20 @@

+ + + +

◆ XED_ICLASS_VDIVNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VDIVNEPBF16_DEFINED   1
+
+
@@ -23007,6 +24535,20 @@

+ + + +

◆ XED_ICLASS_VDPPHPS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VDPPHPS_DEFINED   1
+
+
@@ -23371,6 +24913,20 @@

+ + + +

◆ XED_ICLASS_VFMADD132NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMADD132NEPBF16_DEFINED   1
+
+
@@ -23455,6 +25011,20 @@

+ + + +

◆ XED_ICLASS_VFMADD213NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMADD213NEPBF16_DEFINED   1
+
+
@@ -23539,6 +25109,20 @@

+ + + +

◆ XED_ICLASS_VFMADD231NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMADD231NEPBF16_DEFINED   1
+
+
@@ -23861,6 +25445,20 @@

+ + + +

◆ XED_ICLASS_VFMSUB132NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMSUB132NEPBF16_DEFINED   1
+
+
@@ -23945,6 +25543,20 @@

+ + + +

◆ XED_ICLASS_VFMSUB213NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMSUB213NEPBF16_DEFINED   1
+
+
@@ -24029,6 +25641,20 @@

+ + + +

◆ XED_ICLASS_VFMSUB231NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFMSUB231NEPBF16_DEFINED   1
+
+
@@ -24351,6 +25977,20 @@

+ + + +

◆ XED_ICLASS_VFNMADD132NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMADD132NEPBF16_DEFINED   1
+
+
@@ -24435,6 +26075,20 @@

+ + + +

◆ XED_ICLASS_VFNMADD213NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMADD213NEPBF16_DEFINED   1
+
+
@@ -24519,6 +26173,20 @@

+ + + +

◆ XED_ICLASS_VFNMADD231NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMADD231NEPBF16_DEFINED   1
+
+
@@ -24659,6 +26327,20 @@

+ + + +

◆ XED_ICLASS_VFNMSUB132NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMSUB132NEPBF16_DEFINED   1
+
+
@@ -24743,6 +26425,20 @@

+ + + +

◆ XED_ICLASS_VFNMSUB213NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMSUB213NEPBF16_DEFINED   1
+
+
@@ -24827,6 +26523,20 @@

+ + + +

◆ XED_ICLASS_VFNMSUB231NEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFNMSUB231NEPBF16_DEFINED   1
+
+
@@ -24967,6 +26677,20 @@

+ + + +

◆ XED_ICLASS_VFPCLASSPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VFPCLASSPBF16_DEFINED   1
+
+
@@ -25275,6 +26999,20 @@

+ + + +

◆ XED_ICLASS_VGETEXPPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VGETEXPPBF16_DEFINED   1
+
+
@@ -25359,6 +27097,20 @@

+ + + +

◆ XED_ICLASS_VGETMANTPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VGETMANTPBF16_DEFINED   1
+
+
@@ -25765,6 +27517,20 @@

+ + + +

◆ XED_ICLASS_VMAXPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMAXPBF16_DEFINED   1
+
+
@@ -25891,6 +27657,118 @@

+ + + +

◆ XED_ICLASS_VMINMAXNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXNEPBF16_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXPD_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXPD_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXPH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXPH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXPS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXPS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXSD_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXSD_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXSH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXSH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINMAXSS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINMAXSS_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMINPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMINPBF16_DEFINED   1
+
+
@@ -26367,6 +28245,62 @@

+ + + +

◆ XED_ICLASS_VMOVRSB_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMOVRSB_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMOVRSD_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMOVRSD_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMOVRSQ_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMOVRSQ_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VMOVRSW_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMOVRSW_DEFINED   1
+
+
@@ -26577,6 +28511,20 @@

+ + + +

◆ XED_ICLASS_VMULNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VMULNEPBF16_DEFINED   1
+
+
@@ -31757,6 +33705,20 @@

+ + + +

◆ XED_ICLASS_VRCPPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VRCPPBF16_DEFINED   1
+
+
@@ -31813,6 +33775,20 @@

+ + + +

◆ XED_ICLASS_VREDUCENEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VREDUCENEPBF16_DEFINED   1
+
+
@@ -31897,6 +33873,20 @@

+ + + +

◆ XED_ICLASS_VRNDSCALENEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VRNDSCALENEPBF16_DEFINED   1
+
+
@@ -32149,6 +34139,20 @@

+ + + +

◆ XED_ICLASS_VRSQRTPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VRSQRTPBF16_DEFINED   1
+
+
@@ -32205,6 +34209,20 @@

+ + + +

◆ XED_ICLASS_VSCALEFPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VSCALEFPBF16_DEFINED   1
+
+
@@ -32653,6 +34671,20 @@

+ + + +

◆ XED_ICLASS_VSQRTNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VSQRTNEPBF16_DEFINED   1
+
+
@@ -32751,6 +34783,20 @@

+ + + +

◆ XED_ICLASS_VSUBNEPBF16_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VSUBNEPBF16_DEFINED   1
+
+
@@ -32905,6 +34951,48 @@

+ + + +

◆ XED_ICLASS_VUCOMXSD_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VUCOMXSD_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VUCOMXSH_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VUCOMXSH_DEFINED   1
+
+ +
+
+ +

◆ XED_ICLASS_VUCOMXSS_DEFINED

+ +
+
+ + + + +
#define XED_ICLASS_VUCOMXSS_DEFINED   1
+
+
@@ -34134,6 +36222,7 @@

XED_ICLASS_MOVNTSS  XED_ICLASS_MOVQ  XED_ICLASS_MOVQ2DQ  +XED_ICLASS_MOVRS  XED_ICLASS_MOVSB  XED_ICLASS_MOVSD  XED_ICLASS_MOVSD_XMM  @@ -34309,6 +36398,7 @@

XED_ICLASS_PREFETCHIT0  XED_ICLASS_PREFETCHIT1  XED_ICLASS_PREFETCHNTA  +XED_ICLASS_PREFETCHRST2  XED_ICLASS_PREFETCHT0  XED_ICLASS_PREFETCHT1  XED_ICLASS_PREFETCHT2  @@ -34529,24 +36619,53 @@

XED_ICLASS_SYSRET64  XED_ICLASS_SYSRET_AMD  XED_ICLASS_T1MSKC  +XED_ICLASS_T2RPNTLVWZ0  +XED_ICLASS_T2RPNTLVWZ0RS  +XED_ICLASS_T2RPNTLVWZ0RST1  +XED_ICLASS_T2RPNTLVWZ0T1  +XED_ICLASS_T2RPNTLVWZ1  +XED_ICLASS_T2RPNTLVWZ1RS  +XED_ICLASS_T2RPNTLVWZ1RST1  +XED_ICLASS_T2RPNTLVWZ1T1  XED_ICLASS_TCMMIMFP16PS  XED_ICLASS_TCMMRLFP16PS  +XED_ICLASS_TCONJTCMMIMFP16PS  +XED_ICLASS_TCONJTFP16  +XED_ICLASS_TCVTROWD2PS  +XED_ICLASS_TCVTROWPS2PBF16H  +XED_ICLASS_TCVTROWPS2PBF16L  +XED_ICLASS_TCVTROWPS2PHH  +XED_ICLASS_TCVTROWPS2PHL  XED_ICLASS_TDCALL  XED_ICLASS_TDPBF16PS  +XED_ICLASS_TDPBF8PS  +XED_ICLASS_TDPBHF8PS  XED_ICLASS_TDPBSSD  XED_ICLASS_TDPBSUD  XED_ICLASS_TDPBUSD  XED_ICLASS_TDPBUUD  XED_ICLASS_TDPFP16PS  +XED_ICLASS_TDPHBF8PS  +XED_ICLASS_TDPHF8PS  XED_ICLASS_TEST  XED_ICLASS_TESTUI  XED_ICLASS_TILELOADD  +XED_ICLASS_TILELOADDRS  +XED_ICLASS_TILELOADDRST1  XED_ICLASS_TILELOADDT1  +XED_ICLASS_TILEMOVROW  XED_ICLASS_TILERELEASE  XED_ICLASS_TILESTORED  XED_ICLASS_TILEZERO  XED_ICLASS_TLBSYNC  +XED_ICLASS_TMMULTF32PS  XED_ICLASS_TPAUSE  +XED_ICLASS_TTCMMIMFP16PS  +XED_ICLASS_TTCMMRLFP16PS  +XED_ICLASS_TTDPBF16PS  +XED_ICLASS_TTDPFP16PS  +XED_ICLASS_TTMMULTF32PS  +XED_ICLASS_TTRANSPOSED  XED_ICLASS_TZCNT  XED_ICLASS_TZMSK  XED_ICLASS_UCOMISD  @@ -34567,6 +36686,7 @@

XED_ICLASS_V4FMADDSS  XED_ICLASS_V4FNMADDPS  XED_ICLASS_V4FNMADDSS  +XED_ICLASS_VADDNEPBF16  XED_ICLASS_VADDPD  XED_ICLASS_VADDPH  XED_ICLASS_VADDPS  @@ -34609,6 +36729,7 @@

XED_ICLASS_VBROADCASTI64X4  XED_ICLASS_VBROADCASTSD  XED_ICLASS_VBROADCASTSS  +XED_ICLASS_VCMPPBF16  XED_ICLASS_VCMPPD  XED_ICLASS_VCMPPH  XED_ICLASS_VCMPPS  @@ -34620,14 +36741,34 @@

XED_ICLASS_VCOMISS  XED_ICLASS_VCOMPRESSPD  XED_ICLASS_VCOMPRESSPS  +XED_ICLASS_VCOMSBF16  +XED_ICLASS_VCOMXSD  +XED_ICLASS_VCOMXSH  +XED_ICLASS_VCOMXSS  +XED_ICLASS_VCVT2PS2PHX  +XED_ICLASS_VCVTBIASPH2BF8  +XED_ICLASS_VCVTBIASPH2BF8S  +XED_ICLASS_VCVTBIASPH2HF8  +XED_ICLASS_VCVTBIASPH2HF8S  XED_ICLASS_VCVTDQ2PD  XED_ICLASS_VCVTDQ2PH  XED_ICLASS_VCVTDQ2PS  +XED_ICLASS_VCVTHF82PH  +XED_ICLASS_VCVTNE2PH2BF8  +XED_ICLASS_VCVTNE2PH2BF8S  +XED_ICLASS_VCVTNE2PH2HF8  +XED_ICLASS_VCVTNE2PH2HF8S  XED_ICLASS_VCVTNE2PS2BF16  +XED_ICLASS_VCVTNEBF162IBS  +XED_ICLASS_VCVTNEBF162IUBS  XED_ICLASS_VCVTNEEBF162PS  XED_ICLASS_VCVTNEEPH2PS  XED_ICLASS_VCVTNEOBF162PS  XED_ICLASS_VCVTNEOPH2PS  +XED_ICLASS_VCVTNEPH2BF8  +XED_ICLASS_VCVTNEPH2BF8S  +XED_ICLASS_VCVTNEPH2HF8  +XED_ICLASS_VCVTNEPH2HF8S  XED_ICLASS_VCVTNEPS2BF16  XED_ICLASS_VCVTPD2DQ  XED_ICLASS_VCVTPD2PH  @@ -34636,6 +36777,8 @@

XED_ICLASS_VCVTPD2UDQ  XED_ICLASS_VCVTPD2UQQ  XED_ICLASS_VCVTPH2DQ  +XED_ICLASS_VCVTPH2IBS  +XED_ICLASS_VCVTPH2IUBS  XED_ICLASS_VCVTPH2PD  XED_ICLASS_VCVTPH2PS  XED_ICLASS_VCVTPH2PSX  @@ -34645,6 +36788,8 @@

XED_ICLASS_VCVTPH2UW  XED_ICLASS_VCVTPH2W  XED_ICLASS_VCVTPS2DQ  +XED_ICLASS_VCVTPS2IBS  +XED_ICLASS_VCVTPS2IUBS  XED_ICLASS_VCVTPS2PD  XED_ICLASS_VCVTPS2PH  XED_ICLASS_VCVTPS2PHX  @@ -34669,26 +36814,44 @@

XED_ICLASS_VCVTSS2SH  XED_ICLASS_VCVTSS2SI  XED_ICLASS_VCVTSS2USI  +XED_ICLASS_VCVTTNEBF162IBS  +XED_ICLASS_VCVTTNEBF162IUBS  XED_ICLASS_VCVTTPD2DQ  +XED_ICLASS_VCVTTPD2DQS  XED_ICLASS_VCVTTPD2QQ  +XED_ICLASS_VCVTTPD2QQS  XED_ICLASS_VCVTTPD2UDQ  +XED_ICLASS_VCVTTPD2UDQS  XED_ICLASS_VCVTTPD2UQQ  +XED_ICLASS_VCVTTPD2UQQS  XED_ICLASS_VCVTTPH2DQ  +XED_ICLASS_VCVTTPH2IBS  +XED_ICLASS_VCVTTPH2IUBS  XED_ICLASS_VCVTTPH2QQ  XED_ICLASS_VCVTTPH2UDQ  XED_ICLASS_VCVTTPH2UQQ  XED_ICLASS_VCVTTPH2UW  XED_ICLASS_VCVTTPH2W  XED_ICLASS_VCVTTPS2DQ  +XED_ICLASS_VCVTTPS2DQS  +XED_ICLASS_VCVTTPS2IBS  +XED_ICLASS_VCVTTPS2IUBS  XED_ICLASS_VCVTTPS2QQ  +XED_ICLASS_VCVTTPS2QQS  XED_ICLASS_VCVTTPS2UDQ  +XED_ICLASS_VCVTTPS2UDQS  XED_ICLASS_VCVTTPS2UQQ  +XED_ICLASS_VCVTTPS2UQQS  XED_ICLASS_VCVTTSD2SI  +XED_ICLASS_VCVTTSD2SIS  XED_ICLASS_VCVTTSD2USI  +XED_ICLASS_VCVTTSD2USIS  XED_ICLASS_VCVTTSH2SI  XED_ICLASS_VCVTTSH2USI  XED_ICLASS_VCVTTSS2SI  +XED_ICLASS_VCVTTSS2SIS  XED_ICLASS_VCVTTSS2USI  +XED_ICLASS_VCVTTSS2USIS  XED_ICLASS_VCVTUDQ2PD  XED_ICLASS_VCVTUDQ2PH  XED_ICLASS_VCVTUDQ2PS  @@ -34701,6 +36864,7 @@

XED_ICLASS_VCVTUW2PH  XED_ICLASS_VCVTW2PH  XED_ICLASS_VDBPSADBW  +XED_ICLASS_VDIVNEPBF16  XED_ICLASS_VDIVPD  XED_ICLASS_VDIVPH  XED_ICLASS_VDIVPS  @@ -34709,6 +36873,7 @@

XED_ICLASS_VDIVSS  XED_ICLASS_VDPBF16PS  XED_ICLASS_VDPPD  +XED_ICLASS_VDPPHPS  XED_ICLASS_VDPPS  XED_ICLASS_VERR  XED_ICLASS_VERW  @@ -34735,18 +36900,21 @@

XED_ICLASS_VFIXUPIMMPS  XED_ICLASS_VFIXUPIMMSD  XED_ICLASS_VFIXUPIMMSS  +XED_ICLASS_VFMADD132NEPBF16  XED_ICLASS_VFMADD132PD  XED_ICLASS_VFMADD132PH  XED_ICLASS_VFMADD132PS  XED_ICLASS_VFMADD132SD  XED_ICLASS_VFMADD132SH  XED_ICLASS_VFMADD132SS  +XED_ICLASS_VFMADD213NEPBF16  XED_ICLASS_VFMADD213PD  XED_ICLASS_VFMADD213PH  XED_ICLASS_VFMADD213PS  XED_ICLASS_VFMADD213SD  XED_ICLASS_VFMADD213SH  XED_ICLASS_VFMADD213SS  +XED_ICLASS_VFMADD231NEPBF16  XED_ICLASS_VFMADD231PD  XED_ICLASS_VFMADD231PH  XED_ICLASS_VFMADD231PS  @@ -34770,18 +36938,21 @@

XED_ICLASS_VFMADDSUB231PS  XED_ICLASS_VFMADDSUBPD  XED_ICLASS_VFMADDSUBPS  +XED_ICLASS_VFMSUB132NEPBF16  XED_ICLASS_VFMSUB132PD  XED_ICLASS_VFMSUB132PH  XED_ICLASS_VFMSUB132PS  XED_ICLASS_VFMSUB132SD  XED_ICLASS_VFMSUB132SH  XED_ICLASS_VFMSUB132SS  +XED_ICLASS_VFMSUB213NEPBF16  XED_ICLASS_VFMSUB213PD  XED_ICLASS_VFMSUB213PH  XED_ICLASS_VFMSUB213PS  XED_ICLASS_VFMSUB213SD  XED_ICLASS_VFMSUB213SH  XED_ICLASS_VFMSUB213SS  +XED_ICLASS_VFMSUB231NEPBF16  XED_ICLASS_VFMSUB231PD  XED_ICLASS_VFMSUB231PH  XED_ICLASS_VFMSUB231PS  @@ -34805,18 +36976,21 @@

XED_ICLASS_VFMSUBSS  XED_ICLASS_VFMULCPH  XED_ICLASS_VFMULCSH  +XED_ICLASS_VFNMADD132NEPBF16  XED_ICLASS_VFNMADD132PD  XED_ICLASS_VFNMADD132PH  XED_ICLASS_VFNMADD132PS  XED_ICLASS_VFNMADD132SD  XED_ICLASS_VFNMADD132SH  XED_ICLASS_VFNMADD132SS  +XED_ICLASS_VFNMADD213NEPBF16  XED_ICLASS_VFNMADD213PD  XED_ICLASS_VFNMADD213PH  XED_ICLASS_VFNMADD213PS  XED_ICLASS_VFNMADD213SD  XED_ICLASS_VFNMADD213SH  XED_ICLASS_VFNMADD213SS  +XED_ICLASS_VFNMADD231NEPBF16  XED_ICLASS_VFNMADD231PD  XED_ICLASS_VFNMADD231PH  XED_ICLASS_VFNMADD231PS  @@ -34827,18 +37001,21 @@

XED_ICLASS_VFNMADDPS  XED_ICLASS_VFNMADDSD  XED_ICLASS_VFNMADDSS  +XED_ICLASS_VFNMSUB132NEPBF16  XED_ICLASS_VFNMSUB132PD  XED_ICLASS_VFNMSUB132PH  XED_ICLASS_VFNMSUB132PS  XED_ICLASS_VFNMSUB132SD  XED_ICLASS_VFNMSUB132SH  XED_ICLASS_VFNMSUB132SS  +XED_ICLASS_VFNMSUB213NEPBF16  XED_ICLASS_VFNMSUB213PD  XED_ICLASS_VFNMSUB213PH  XED_ICLASS_VFNMSUB213PS  XED_ICLASS_VFNMSUB213SD  XED_ICLASS_VFNMSUB213SH  XED_ICLASS_VFNMSUB213SS  +XED_ICLASS_VFNMSUB231NEPBF16  XED_ICLASS_VFNMSUB231PD  XED_ICLASS_VFNMSUB231PH  XED_ICLASS_VFNMSUB231PS  @@ -34849,6 +37026,7 @@

XED_ICLASS_VFNMSUBPS  XED_ICLASS_VFNMSUBSD  XED_ICLASS_VFNMSUBSS  +XED_ICLASS_VFPCLASSPBF16  XED_ICLASS_VFPCLASSPD  XED_ICLASS_VFPCLASSPH  XED_ICLASS_VFPCLASSPS  @@ -34871,12 +37049,14 @@

XED_ICLASS_VGATHERPF1QPS  XED_ICLASS_VGATHERQPD  XED_ICLASS_VGATHERQPS  +XED_ICLASS_VGETEXPPBF16  XED_ICLASS_VGETEXPPD  XED_ICLASS_VGETEXPPH  XED_ICLASS_VGETEXPPS  XED_ICLASS_VGETEXPSD  XED_ICLASS_VGETEXPSH  XED_ICLASS_VGETEXPSS  +XED_ICLASS_VGETMANTPBF16  XED_ICLASS_VGETMANTPD  XED_ICLASS_VGETMANTPH  XED_ICLASS_VGETMANTPS  @@ -34906,6 +37086,7 @@

XED_ICLASS_VMASKMOVDQU  XED_ICLASS_VMASKMOVPD  XED_ICLASS_VMASKMOVPS  +XED_ICLASS_VMAXPBF16  XED_ICLASS_VMAXPD  XED_ICLASS_VMAXPH  XED_ICLASS_VMAXPS  @@ -34915,6 +37096,14 @@

XED_ICLASS_VMCALL  XED_ICLASS_VMCLEAR  XED_ICLASS_VMFUNC  +XED_ICLASS_VMINMAXNEPBF16  +XED_ICLASS_VMINMAXPD  +XED_ICLASS_VMINMAXPH  +XED_ICLASS_VMINMAXPS  +XED_ICLASS_VMINMAXSD  +XED_ICLASS_VMINMAXSH  +XED_ICLASS_VMINMAXSS  +XED_ICLASS_VMINPBF16  XED_ICLASS_VMINPD  XED_ICLASS_VMINPH  XED_ICLASS_VMINPS  @@ -34949,6 +37138,10 @@

XED_ICLASS_VMOVNTPD  XED_ICLASS_VMOVNTPS  XED_ICLASS_VMOVQ  +XED_ICLASS_VMOVRSB  +XED_ICLASS_VMOVRSD  +XED_ICLASS_VMOVRSQ  +XED_ICLASS_VMOVRSW  XED_ICLASS_VMOVSD  XED_ICLASS_VMOVSH  XED_ICLASS_VMOVSHDUP  @@ -34964,6 +37157,7 @@

XED_ICLASS_VMRESUME  XED_ICLASS_VMRUN  XED_ICLASS_VMSAVE  +XED_ICLASS_VMULNEPBF16  XED_ICLASS_VMULPD  XED_ICLASS_VMULPH  XED_ICLASS_VMULPS  @@ -35334,16 +37528,19 @@

XED_ICLASS_VRCP28PS  XED_ICLASS_VRCP28SD  XED_ICLASS_VRCP28SS  +XED_ICLASS_VRCPPBF16  XED_ICLASS_VRCPPH  XED_ICLASS_VRCPPS  XED_ICLASS_VRCPSH  XED_ICLASS_VRCPSS  +XED_ICLASS_VREDUCENEPBF16  XED_ICLASS_VREDUCEPD  XED_ICLASS_VREDUCEPH  XED_ICLASS_VREDUCEPS  XED_ICLASS_VREDUCESD  XED_ICLASS_VREDUCESH  XED_ICLASS_VREDUCESS  +XED_ICLASS_VRNDSCALENEPBF16  XED_ICLASS_VRNDSCALEPD  XED_ICLASS_VRNDSCALEPH  XED_ICLASS_VRNDSCALEPS  @@ -35362,10 +37559,12 @@

XED_ICLASS_VRSQRT28PS  XED_ICLASS_VRSQRT28SD  XED_ICLASS_VRSQRT28SS  +XED_ICLASS_VRSQRTPBF16  XED_ICLASS_VRSQRTPH  XED_ICLASS_VRSQRTPS  XED_ICLASS_VRSQRTSH  XED_ICLASS_VRSQRTSS  +XED_ICLASS_VSCALEFPBF16  XED_ICLASS_VSCALEFPD  XED_ICLASS_VSCALEFPH  XED_ICLASS_VSCALEFPS  @@ -35398,6 +37597,7 @@

XED_ICLASS_VSM3RNDS2  XED_ICLASS_VSM4KEY4  XED_ICLASS_VSM4RNDS4  +XED_ICLASS_VSQRTNEPBF16  XED_ICLASS_VSQRTPD  XED_ICLASS_VSQRTPH  XED_ICLASS_VSQRTPS  @@ -35405,6 +37605,7 @@

XED_ICLASS_VSQRTSH  XED_ICLASS_VSQRTSS  XED_ICLASS_VSTMXCSR  +XED_ICLASS_VSUBNEPBF16  XED_ICLASS_VSUBPD  XED_ICLASS_VSUBPH  XED_ICLASS_VSUBPS  @@ -35416,6 +37617,9 @@

XED_ICLASS_VUCOMISD  XED_ICLASS_VUCOMISH  XED_ICLASS_VUCOMISS  +XED_ICLASS_VUCOMXSD  +XED_ICLASS_VUCOMXSH  +XED_ICLASS_VUCOMXSS  XED_ICLASS_VUNPCKHPD  XED_ICLASS_VUNPCKHPS  XED_ICLASS_VUNPCKLPD  diff --git a/ref-manual/xed-iclass-enum_8h.js b/ref-manual/xed-iclass-enum_8h.js index 29d1536..93bdb32 100644 --- a/ref-manual/xed-iclass-enum_8h.js +++ b/ref-manual/xed-iclass-enum_8h.js @@ -531,6 +531,7 @@ var xed_iclass_enum_8h = [ "XED_ICLASS_MOVNTSS_DEFINED", "xed-iclass-enum_8h.html#a2f0743fa282c66722b95d9ef315fd4e1", null ], [ "XED_ICLASS_MOVQ2DQ_DEFINED", "xed-iclass-enum_8h.html#a2f3d4a68c352a5ccc988aadfc21c6434", null ], [ "XED_ICLASS_MOVQ_DEFINED", "xed-iclass-enum_8h.html#af1cce310070c33290d14e8a77d01a2d6", null ], + [ "XED_ICLASS_MOVRS_DEFINED", "xed-iclass-enum_8h.html#afd2b9471383aa687ef610d1206aded5f", null ], [ "XED_ICLASS_MOVSB_DEFINED", "xed-iclass-enum_8h.html#a1083d3768d30b30f5c1e225058c4f939", null ], [ "XED_ICLASS_MOVSD_DEFINED", "xed-iclass-enum_8h.html#a3e2dcf839a43688560c7b453fda62cab", null ], [ "XED_ICLASS_MOVSD_XMM_DEFINED", "xed-iclass-enum_8h.html#a94265a8ed6d59e54fad4c661d3e6c88a", null ], @@ -706,6 +707,7 @@ var xed_iclass_enum_8h = [ "XED_ICLASS_PREFETCHIT0_DEFINED", "xed-iclass-enum_8h.html#a63295db2789df5246c422fb371a79c6d", null ], [ "XED_ICLASS_PREFETCHIT1_DEFINED", "xed-iclass-enum_8h.html#a07169fe471949965ade38daf09678594", null ], [ "XED_ICLASS_PREFETCHNTA_DEFINED", "xed-iclass-enum_8h.html#aa7062e460663bcdf0ef7c7a90f796e10", null ], + [ "XED_ICLASS_PREFETCHRST2_DEFINED", "xed-iclass-enum_8h.html#af87d1fb8269ab140fd0d4e2e4bd9b676", null ], [ "XED_ICLASS_PREFETCHT0_DEFINED", "xed-iclass-enum_8h.html#a443b31cb42f8ffa3b90501214a51c2b8", null ], [ "XED_ICLASS_PREFETCHT1_DEFINED", "xed-iclass-enum_8h.html#ae3350fadd3913bce7e7aaa3611de3169", null ], [ "XED_ICLASS_PREFETCHT2_DEFINED", "xed-iclass-enum_8h.html#a4de16dc6cef39a3384b2def1d1022b71", null ], @@ -924,24 +926,53 @@ var xed_iclass_enum_8h = [ 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"xed-iclass-enum_8h.html#a734f64aa7e4a74cf290f1c1b90195af2", null ], + [ "XED_ICLASS_T2RPNTLVWZ1T1_DEFINED", "xed-iclass-enum_8h.html#a20d217283fa476134db86861efbd6239", null ], [ "XED_ICLASS_TCMMIMFP16PS_DEFINED", "xed-iclass-enum_8h.html#a3344e901b48f7186189d829bd60a0598", null ], [ "XED_ICLASS_TCMMRLFP16PS_DEFINED", "xed-iclass-enum_8h.html#a92045e93c561b68f042aa2d713e562e8", null ], + [ "XED_ICLASS_TCONJTCMMIMFP16PS_DEFINED", "xed-iclass-enum_8h.html#a1bbe2056f584a0ea27b45bd988bc997b", null ], + [ "XED_ICLASS_TCONJTFP16_DEFINED", "xed-iclass-enum_8h.html#afbea51078f2de2b238e019fb7ab48fd4", null ], + [ "XED_ICLASS_TCVTROWD2PS_DEFINED", "xed-iclass-enum_8h.html#ab4581324a3e47b7dd1069412971872d0", null ], + [ "XED_ICLASS_TCVTROWPS2PBF16H_DEFINED", "xed-iclass-enum_8h.html#a35d6043ee9d3c1bef41e044a198b6cba", null ], + [ "XED_ICLASS_TCVTROWPS2PBF16L_DEFINED", "xed-iclass-enum_8h.html#a1a71f45c027020ae1f5e868803532c97", null ], + [ "XED_ICLASS_TCVTROWPS2PHH_DEFINED", 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"xed-iclass-enum_8h.html#ad318511ae9cc50f102251b3c91a1ab9fac4933e16b2e22bb55a853d2ba54bf26d", null ], [ "XED_ICLASS_VUNPCKHPS", "xed-iclass-enum_8h.html#ad318511ae9cc50f102251b3c91a1ab9face65b43b807aacb394894bda97b29335", null ], [ "XED_ICLASS_VUNPCKLPD", "xed-iclass-enum_8h.html#ad318511ae9cc50f102251b3c91a1ab9fa7a9e4dc3f6fc6f11aee4a15f6dd83905", null ], diff --git a/ref-manual/xed-iform-enum_8h.html b/ref-manual/xed-iform-enum_8h.html index c16f874..593d0af 100644 --- a/ref-manual/xed-iform-enum_8h.html +++ b/ref-manual/xed-iform-enum_8h.html @@ -3414,6 +3414,10 @@   #define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED   1   +#define XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED   1 +  +#define XED_IFORM_MOVRS_GPRv_MEMv_DEFINED   1 +  #define XED_IFORM_MOVSB_DEFINED   1   #define XED_IFORM_MOVSD_DEFINED   1 @@ -3604,8 +3608,6 @@   #define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED   1   -#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED   1 -  #define XED_IFORM_NOP_MEMv_0F18r5_DEFINED   1   #define XED_IFORM_NOP_MEMv_0F1F_DEFINED   1 @@ -4484,6 +4486,8 @@   #define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED   1   +#define XED_IFORM_PREFETCHRST2_MEMu8_DEFINED   1 +  #define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED   1   #define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED   1 @@ -4992,6 +4996,10 @@   #define XED_IFORM_RDMSR_DEFINED   1   +#define XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED   1 +  +#define XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED   1 +  #define XED_IFORM_RDMSRLIST_DEFINED   1   #define XED_IFORM_RDPID_GPR32u32_DEFINED   1 @@ -6192,14 +6200,58 @@   #define XED_IFORM_T1MSKC_GPRyy_MEMy_DEFINED   1   +#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED   1 +  +#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED   1 +  #define XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1   #define XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1   +#define XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1 +  +#define XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED   1 +  +#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED   1 +  #define XED_IFORM_TDCALL_DEFINED   1   #define XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16_DEFINED   1   +#define XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED   1 +  +#define XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED   1 +  #define XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8_DEFINED   1   #define XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8_DEFINED   1 @@ -6210,6 +6262,10 @@   #define XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1   +#define XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED   1 +  +#define XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED   1 +  #define XED_IFORM_TEST_AL_IMMb_DEFINED   1   #define XED_IFORM_TEST_GPR8_GPR8_DEFINED   1 @@ -6244,10 +6300,18 @@   #define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED   1 +  +#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED   1 +  #define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX_DEFINED   1   #define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED   1 +  +#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED   1 +  #define XED_IFORM_TILERELEASE_DEFINED   1   #define XED_IFORM_TILESTORED_MEMu32_TMMu32_APX_DEFINED   1 @@ -6258,8 +6322,22 @@   #define XED_IFORM_TLBSYNC_DEFINED   1   +#define XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1 +  #define XED_IFORM_TPAUSE_GPR32u32_DEFINED   1   +#define XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1 +  +#define XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1 +  +#define XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED   1 +  +#define XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED   1 +  +#define XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1 +  +#define XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED   1 +  #define XED_IFORM_TZCNT_GPRv_GPRv_APX_DEFINED   1   #define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED   1 @@ -6342,6 +6420,18 @@   #define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1   +#define XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -6354,6 +6444,8 @@   #define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -6370,6 +6462,8 @@   #define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -6386,6 +6480,8 @@   #define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -6402,10 +6498,14 @@   #define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -6414,6 +6514,8 @@   #define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -6766,6 +6868,18 @@   #define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1 @@ -6774,6 +6888,8 @@   #define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -6794,6 +6910,8 @@   #define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1 @@ -6806,6 +6924,8 @@   #define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -6822,6 +6942,8 @@   #define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1   #define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED   1 @@ -6830,10 +6952,14 @@   #define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1   #define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED   1 @@ -6842,6 +6968,8 @@   #define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED   1   #define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED   1 @@ -6850,6 +6978,8 @@   #define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED   1 @@ -6858,6 +6988,8 @@   #define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1   #define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1 @@ -6882,6 +7014,82 @@   #define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCOMSBF16_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMSBF16_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED   1   #define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED   1 @@ -6894,6 +7102,8 @@   #define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED   1   #define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED   1 @@ -6910,6 +7120,8 @@   #define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED   1   #define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED   1 @@ -6926,6 +7138,8 @@   #define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED   1 @@ -6934,6 +7148,66 @@   #define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED   1   #define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1 @@ -6946,6 +7220,30 @@   #define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED   1   #define XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED   1 @@ -6962,6 +7260,54 @@   #define XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED   1   +#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1   #define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1 @@ -6998,6 +7344,8 @@   #define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1 @@ -7012,6 +7360,8 @@   #define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED   1 @@ -7030,6 +7380,8 @@   #define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1 @@ -7042,6 +7394,8 @@   #define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1 @@ -7054,6 +7408,8 @@   #define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1 @@ -7066,6 +7422,8 @@   #define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1 @@ -7078,10 +7436,36 @@   #define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7090,6 +7474,8 @@   #define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7106,6 +7492,8 @@   #define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED   1   #define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED   1 @@ -7122,6 +7510,8 @@   #define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1 @@ -7134,6 +7524,8 @@   #define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7146,6 +7538,8 @@   #define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1 @@ -7158,6 +7552,8 @@   #define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7170,6 +7566,8 @@   #define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -7182,6 +7580,8 @@   #define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -7198,6 +7598,8 @@   #define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED   1 @@ -7206,6 +7608,30 @@   #define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED   1   #define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED   1 @@ -7218,6 +7644,8 @@   #define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED   1   #define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED   1 @@ -7242,6 +7670,8 @@   #define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED   1   #define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -7254,6 +7684,8 @@   #define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED   1 @@ -7266,6 +7698,8 @@   #define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1 @@ -7278,6 +7712,8 @@   #define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1 @@ -7290,6 +7726,8 @@   #define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1 @@ -7302,6 +7740,8 @@   #define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1 @@ -7316,6 +7756,8 @@   #define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1   #define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1 @@ -7326,6 +7768,8 @@   #define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1 @@ -7334,6 +7778,8 @@   #define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED   1   #define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED   1 @@ -7342,10 +7788,14 @@   #define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED   1   #define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED   1 @@ -7358,38 +7808,56 @@   #define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED   1   #define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED   1 @@ -7400,16 +7868,24 @@   #define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED   1   #define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED   1 @@ -7424,8 +7900,12 @@   #define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED   1 @@ -7438,10 +7918,14 @@   #define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED   1   #define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED   1 @@ -7450,10 +7934,14 @@   #define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED   1   #define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED   1 @@ -7462,10 +7950,38 @@   #define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED   1 @@ -7482,10 +7998,24 @@   #define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1   +#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1 @@ -7494,10 +8024,24 @@   #define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1   #define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1 @@ -7506,10 +8050,24 @@   #define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1   +#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1 @@ -7518,10 +8076,24 @@   #define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7530,10 +8102,36 @@   #define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7542,6 +8140,8 @@   #define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7554,6 +8154,8 @@   #define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1 @@ -7566,6 +8168,8 @@   #define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -7578,6 +8182,8 @@   #define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -7590,6 +8196,8 @@   #define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -7606,6 +8214,8 @@   #define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED   1 @@ -7614,6 +8224,42 @@   #define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1 @@ -7622,10 +8268,24 @@   #define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1 @@ -7634,10 +8294,24 @@   #define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1 @@ -7646,10 +8320,24 @@   #define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED   1   #define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED   1 @@ -7658,38 +8346,70 @@   #define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED   1   #define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED   1   +#define XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED   1   #define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED   1 @@ -7698,22 +8418,46 @@   #define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED   1   #define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED   1   +#define XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1 @@ -7722,6 +8466,8 @@   #define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED   1 @@ -7734,6 +8480,8 @@   #define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED   1 @@ -7746,6 +8494,8 @@   #define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED   1 @@ -7758,6 +8508,8 @@   #define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1   #define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED   1 @@ -7772,6 +8524,8 @@   #define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1   #define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1 @@ -7782,30 +8536,44 @@   #define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1   +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED   1 +  #define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1   #define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED   1   #define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED   1   #define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED   1 @@ -7818,6 +8586,8 @@   #define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1   #define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED   1 @@ -7830,6 +8600,8 @@   #define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED   1   +#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1   #define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED   1 @@ -7846,6 +8618,18 @@   #define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -7858,6 +8642,8 @@   #define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -7874,6 +8660,8 @@   #define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -7890,6 +8678,8 @@   #define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -7906,10 +8696,14 @@   #define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -7918,6 +8712,8 @@   #define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1 @@ -7934,6 +8730,18 @@   #define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1   +#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1 +  +#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1 +  #define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1   #define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1 @@ -8054,6 +8862,8 @@   #define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1 @@ -8062,6 +8872,8 @@   #define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1 @@ -8070,6 +8882,8 @@   #define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1 @@ -8078,6 +8892,8 @@   #define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1 @@ -8086,6 +8902,8 @@   #define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -8098,6 +8916,8 @@   #define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -8106,10 +8926,26 @@   #define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8122,6 +8958,8 @@   #define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8138,6 +8976,8 @@   #define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8154,6 +8994,8 @@   #define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8170,10 +9012,14 @@   #define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8182,6 +9028,20 @@   #define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8194,6 +9054,8 @@   #define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8210,6 +9072,8 @@   #define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8226,6 +9090,8 @@   #define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8242,10 +9108,14 @@   #define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8254,6 +9124,20 @@   #define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8266,6 +9150,8 @@   #define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8282,6 +9168,8 @@   #define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8298,6 +9186,8 @@   #define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8314,10 +9204,14 @@   #define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8326,6 +9220,8 @@   #define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1 @@ -8334,6 +9230,8 @@   #define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1 @@ -8342,6 +9240,8 @@   #define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1   #define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1 @@ -8390,6 +9290,8 @@   #define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8406,6 +9308,8 @@   #define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8422,6 +9326,8 @@   #define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8442,6 +9348,8 @@   #define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8458,6 +9366,8 @@   #define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8474,6 +9384,8 @@   #define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8494,6 +9406,8 @@   #define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8510,6 +9424,8 @@   #define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8526,6 +9442,8 @@   #define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8558,6 +9476,18 @@   #define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1   +#define XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8570,6 +9500,8 @@   #define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8586,6 +9518,8 @@   #define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8602,6 +9536,8 @@   #define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8618,10 +9554,14 @@   #define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8630,6 +9570,20 @@   #define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8642,6 +9596,8 @@   #define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8658,6 +9614,8 @@   #define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8674,6 +9632,8 @@   #define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8690,10 +9650,14 @@   #define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8702,6 +9666,20 @@   #define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8714,6 +9692,8 @@   #define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8730,6 +9710,8 @@   #define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8746,6 +9728,8 @@   #define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8762,10 +9746,14 @@   #define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -8774,6 +9762,8 @@   #define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -8786,6 +9776,8 @@   #define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8802,6 +9794,8 @@   #define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8818,6 +9812,8 @@   #define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8838,6 +9834,8 @@   #define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8854,6 +9852,8 @@   #define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8870,6 +9870,8 @@   #define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8890,6 +9892,8 @@   #define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8906,6 +9910,8 @@   #define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -8922,6 +9928,8 @@   #define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -8998,6 +10006,8 @@   #define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1   #define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1 @@ -9006,6 +10016,20 @@   #define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1   +#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9018,6 +10042,8 @@   #define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9034,6 +10060,8 @@   #define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9050,6 +10078,8 @@   #define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9066,10 +10096,14 @@   #define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9078,6 +10112,20 @@   #define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9090,6 +10138,8 @@   #define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9106,6 +10156,8 @@   #define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9122,6 +10174,8 @@   #define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9138,10 +10192,14 @@   #define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9150,6 +10208,20 @@   #define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9162,6 +10234,8 @@   #define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9178,6 +10252,8 @@   #define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9194,6 +10270,8 @@   #define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9210,10 +10288,14 @@   #define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9222,6 +10304,8 @@   #define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1   #define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1 @@ -9258,6 +10342,18 @@   #define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1   +#define XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9270,6 +10366,8 @@   #define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9286,6 +10384,8 @@   #define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9302,6 +10402,8 @@   #define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9318,10 +10420,14 @@   #define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9330,6 +10436,20 @@   #define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9342,6 +10462,8 @@   #define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9358,6 +10480,8 @@   #define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9374,6 +10498,8 @@   #define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9390,10 +10516,14 @@   #define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9402,6 +10532,20 @@   #define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9414,6 +10558,8 @@   #define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9430,6 +10576,8 @@   #define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9446,6 +10594,8 @@   #define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9462,10 +10612,14 @@   #define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1   #define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1 @@ -9474,6 +10628,8 @@   #define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1   #define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1 @@ -9510,6 +10666,18 @@   #define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1   +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED   1 +  +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED   1 +  +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED   1 +  +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED   1   #define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED   1 @@ -9638,6 +10806,18 @@   #define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1   +#define XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1 @@ -9646,6 +10826,8 @@   #define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1 @@ -9658,6 +10840,8 @@   #define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -9670,6 +10854,8 @@   #define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1 @@ -9678,14 +10864,32 @@   #define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1 @@ -9694,6 +10898,8 @@   #define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -9706,6 +10912,8 @@   #define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1 @@ -9718,6 +10926,8 @@   #define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -9726,14 +10936,20 @@   #define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED   1 @@ -9914,6 +11130,18 @@   #define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED   1   +#define XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -9926,6 +11154,8 @@   #define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9942,6 +11172,8 @@   #define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -9958,6 +11190,8 @@   #define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -9974,10 +11208,14 @@   #define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -9986,12 +11224,86 @@   #define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMCALL_DEFINED   1   #define XED_IFORM_VMCLEAR_MEMq_DEFINED   1   #define XED_IFORM_VMFUNC_DEFINED   1   +#define XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -10004,6 +11316,8 @@   #define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -10020,6 +11334,8 @@   #define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -10036,6 +11352,8 @@   #define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -10052,10 +11370,14 @@   #define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -10064,6 +11386,8 @@   #define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMLAUNCH_DEFINED   1   #define XED_IFORM_VMLOAD_ArAX_DEFINED   1 @@ -10146,6 +11470,8 @@   #define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED   1 +  #define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED   1   #define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED   1 @@ -10154,6 +11480,10 @@   #define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED   1   +#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED   1 +  +#define XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED   1 +  #define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED   1   #define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED   1 @@ -10428,6 +11758,30 @@   #define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED   1   +#define XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1 +  #define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1   #define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED   1 @@ -10574,18 +11928,36 @@   #define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED   1 +  #define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED   1   #define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED   1 +  +#define XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED   1 +  #define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1   #define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1   +#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1   #define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1   +#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VMPTRLD_MEMq_DEFINED   1   #define XED_IFORM_VMPTRST_MEMq_DEFINED   1 @@ -10604,6 +11976,18 @@   #define XED_IFORM_VMSAVE_DEFINED   1   +#define XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -10616,6 +12000,8 @@   #define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -10632,6 +12018,8 @@   #define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -10648,6 +12036,8 @@   #define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -10664,10 +12054,14 @@   #define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -10676,6 +12070,8 @@   #define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED   1   #define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED   1 @@ -11800,38 +13196,86 @@   #define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED   1   +#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8_DEFINED   1   #define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8_DEFINED   1   +#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8_DEFINED   1   #define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8_DEFINED   1   +#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8_DEFINED   1   #define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8_DEFINED   1   +#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8_DEFINED   1   #define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8_DEFINED   1   +#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED   1 @@ -11872,22 +13316,46 @@   #define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8_DEFINED   1   #define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8_DEFINED   1   +#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED   1   #define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED   1 @@ -11928,54 +13396,126 @@   #define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED   1   +#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16_DEFINED   1   #define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16_DEFINED   1   +#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16_DEFINED   1   #define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16_DEFINED   1   +#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16_DEFINED   1   #define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16_DEFINED   1   +#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16_DEFINED   1   #define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16_DEFINED   1   +#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16_DEFINED   1   #define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16_DEFINED   1   +#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1 +  +#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1 +  #define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1   #define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1 @@ -15270,6 +16810,8 @@   #define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -15282,6 +16824,8 @@   #define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -15290,10 +16834,14 @@   #define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1 @@ -15342,6 +16890,18 @@   #define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1   +#define XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -15370,6 +16930,18 @@   #define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED   1   +#define XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1 @@ -15378,6 +16950,8 @@   #define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -15390,6 +16964,8 @@   #define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1 @@ -15402,6 +16978,8 @@   #define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -15410,14 +16988,32 @@   #define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1 +  +#define XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1 +  #define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1 @@ -15426,6 +17022,8 @@   #define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1 @@ -15438,6 +17036,8 @@   #define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1 @@ -15450,6 +17050,8 @@   #define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1 @@ -15458,14 +17060,20 @@   #define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1   #define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1   +#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED   1   #define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED   1 @@ -15538,6 +17146,18 @@   #define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1   +#define XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1 @@ -15566,6 +17186,18 @@   #define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1   +#define XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1 @@ -15574,6 +17206,8 @@   #define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1 @@ -15586,6 +17220,8 @@   #define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -15598,6 +17234,8 @@   #define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1 @@ -15606,14 +17244,20 @@   #define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1   #define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1   #define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1 @@ -15744,22 +17388,58 @@   #define XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8_DEFINED   1   +#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_DEFINED   1   +#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_DEFINED   1   +#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_DEFINED   1   +#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_DEFINED   1   +#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1 +  #define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_DEFINED   1   +#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED   1 @@ -15772,6 +17452,8 @@   #define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED   1 @@ -15788,6 +17470,8 @@   #define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1 @@ -15804,6 +17488,8 @@   #define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED   1 @@ -15820,10 +17506,14 @@   #define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -15832,8 +17522,22 @@   #define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSTMXCSR_MEMd_DEFINED   1   +#define XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1 +  #define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -15846,6 +17550,8 @@   #define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -15862,6 +17568,8 @@   #define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1 @@ -15878,6 +17586,8 @@   #define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1 +  #define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1   #define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1 @@ -15894,10 +17604,14 @@   #define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED   1 @@ -15906,6 +17620,8 @@   #define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED   1 @@ -15930,10 +17646,14 @@   #define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1   +#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED   1   #define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1   +#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1 +  #define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED   1   #define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED   1 @@ -15942,6 +17662,20 @@   #define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1   +#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1 +  +#define XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1 +  +#define XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1 +  +#define XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1 +  +#define XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1 +  #define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED   1   #define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED   1 @@ -16080,6 +17814,10 @@   #define XED_IFORM_WRMSRNS_DEFINED   1   +#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED   1 +  +#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED   1 +  #define XED_IFORM_WRPKRU_DEFINED   1   #define XED_IFORM_WRSSD_MEMu32_GPR32u32_APX_DEFINED   1 @@ -19574,12875 +21312,14613 @@
  XED_IFORM_MOVQ2DQ_XMMdq_MMXq =1650,
-  XED_IFORM_MOVSB =1651, +  XED_IFORM_MOVRS_GPR8i8_MEMi8 =1651,
-  XED_IFORM_MOVSD =1652, +  XED_IFORM_MOVRS_GPRv_MEMv =1652,
-  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd =1653, +  XED_IFORM_MOVSB =1653,
-  XED_IFORM_MOVSD_XMM_XMMdq_MEMsd =1654, +  XED_IFORM_MOVSD =1654,
-  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 =1655, +  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd =1655,
-  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 =1656, +  XED_IFORM_MOVSD_XMM_XMMdq_MEMsd =1656,
-  XED_IFORM_MOVSHDUP_XMMps_MEMps =1657, +  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 =1657,
-  XED_IFORM_MOVSHDUP_XMMps_XMMps =1658, +  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 =1658,
-  XED_IFORM_MOVSLDUP_XMMps_MEMps =1659, +  XED_IFORM_MOVSHDUP_XMMps_MEMps =1659,
-  XED_IFORM_MOVSLDUP_XMMps_XMMps =1660, +  XED_IFORM_MOVSHDUP_XMMps_XMMps =1660,
-  XED_IFORM_MOVSQ =1661, +  XED_IFORM_MOVSLDUP_XMMps_MEMps =1661,
-  XED_IFORM_MOVSS_MEMss_XMMss =1662, +  XED_IFORM_MOVSLDUP_XMMps_XMMps =1662,
-  XED_IFORM_MOVSS_XMMdq_MEMss =1663, +  XED_IFORM_MOVSQ =1663,
-  XED_IFORM_MOVSS_XMMss_XMMss_0F10 =1664, +  XED_IFORM_MOVSS_MEMss_XMMss =1664,
-  XED_IFORM_MOVSS_XMMss_XMMss_0F11 =1665, +  XED_IFORM_MOVSS_XMMdq_MEMss =1665,
-  XED_IFORM_MOVSW =1666, +  XED_IFORM_MOVSS_XMMss_XMMss_0F10 =1666,
-  XED_IFORM_MOVSX_GPRv_GPR16 =1667, +  XED_IFORM_MOVSS_XMMss_XMMss_0F11 =1667,
-  XED_IFORM_MOVSX_GPRv_GPR8 =1668, +  XED_IFORM_MOVSW =1668,
-  XED_IFORM_MOVSX_GPRv_MEMb =1669, +  XED_IFORM_MOVSX_GPRv_GPR16 =1669,
-  XED_IFORM_MOVSX_GPRv_MEMw =1670, +  XED_IFORM_MOVSX_GPRv_GPR8 =1670,
-  XED_IFORM_MOVSXD_GPRv_GPRz =1671, +  XED_IFORM_MOVSX_GPRv_MEMb =1671,
-  XED_IFORM_MOVSXD_GPRv_MEMz =1672, +  XED_IFORM_MOVSX_GPRv_MEMw =1672,
-  XED_IFORM_MOVUPD_MEMpd_XMMpd =1673, +  XED_IFORM_MOVSXD_GPRv_GPRz =1673,
-  XED_IFORM_MOVUPD_XMMpd_MEMpd =1674, +  XED_IFORM_MOVSXD_GPRv_MEMz =1674,
-  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 =1675, +  XED_IFORM_MOVUPD_MEMpd_XMMpd =1675,
-  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 =1676, +  XED_IFORM_MOVUPD_XMMpd_MEMpd =1676,
-  XED_IFORM_MOVUPS_MEMps_XMMps =1677, +  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 =1677,
-  XED_IFORM_MOVUPS_XMMps_MEMps =1678, +  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 =1678,
-  XED_IFORM_MOVUPS_XMMps_XMMps_0F10 =1679, +  XED_IFORM_MOVUPS_MEMps_XMMps =1679,
-  XED_IFORM_MOVUPS_XMMps_XMMps_0F11 =1680, +  XED_IFORM_MOVUPS_XMMps_MEMps =1680,
-  XED_IFORM_MOVZX_GPRv_GPR16 =1681, +  XED_IFORM_MOVUPS_XMMps_XMMps_0F10 =1681,
-  XED_IFORM_MOVZX_GPRv_GPR8 =1682, +  XED_IFORM_MOVUPS_XMMps_XMMps_0F11 =1682,
-  XED_IFORM_MOVZX_GPRv_MEMb =1683, +  XED_IFORM_MOVZX_GPRv_GPR16 =1683,
-  XED_IFORM_MOVZX_GPRv_MEMw =1684, +  XED_IFORM_MOVZX_GPRv_GPR8 =1684,
-  XED_IFORM_MOV_CR_CR_GPR32 =1685, +  XED_IFORM_MOVZX_GPRv_MEMb =1685,
-  XED_IFORM_MOV_CR_CR_GPR64 =1686, +  XED_IFORM_MOVZX_GPRv_MEMw =1686,
-  XED_IFORM_MOV_CR_GPR32_CR =1687, +  XED_IFORM_MOV_CR_CR_GPR32 =1687,
-  XED_IFORM_MOV_CR_GPR64_CR =1688, +  XED_IFORM_MOV_CR_CR_GPR64 =1688,
-  XED_IFORM_MOV_DR_DR_GPR32 =1689, +  XED_IFORM_MOV_CR_GPR32_CR =1689,
-  XED_IFORM_MOV_DR_DR_GPR64 =1690, +  XED_IFORM_MOV_CR_GPR64_CR =1690,
-  XED_IFORM_MOV_DR_GPR32_DR =1691, +  XED_IFORM_MOV_DR_DR_GPR32 =1691,
-  XED_IFORM_MOV_DR_GPR64_DR =1692, +  XED_IFORM_MOV_DR_DR_GPR64 =1692,
-  XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb =1693, +  XED_IFORM_MOV_DR_GPR32_DR =1693,
-  XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb =1694, +  XED_IFORM_MOV_DR_GPR64_DR =1694,
-  XED_IFORM_MUL_GPR8 =1695, +  XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb =1695,
-  XED_IFORM_MUL_GPR8i8_APX =1696, +  XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb =1696,
-  XED_IFORM_MUL_GPRv =1697, +  XED_IFORM_MUL_GPR8 =1697,
-  XED_IFORM_MUL_GPRv_APX =1698, +  XED_IFORM_MUL_GPR8i8_APX =1698,
-  XED_IFORM_MUL_MEMb =1699, +  XED_IFORM_MUL_GPRv =1699,
-  XED_IFORM_MUL_MEMi8_APX =1700, +  XED_IFORM_MUL_GPRv_APX =1700,
-  XED_IFORM_MUL_MEMv =1701, +  XED_IFORM_MUL_MEMb =1701,
-  XED_IFORM_MUL_MEMv_APX =1702, +  XED_IFORM_MUL_MEMi8_APX =1702,
-  XED_IFORM_MULPD_XMMpd_MEMpd =1703, +  XED_IFORM_MUL_MEMv =1703,
-  XED_IFORM_MULPD_XMMpd_XMMpd =1704, +  XED_IFORM_MUL_MEMv_APX =1704,
-  XED_IFORM_MULPS_XMMps_MEMps =1705, +  XED_IFORM_MULPD_XMMpd_MEMpd =1705,
-  XED_IFORM_MULPS_XMMps_XMMps =1706, +  XED_IFORM_MULPD_XMMpd_XMMpd =1706,
-  XED_IFORM_MULSD_XMMsd_MEMsd =1707, +  XED_IFORM_MULPS_XMMps_MEMps =1707,
-  XED_IFORM_MULSD_XMMsd_XMMsd =1708, +  XED_IFORM_MULPS_XMMps_XMMps =1708,
-  XED_IFORM_MULSS_XMMss_MEMss =1709, +  XED_IFORM_MULSD_XMMsd_MEMsd =1709,
-  XED_IFORM_MULSS_XMMss_XMMss =1710, +  XED_IFORM_MULSD_XMMsd_XMMsd =1710,
-  XED_IFORM_MULX_GPR32d_GPR32d_GPR32d =1711, +  XED_IFORM_MULSS_XMMss_MEMss =1711,
-  XED_IFORM_MULX_GPR32d_GPR32d_MEMd =1712, +  XED_IFORM_MULSS_XMMss_XMMss =1712,
-  XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX =1713, +  XED_IFORM_MULX_GPR32d_GPR32d_GPR32d =1713,
-  XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX =1714, +  XED_IFORM_MULX_GPR32d_GPR32d_MEMd =1714,
-  XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX =1715, +  XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX =1715,
-  XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX =1716, +  XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX =1716,
-  XED_IFORM_MULX_GPR64q_GPR64q_GPR64q =1717, +  XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX =1717,
-  XED_IFORM_MULX_GPR64q_GPR64q_MEMq =1718, +  XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX =1718,
-  XED_IFORM_MWAIT =1719, +  XED_IFORM_MULX_GPR64q_GPR64q_GPR64q =1719,
-  XED_IFORM_MWAITX =1720, +  XED_IFORM_MULX_GPR64q_GPR64q_MEMq =1720,
-  XED_IFORM_NEG_GPR8 =1721, +  XED_IFORM_MWAIT =1721,
-  XED_IFORM_NEG_GPR8i8_APX =1722, +  XED_IFORM_MWAITX =1722,
-  XED_IFORM_NEG_GPR8i8_GPR8i8_APX =1723, +  XED_IFORM_NEG_GPR8 =1723,
-  XED_IFORM_NEG_GPR8i8_MEMi8_APX =1724, +  XED_IFORM_NEG_GPR8i8_APX =1724,
-  XED_IFORM_NEG_GPRv =1725, +  XED_IFORM_NEG_GPR8i8_GPR8i8_APX =1725,
-  XED_IFORM_NEG_GPRv_APX =1726, +  XED_IFORM_NEG_GPR8i8_MEMi8_APX =1726,
-  XED_IFORM_NEG_GPRv_GPRv_APX =1727, +  XED_IFORM_NEG_GPRv =1727,
-  XED_IFORM_NEG_GPRv_MEMv_APX =1728, +  XED_IFORM_NEG_GPRv_APX =1728,
-  XED_IFORM_NEG_MEMb =1729, +  XED_IFORM_NEG_GPRv_GPRv_APX =1729,
-  XED_IFORM_NEG_MEMi8_APX =1730, +  XED_IFORM_NEG_GPRv_MEMv_APX =1730,
-  XED_IFORM_NEG_MEMv =1731, +  XED_IFORM_NEG_MEMb =1731,
-  XED_IFORM_NEG_MEMv_APX =1732, +  XED_IFORM_NEG_MEMi8_APX =1732,
-  XED_IFORM_NEG_LOCK_MEMb =1733, +  XED_IFORM_NEG_MEMv =1733,
-  XED_IFORM_NEG_LOCK_MEMv =1734, +  XED_IFORM_NEG_MEMv_APX =1734,
-  XED_IFORM_NOP_90 =1735, +  XED_IFORM_NEG_LOCK_MEMb =1735,
-  XED_IFORM_NOP_GPRv_0F18r0 =1736, +  XED_IFORM_NEG_LOCK_MEMv =1736,
-  XED_IFORM_NOP_GPRv_0F18r1 =1737, +  XED_IFORM_NOP_90 =1737,
-  XED_IFORM_NOP_GPRv_0F18r2 =1738, +  XED_IFORM_NOP_GPRv_0F18r0 =1738,
-  XED_IFORM_NOP_GPRv_0F18r3 =1739, +  XED_IFORM_NOP_GPRv_0F18r1 =1739,
-  XED_IFORM_NOP_GPRv_0F18r4 =1740, +  XED_IFORM_NOP_GPRv_0F18r2 =1740,
-  XED_IFORM_NOP_GPRv_0F18r5 =1741, +  XED_IFORM_NOP_GPRv_0F18r3 =1741,
-  XED_IFORM_NOP_GPRv_0F18r6 =1742, +  XED_IFORM_NOP_GPRv_0F18r4 =1742,
-  XED_IFORM_NOP_GPRv_0F18r7 =1743, +  XED_IFORM_NOP_GPRv_0F18r5 =1743,
-  XED_IFORM_NOP_GPRv_0F1F =1744, +  XED_IFORM_NOP_GPRv_0F18r6 =1744,
-  XED_IFORM_NOP_GPRv_GPRv_0F0D =1745, +  XED_IFORM_NOP_GPRv_0F18r7 =1745,
-  XED_IFORM_NOP_GPRv_GPRv_0F19 =1746, +  XED_IFORM_NOP_GPRv_0F1F =1746,
-  XED_IFORM_NOP_GPRv_GPRv_0F1A =1747, +  XED_IFORM_NOP_GPRv_GPRv_0F0D =1747,
-  XED_IFORM_NOP_GPRv_GPRv_0F1B =1748, +  XED_IFORM_NOP_GPRv_GPRv_0F19 =1748,
-  XED_IFORM_NOP_GPRv_GPRv_0F1C =1749, +  XED_IFORM_NOP_GPRv_GPRv_0F1A =1749,
-  XED_IFORM_NOP_GPRv_GPRv_0F1D =1750, +  XED_IFORM_NOP_GPRv_GPRv_0F1B =1750,
-  XED_IFORM_NOP_GPRv_GPRv_0F1E =1751, +  XED_IFORM_NOP_GPRv_GPRv_0F1C =1751,
-  XED_IFORM_NOP_GPRv_MEM_0F1B =1752, +  XED_IFORM_NOP_GPRv_GPRv_0F1D =1752,
-  XED_IFORM_NOP_GPRv_MEMv_0F1A =1753, +  XED_IFORM_NOP_GPRv_GPRv_0F1E =1753,
-  XED_IFORM_NOP_MEMv_0F18r4 =1754, +  XED_IFORM_NOP_GPRv_MEM_0F1B =1754,
-  XED_IFORM_NOP_MEMv_0F18r5 =1755, +  XED_IFORM_NOP_GPRv_MEMv_0F1A =1755,
-  XED_IFORM_NOP_MEMv_0F1F =1756, +  XED_IFORM_NOP_MEMv_0F18r5 =1756,
-  XED_IFORM_NOP_MEMv_GPRv_0F19 =1757, +  XED_IFORM_NOP_MEMv_0F1F =1757,
-  XED_IFORM_NOP_MEMv_GPRv_0F1C =1758, +  XED_IFORM_NOP_MEMv_GPRv_0F19 =1758,
-  XED_IFORM_NOP_MEMv_GPRv_0F1D =1759, +  XED_IFORM_NOP_MEMv_GPRv_0F1C =1759,
-  XED_IFORM_NOP_MEMv_GPRv_0F1E =1760, +  XED_IFORM_NOP_MEMv_GPRv_0F1D =1760,
-  XED_IFORM_NOT_GPR8 =1761, +  XED_IFORM_NOP_MEMv_GPRv_0F1E =1761,
-  XED_IFORM_NOT_GPR8i8_APX =1762, +  XED_IFORM_NOT_GPR8 =1762,
-  XED_IFORM_NOT_GPR8i8_GPR8i8_APX =1763, +  XED_IFORM_NOT_GPR8i8_APX =1763,
-  XED_IFORM_NOT_GPR8i8_MEMi8_APX =1764, +  XED_IFORM_NOT_GPR8i8_GPR8i8_APX =1764,
-  XED_IFORM_NOT_GPRv =1765, +  XED_IFORM_NOT_GPR8i8_MEMi8_APX =1765,
-  XED_IFORM_NOT_GPRv_APX =1766, +  XED_IFORM_NOT_GPRv =1766,
-  XED_IFORM_NOT_GPRv_GPRv_APX =1767, +  XED_IFORM_NOT_GPRv_APX =1767,
-  XED_IFORM_NOT_GPRv_MEMv_APX =1768, +  XED_IFORM_NOT_GPRv_GPRv_APX =1768,
-  XED_IFORM_NOT_MEMb =1769, +  XED_IFORM_NOT_GPRv_MEMv_APX =1769,
-  XED_IFORM_NOT_MEMi8_APX =1770, +  XED_IFORM_NOT_MEMb =1770,
-  XED_IFORM_NOT_MEMv =1771, +  XED_IFORM_NOT_MEMi8_APX =1771,
-  XED_IFORM_NOT_MEMv_APX =1772, +  XED_IFORM_NOT_MEMv =1772,
-  XED_IFORM_NOT_LOCK_MEMb =1773, +  XED_IFORM_NOT_MEMv_APX =1773,
-  XED_IFORM_NOT_LOCK_MEMv =1774, +  XED_IFORM_NOT_LOCK_MEMb =1774,
-  XED_IFORM_OR_AL_IMMb =1775, +  XED_IFORM_NOT_LOCK_MEMv =1775,
-  XED_IFORM_OR_GPR8_GPR8_08 =1776, +  XED_IFORM_OR_AL_IMMb =1776,
-  XED_IFORM_OR_GPR8_GPR8_0A =1777, +  XED_IFORM_OR_GPR8_GPR8_08 =1777,
-  XED_IFORM_OR_GPR8_IMMb_80r1 =1778, +  XED_IFORM_OR_GPR8_GPR8_0A =1778,
-  XED_IFORM_OR_GPR8_IMMb_82r1 =1779, +  XED_IFORM_OR_GPR8_IMMb_80r1 =1779,
-  XED_IFORM_OR_GPR8_MEMb =1780, +  XED_IFORM_OR_GPR8_IMMb_82r1 =1780,
-  XED_IFORM_OR_GPR8i8_GPR8i8_APX =1781, +  XED_IFORM_OR_GPR8_MEMb =1781,
-  XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX =1782, +  XED_IFORM_OR_GPR8i8_GPR8i8_APX =1782,
-  XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX =1783, +  XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX =1783,
-  XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX =1784, +  XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX =1784,
-  XED_IFORM_OR_GPR8i8_IMM8_APX =1785, +  XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX =1785,
-  XED_IFORM_OR_GPR8i8_MEMi8_APX =1786, +  XED_IFORM_OR_GPR8i8_IMM8_APX =1786,
-  XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX =1787, +  XED_IFORM_OR_GPR8i8_MEMi8_APX =1787,
-  XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX =1788, +  XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX =1788,
-  XED_IFORM_OR_GPRv_GPRv_09 =1789, +  XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX =1789,
-  XED_IFORM_OR_GPRv_GPRv_0B =1790, +  XED_IFORM_OR_GPRv_GPRv_09 =1790,
-  XED_IFORM_OR_GPRv_GPRv_APX =1791, +  XED_IFORM_OR_GPRv_GPRv_0B =1791,
-  XED_IFORM_OR_GPRv_GPRv_GPRv_APX =1792, +  XED_IFORM_OR_GPRv_GPRv_APX =1792,
-  XED_IFORM_OR_GPRv_GPRv_IMM8_APX =1793, +  XED_IFORM_OR_GPRv_GPRv_GPRv_APX =1793,
-  XED_IFORM_OR_GPRv_GPRv_IMMz_APX =1794, +  XED_IFORM_OR_GPRv_GPRv_IMM8_APX =1794,
-  XED_IFORM_OR_GPRv_GPRv_MEMv_APX =1795, +  XED_IFORM_OR_GPRv_GPRv_IMMz_APX =1795,
-  XED_IFORM_OR_GPRv_IMM8_APX =1796, +  XED_IFORM_OR_GPRv_GPRv_MEMv_APX =1796,
-  XED_IFORM_OR_GPRv_IMMb =1797, +  XED_IFORM_OR_GPRv_IMM8_APX =1797,
-  XED_IFORM_OR_GPRv_IMMz =1798, +  XED_IFORM_OR_GPRv_IMMb =1798,
-  XED_IFORM_OR_GPRv_IMMz_APX =1799, +  XED_IFORM_OR_GPRv_IMMz =1799,
-  XED_IFORM_OR_GPRv_MEMv =1800, +  XED_IFORM_OR_GPRv_IMMz_APX =1800,
-  XED_IFORM_OR_GPRv_MEMv_APX =1801, +  XED_IFORM_OR_GPRv_MEMv =1801,
-  XED_IFORM_OR_GPRv_MEMv_GPRv_APX =1802, +  XED_IFORM_OR_GPRv_MEMv_APX =1802,
-  XED_IFORM_OR_GPRv_MEMv_IMM8_APX =1803, +  XED_IFORM_OR_GPRv_MEMv_GPRv_APX =1803,
-  XED_IFORM_OR_GPRv_MEMv_IMMz_APX =1804, +  XED_IFORM_OR_GPRv_MEMv_IMM8_APX =1804,
-  XED_IFORM_OR_MEMb_GPR8 =1805, +  XED_IFORM_OR_GPRv_MEMv_IMMz_APX =1805,
-  XED_IFORM_OR_MEMb_IMMb_80r1 =1806, +  XED_IFORM_OR_MEMb_GPR8 =1806,
-  XED_IFORM_OR_MEMb_IMMb_82r1 =1807, +  XED_IFORM_OR_MEMb_IMMb_80r1 =1807,
-  XED_IFORM_OR_MEMi8_GPR8i8_APX =1808, +  XED_IFORM_OR_MEMb_IMMb_82r1 =1808,
-  XED_IFORM_OR_MEMi8_IMM8_APX =1809, +  XED_IFORM_OR_MEMi8_GPR8i8_APX =1809,
-  XED_IFORM_OR_MEMv_GPRv =1810, +  XED_IFORM_OR_MEMi8_IMM8_APX =1810,
-  XED_IFORM_OR_MEMv_GPRv_APX =1811, +  XED_IFORM_OR_MEMv_GPRv =1811,
-  XED_IFORM_OR_MEMv_IMM8_APX =1812, +  XED_IFORM_OR_MEMv_GPRv_APX =1812,
-  XED_IFORM_OR_MEMv_IMMb =1813, +  XED_IFORM_OR_MEMv_IMM8_APX =1813,
-  XED_IFORM_OR_MEMv_IMMz =1814, +  XED_IFORM_OR_MEMv_IMMb =1814,
-  XED_IFORM_OR_MEMv_IMMz_APX =1815, +  XED_IFORM_OR_MEMv_IMMz =1815,
-  XED_IFORM_OR_OrAX_IMMz =1816, +  XED_IFORM_OR_MEMv_IMMz_APX =1816,
-  XED_IFORM_ORPD_XMMxuq_MEMxuq =1817, +  XED_IFORM_OR_OrAX_IMMz =1817,
-  XED_IFORM_ORPD_XMMxuq_XMMxuq =1818, +  XED_IFORM_ORPD_XMMxuq_MEMxuq =1818,
-  XED_IFORM_ORPS_XMMxud_MEMxud =1819, +  XED_IFORM_ORPD_XMMxuq_XMMxuq =1819,
-  XED_IFORM_ORPS_XMMxud_XMMxud =1820, +  XED_IFORM_ORPS_XMMxud_MEMxud =1820,
-  XED_IFORM_OR_LOCK_MEMb_GPR8 =1821, +  XED_IFORM_ORPS_XMMxud_XMMxud =1821,
-  XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 =1822, +  XED_IFORM_OR_LOCK_MEMb_GPR8 =1822,
-  XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 =1823, +  XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 =1823,
-  XED_IFORM_OR_LOCK_MEMv_GPRv =1824, +  XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 =1824,
-  XED_IFORM_OR_LOCK_MEMv_IMMb =1825, +  XED_IFORM_OR_LOCK_MEMv_GPRv =1825,
-  XED_IFORM_OR_LOCK_MEMv_IMMz =1826, +  XED_IFORM_OR_LOCK_MEMv_IMMb =1826,
-  XED_IFORM_OUT_DX_AL =1827, +  XED_IFORM_OR_LOCK_MEMv_IMMz =1827,
-  XED_IFORM_OUT_DX_OeAX =1828, +  XED_IFORM_OUT_DX_AL =1828,
-  XED_IFORM_OUT_IMMb_AL =1829, +  XED_IFORM_OUT_DX_OeAX =1829,
-  XED_IFORM_OUT_IMMb_OeAX =1830, +  XED_IFORM_OUT_IMMb_AL =1830,
-  XED_IFORM_OUTSB =1831, +  XED_IFORM_OUT_IMMb_OeAX =1831,
-  XED_IFORM_OUTSD =1832, +  XED_IFORM_OUTSB =1832,
-  XED_IFORM_OUTSW =1833, +  XED_IFORM_OUTSD =1833,
-  XED_IFORM_PABSB_MMXq_MEMq =1834, +  XED_IFORM_OUTSW =1834,
-  XED_IFORM_PABSB_MMXq_MMXq =1835, +  XED_IFORM_PABSB_MMXq_MEMq =1835,
-  XED_IFORM_PABSB_XMMdq_MEMdq =1836, +  XED_IFORM_PABSB_MMXq_MMXq =1836,
-  XED_IFORM_PABSB_XMMdq_XMMdq =1837, +  XED_IFORM_PABSB_XMMdq_MEMdq =1837,
-  XED_IFORM_PABSD_MMXq_MEMq =1838, +  XED_IFORM_PABSB_XMMdq_XMMdq =1838,
-  XED_IFORM_PABSD_MMXq_MMXq =1839, +  XED_IFORM_PABSD_MMXq_MEMq =1839,
-  XED_IFORM_PABSD_XMMdq_MEMdq =1840, +  XED_IFORM_PABSD_MMXq_MMXq =1840,
-  XED_IFORM_PABSD_XMMdq_XMMdq =1841, +  XED_IFORM_PABSD_XMMdq_MEMdq =1841,
-  XED_IFORM_PABSW_MMXq_MEMq =1842, +  XED_IFORM_PABSD_XMMdq_XMMdq =1842,
-  XED_IFORM_PABSW_MMXq_MMXq =1843, +  XED_IFORM_PABSW_MMXq_MEMq =1843,
-  XED_IFORM_PABSW_XMMdq_MEMdq =1844, +  XED_IFORM_PABSW_MMXq_MMXq =1844,
-  XED_IFORM_PABSW_XMMdq_XMMdq =1845, +  XED_IFORM_PABSW_XMMdq_MEMdq =1845,
-  XED_IFORM_PACKSSDW_MMXq_MEMq =1846, +  XED_IFORM_PABSW_XMMdq_XMMdq =1846,
-  XED_IFORM_PACKSSDW_MMXq_MMXq =1847, +  XED_IFORM_PACKSSDW_MMXq_MEMq =1847,
-  XED_IFORM_PACKSSDW_XMMdq_MEMdq =1848, +  XED_IFORM_PACKSSDW_MMXq_MMXq =1848,
-  XED_IFORM_PACKSSDW_XMMdq_XMMdq =1849, +  XED_IFORM_PACKSSDW_XMMdq_MEMdq =1849,
-  XED_IFORM_PACKSSWB_MMXq_MEMq =1850, +  XED_IFORM_PACKSSDW_XMMdq_XMMdq =1850,
-  XED_IFORM_PACKSSWB_MMXq_MMXq =1851, +  XED_IFORM_PACKSSWB_MMXq_MEMq =1851,
-  XED_IFORM_PACKSSWB_XMMdq_MEMdq =1852, +  XED_IFORM_PACKSSWB_MMXq_MMXq =1852,
-  XED_IFORM_PACKSSWB_XMMdq_XMMdq =1853, +  XED_IFORM_PACKSSWB_XMMdq_MEMdq =1853,
-  XED_IFORM_PACKUSDW_XMMdq_MEMdq =1854, +  XED_IFORM_PACKSSWB_XMMdq_XMMdq =1854,
-  XED_IFORM_PACKUSDW_XMMdq_XMMdq =1855, +  XED_IFORM_PACKUSDW_XMMdq_MEMdq =1855,
-  XED_IFORM_PACKUSWB_MMXq_MEMq =1856, +  XED_IFORM_PACKUSDW_XMMdq_XMMdq =1856,
-  XED_IFORM_PACKUSWB_MMXq_MMXq =1857, +  XED_IFORM_PACKUSWB_MMXq_MEMq =1857,
-  XED_IFORM_PACKUSWB_XMMdq_MEMdq =1858, +  XED_IFORM_PACKUSWB_MMXq_MMXq =1858,
-  XED_IFORM_PACKUSWB_XMMdq_XMMdq =1859, +  XED_IFORM_PACKUSWB_XMMdq_MEMdq =1859,
-  XED_IFORM_PADDB_MMXq_MEMq =1860, +  XED_IFORM_PACKUSWB_XMMdq_XMMdq =1860,
-  XED_IFORM_PADDB_MMXq_MMXq =1861, +  XED_IFORM_PADDB_MMXq_MEMq =1861,
-  XED_IFORM_PADDB_XMMdq_MEMdq =1862, +  XED_IFORM_PADDB_MMXq_MMXq =1862,
-  XED_IFORM_PADDB_XMMdq_XMMdq =1863, +  XED_IFORM_PADDB_XMMdq_MEMdq =1863,
-  XED_IFORM_PADDD_MMXq_MEMq =1864, +  XED_IFORM_PADDB_XMMdq_XMMdq =1864,
-  XED_IFORM_PADDD_MMXq_MMXq =1865, +  XED_IFORM_PADDD_MMXq_MEMq =1865,
-  XED_IFORM_PADDD_XMMdq_MEMdq =1866, +  XED_IFORM_PADDD_MMXq_MMXq =1866,
-  XED_IFORM_PADDD_XMMdq_XMMdq =1867, +  XED_IFORM_PADDD_XMMdq_MEMdq =1867,
-  XED_IFORM_PADDQ_MMXq_MEMq =1868, +  XED_IFORM_PADDD_XMMdq_XMMdq =1868,
-  XED_IFORM_PADDQ_MMXq_MMXq =1869, +  XED_IFORM_PADDQ_MMXq_MEMq =1869,
-  XED_IFORM_PADDQ_XMMdq_MEMdq =1870, +  XED_IFORM_PADDQ_MMXq_MMXq =1870,
-  XED_IFORM_PADDQ_XMMdq_XMMdq =1871, +  XED_IFORM_PADDQ_XMMdq_MEMdq =1871,
-  XED_IFORM_PADDSB_MMXq_MEMq =1872, +  XED_IFORM_PADDQ_XMMdq_XMMdq =1872,
-  XED_IFORM_PADDSB_MMXq_MMXq =1873, +  XED_IFORM_PADDSB_MMXq_MEMq =1873,
-  XED_IFORM_PADDSB_XMMdq_MEMdq =1874, +  XED_IFORM_PADDSB_MMXq_MMXq =1874,
-  XED_IFORM_PADDSB_XMMdq_XMMdq =1875, +  XED_IFORM_PADDSB_XMMdq_MEMdq =1875,
-  XED_IFORM_PADDSW_MMXq_MEMq =1876, +  XED_IFORM_PADDSB_XMMdq_XMMdq =1876,
-  XED_IFORM_PADDSW_MMXq_MMXq =1877, +  XED_IFORM_PADDSW_MMXq_MEMq =1877,
-  XED_IFORM_PADDSW_XMMdq_MEMdq =1878, +  XED_IFORM_PADDSW_MMXq_MMXq =1878,
-  XED_IFORM_PADDSW_XMMdq_XMMdq =1879, +  XED_IFORM_PADDSW_XMMdq_MEMdq =1879,
-  XED_IFORM_PADDUSB_MMXq_MEMq =1880, +  XED_IFORM_PADDSW_XMMdq_XMMdq =1880,
-  XED_IFORM_PADDUSB_MMXq_MMXq =1881, +  XED_IFORM_PADDUSB_MMXq_MEMq =1881,
-  XED_IFORM_PADDUSB_XMMdq_MEMdq =1882, +  XED_IFORM_PADDUSB_MMXq_MMXq =1882,
-  XED_IFORM_PADDUSB_XMMdq_XMMdq =1883, +  XED_IFORM_PADDUSB_XMMdq_MEMdq =1883,
-  XED_IFORM_PADDUSW_MMXq_MEMq =1884, +  XED_IFORM_PADDUSB_XMMdq_XMMdq =1884,
-  XED_IFORM_PADDUSW_MMXq_MMXq =1885, +  XED_IFORM_PADDUSW_MMXq_MEMq =1885,
-  XED_IFORM_PADDUSW_XMMdq_MEMdq =1886, +  XED_IFORM_PADDUSW_MMXq_MMXq =1886,
-  XED_IFORM_PADDUSW_XMMdq_XMMdq =1887, +  XED_IFORM_PADDUSW_XMMdq_MEMdq =1887,
-  XED_IFORM_PADDW_MMXq_MEMq =1888, +  XED_IFORM_PADDUSW_XMMdq_XMMdq =1888,
-  XED_IFORM_PADDW_MMXq_MMXq =1889, +  XED_IFORM_PADDW_MMXq_MEMq =1889,
-  XED_IFORM_PADDW_XMMdq_MEMdq =1890, +  XED_IFORM_PADDW_MMXq_MMXq =1890,
-  XED_IFORM_PADDW_XMMdq_XMMdq =1891, +  XED_IFORM_PADDW_XMMdq_MEMdq =1891,
-  XED_IFORM_PALIGNR_MMXq_MEMq_IMMb =1892, +  XED_IFORM_PADDW_XMMdq_XMMdq =1892,
-  XED_IFORM_PALIGNR_MMXq_MMXq_IMMb =1893, +  XED_IFORM_PALIGNR_MMXq_MEMq_IMMb =1893,
-  XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb =1894, +  XED_IFORM_PALIGNR_MMXq_MMXq_IMMb =1894,
-  XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb =1895, +  XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb =1895,
-  XED_IFORM_PAND_MMXq_MEMq =1896, +  XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb =1896,
-  XED_IFORM_PAND_MMXq_MMXq =1897, +  XED_IFORM_PAND_MMXq_MEMq =1897,
-  XED_IFORM_PAND_XMMdq_MEMdq =1898, +  XED_IFORM_PAND_MMXq_MMXq =1898,
-  XED_IFORM_PAND_XMMdq_XMMdq =1899, +  XED_IFORM_PAND_XMMdq_MEMdq =1899,
-  XED_IFORM_PANDN_MMXq_MEMq =1900, +  XED_IFORM_PAND_XMMdq_XMMdq =1900,
-  XED_IFORM_PANDN_MMXq_MMXq =1901, +  XED_IFORM_PANDN_MMXq_MEMq =1901,
-  XED_IFORM_PANDN_XMMdq_MEMdq =1902, +  XED_IFORM_PANDN_MMXq_MMXq =1902,
-  XED_IFORM_PANDN_XMMdq_XMMdq =1903, +  XED_IFORM_PANDN_XMMdq_MEMdq =1903,
-  XED_IFORM_PAUSE =1904, +  XED_IFORM_PANDN_XMMdq_XMMdq =1904,
-  XED_IFORM_PAVGB_MMXq_MEMq =1905, +  XED_IFORM_PAUSE =1905,
-  XED_IFORM_PAVGB_MMXq_MMXq =1906, +  XED_IFORM_PAVGB_MMXq_MEMq =1906,
-  XED_IFORM_PAVGB_XMMdq_MEMdq =1907, +  XED_IFORM_PAVGB_MMXq_MMXq =1907,
-  XED_IFORM_PAVGB_XMMdq_XMMdq =1908, +  XED_IFORM_PAVGB_XMMdq_MEMdq =1908,
-  XED_IFORM_PAVGUSB_MMXq_MEMq =1909, +  XED_IFORM_PAVGB_XMMdq_XMMdq =1909,
-  XED_IFORM_PAVGUSB_MMXq_MMXq =1910, +  XED_IFORM_PAVGUSB_MMXq_MEMq =1910,
-  XED_IFORM_PAVGW_MMXq_MEMq =1911, +  XED_IFORM_PAVGUSB_MMXq_MMXq =1911,
-  XED_IFORM_PAVGW_MMXq_MMXq =1912, +  XED_IFORM_PAVGW_MMXq_MEMq =1912,
-  XED_IFORM_PAVGW_XMMdq_MEMdq =1913, +  XED_IFORM_PAVGW_MMXq_MMXq =1913,
-  XED_IFORM_PAVGW_XMMdq_XMMdq =1914, +  XED_IFORM_PAVGW_XMMdq_MEMdq =1914,
-  XED_IFORM_PBLENDVB_XMMdq_MEMdq =1915, +  XED_IFORM_PAVGW_XMMdq_XMMdq =1915,
-  XED_IFORM_PBLENDVB_XMMdq_XMMdq =1916, +  XED_IFORM_PBLENDVB_XMMdq_MEMdq =1916,
-  XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb =1917, +  XED_IFORM_PBLENDVB_XMMdq_XMMdq =1917,
-  XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb =1918, +  XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb =1918,
-  XED_IFORM_PBNDKB =1919, +  XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb =1919,
-  XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb =1920, +  XED_IFORM_PBNDKB =1920,
-  XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb =1921, +  XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb =1921,
-  XED_IFORM_PCMPEQB_MMXq_MEMq =1922, +  XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb =1922,
-  XED_IFORM_PCMPEQB_MMXq_MMXq =1923, +  XED_IFORM_PCMPEQB_MMXq_MEMq =1923,
-  XED_IFORM_PCMPEQB_XMMdq_MEMdq =1924, +  XED_IFORM_PCMPEQB_MMXq_MMXq =1924,
-  XED_IFORM_PCMPEQB_XMMdq_XMMdq =1925, +  XED_IFORM_PCMPEQB_XMMdq_MEMdq =1925,
-  XED_IFORM_PCMPEQD_MMXq_MEMq =1926, +  XED_IFORM_PCMPEQB_XMMdq_XMMdq =1926,
-  XED_IFORM_PCMPEQD_MMXq_MMXq =1927, +  XED_IFORM_PCMPEQD_MMXq_MEMq =1927,
-  XED_IFORM_PCMPEQD_XMMdq_MEMdq =1928, +  XED_IFORM_PCMPEQD_MMXq_MMXq =1928,
-  XED_IFORM_PCMPEQD_XMMdq_XMMdq =1929, +  XED_IFORM_PCMPEQD_XMMdq_MEMdq =1929,
-  XED_IFORM_PCMPEQQ_XMMdq_MEMdq =1930, +  XED_IFORM_PCMPEQD_XMMdq_XMMdq =1930,
-  XED_IFORM_PCMPEQQ_XMMdq_XMMdq =1931, +  XED_IFORM_PCMPEQQ_XMMdq_MEMdq =1931,
-  XED_IFORM_PCMPEQW_MMXq_MEMq =1932, +  XED_IFORM_PCMPEQQ_XMMdq_XMMdq =1932,
-  XED_IFORM_PCMPEQW_MMXq_MMXq =1933, +  XED_IFORM_PCMPEQW_MMXq_MEMq =1933,
-  XED_IFORM_PCMPEQW_XMMdq_MEMdq =1934, +  XED_IFORM_PCMPEQW_MMXq_MMXq =1934,
-  XED_IFORM_PCMPEQW_XMMdq_XMMdq =1935, +  XED_IFORM_PCMPEQW_XMMdq_MEMdq =1935,
-  XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb =1936, +  XED_IFORM_PCMPEQW_XMMdq_XMMdq =1936,
-  XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb =1937, +  XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb =1937,
-  XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb =1938, +  XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb =1938,
-  XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb =1939, +  XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb =1939,
-  XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb =1940, +  XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb =1940,
-  XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb =1941, +  XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb =1941,
-  XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb =1942, +  XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb =1942,
-  XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb =1943, +  XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb =1943,
-  XED_IFORM_PCMPGTB_MMXq_MEMq =1944, +  XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb =1944,
-  XED_IFORM_PCMPGTB_MMXq_MMXq =1945, +  XED_IFORM_PCMPGTB_MMXq_MEMq =1945,
-  XED_IFORM_PCMPGTB_XMMdq_MEMdq =1946, +  XED_IFORM_PCMPGTB_MMXq_MMXq =1946,
-  XED_IFORM_PCMPGTB_XMMdq_XMMdq =1947, +  XED_IFORM_PCMPGTB_XMMdq_MEMdq =1947,
-  XED_IFORM_PCMPGTD_MMXq_MEMq =1948, +  XED_IFORM_PCMPGTB_XMMdq_XMMdq =1948,
-  XED_IFORM_PCMPGTD_MMXq_MMXq =1949, +  XED_IFORM_PCMPGTD_MMXq_MEMq =1949,
-  XED_IFORM_PCMPGTD_XMMdq_MEMdq =1950, +  XED_IFORM_PCMPGTD_MMXq_MMXq =1950,
-  XED_IFORM_PCMPGTD_XMMdq_XMMdq =1951, +  XED_IFORM_PCMPGTD_XMMdq_MEMdq =1951,
-  XED_IFORM_PCMPGTQ_XMMdq_MEMdq =1952, +  XED_IFORM_PCMPGTD_XMMdq_XMMdq =1952,
-  XED_IFORM_PCMPGTQ_XMMdq_XMMdq =1953, +  XED_IFORM_PCMPGTQ_XMMdq_MEMdq =1953,
-  XED_IFORM_PCMPGTW_MMXq_MEMq =1954, +  XED_IFORM_PCMPGTQ_XMMdq_XMMdq =1954,
-  XED_IFORM_PCMPGTW_MMXq_MMXq =1955, +  XED_IFORM_PCMPGTW_MMXq_MEMq =1955,
-  XED_IFORM_PCMPGTW_XMMdq_MEMdq =1956, +  XED_IFORM_PCMPGTW_MMXq_MMXq =1956,
-  XED_IFORM_PCMPGTW_XMMdq_XMMdq =1957, +  XED_IFORM_PCMPGTW_XMMdq_MEMdq =1957,
-  XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb =1958, +  XED_IFORM_PCMPGTW_XMMdq_XMMdq =1958,
-  XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb =1959, +  XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb =1959,
-  XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb =1960, +  XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb =1960,
-  XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb =1961, +  XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb =1961,
-  XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb =1962, +  XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb =1962,
-  XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb =1963, +  XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb =1963,
-  XED_IFORM_PCONFIG =1964, +  XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb =1964,
-  XED_IFORM_PCONFIG64 =1965, +  XED_IFORM_PCONFIG =1965,
-  XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d =1966, +  XED_IFORM_PCONFIG64 =1966,
-  XED_IFORM_PDEP_GPR32d_GPR32d_MEMd =1967, +  XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d =1967,
-  XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX =1968, +  XED_IFORM_PDEP_GPR32d_GPR32d_MEMd =1968,
-  XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX =1969, +  XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX =1969,
-  XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX =1970, +  XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX =1970,
-  XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX =1971, +  XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX =1971,
-  XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q =1972, +  XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX =1972,
-  XED_IFORM_PDEP_GPR64q_GPR64q_MEMq =1973, +  XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q =1973,
-  XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d =1974, +  XED_IFORM_PDEP_GPR64q_GPR64q_MEMq =1974,
-  XED_IFORM_PEXT_GPR32d_GPR32d_MEMd =1975, +  XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d =1975,
-  XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX =1976, +  XED_IFORM_PEXT_GPR32d_GPR32d_MEMd =1976,
-  XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX =1977, +  XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX =1977,
-  XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX =1978, +  XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX =1978,
-  XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX =1979, +  XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX =1979,
-  XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q =1980, +  XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX =1980,
-  XED_IFORM_PEXT_GPR64q_GPR64q_MEMq =1981, +  XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q =1981,
-  XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb =1982, +  XED_IFORM_PEXT_GPR64q_GPR64q_MEMq =1982,
-  XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb =1983, +  XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb =1983,
-  XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb =1984, +  XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb =1984,
-  XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb =1985, +  XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb =1985,
-  XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb =1986, +  XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb =1986,
-  XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb =1987, +  XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb =1987,
-  XED_IFORM_PEXTRW_GPR32_MMXq_IMMb =1988, +  XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb =1988,
-  XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb =1989, +  XED_IFORM_PEXTRW_GPR32_MMXq_IMMb =1989,
-  XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb =1990, +  XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb =1990,
-  XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb =1991, +  XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb =1991,
-  XED_IFORM_PF2ID_MMXq_MEMq =1992, +  XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb =1992,
-  XED_IFORM_PF2ID_MMXq_MMXq =1993, +  XED_IFORM_PF2ID_MMXq_MEMq =1993,
-  XED_IFORM_PF2IW_MMXq_MEMq =1994, +  XED_IFORM_PF2ID_MMXq_MMXq =1994,
-  XED_IFORM_PF2IW_MMXq_MMXq =1995, +  XED_IFORM_PF2IW_MMXq_MEMq =1995,
-  XED_IFORM_PFACC_MMXq_MEMq =1996, +  XED_IFORM_PF2IW_MMXq_MMXq =1996,
-  XED_IFORM_PFACC_MMXq_MMXq =1997, +  XED_IFORM_PFACC_MMXq_MEMq =1997,
-  XED_IFORM_PFADD_MMXq_MEMq =1998, +  XED_IFORM_PFACC_MMXq_MMXq =1998,
-  XED_IFORM_PFADD_MMXq_MMXq =1999, +  XED_IFORM_PFADD_MMXq_MEMq =1999,
-  XED_IFORM_PFCMPEQ_MMXq_MEMq =2000, +  XED_IFORM_PFADD_MMXq_MMXq =2000,
-  XED_IFORM_PFCMPEQ_MMXq_MMXq =2001, +  XED_IFORM_PFCMPEQ_MMXq_MEMq =2001,
-  XED_IFORM_PFCMPGE_MMXq_MEMq =2002, +  XED_IFORM_PFCMPEQ_MMXq_MMXq =2002,
-  XED_IFORM_PFCMPGE_MMXq_MMXq =2003, +  XED_IFORM_PFCMPGE_MMXq_MEMq =2003,
-  XED_IFORM_PFCMPGT_MMXq_MEMq =2004, +  XED_IFORM_PFCMPGE_MMXq_MMXq =2004,
-  XED_IFORM_PFCMPGT_MMXq_MMXq =2005, +  XED_IFORM_PFCMPGT_MMXq_MEMq =2005,
-  XED_IFORM_PFMAX_MMXq_MEMq =2006, +  XED_IFORM_PFCMPGT_MMXq_MMXq =2006,
-  XED_IFORM_PFMAX_MMXq_MMXq =2007, +  XED_IFORM_PFMAX_MMXq_MEMq =2007,
-  XED_IFORM_PFMIN_MMXq_MEMq =2008, +  XED_IFORM_PFMAX_MMXq_MMXq =2008,
-  XED_IFORM_PFMIN_MMXq_MMXq =2009, +  XED_IFORM_PFMIN_MMXq_MEMq =2009,
-  XED_IFORM_PFMUL_MMXq_MEMq =2010, +  XED_IFORM_PFMIN_MMXq_MMXq =2010,
-  XED_IFORM_PFMUL_MMXq_MMXq =2011, +  XED_IFORM_PFMUL_MMXq_MEMq =2011,
-  XED_IFORM_PFNACC_MMXq_MEMq =2012, +  XED_IFORM_PFMUL_MMXq_MMXq =2012,
-  XED_IFORM_PFNACC_MMXq_MMXq =2013, +  XED_IFORM_PFNACC_MMXq_MEMq =2013,
-  XED_IFORM_PFPNACC_MMXq_MEMq =2014, +  XED_IFORM_PFNACC_MMXq_MMXq =2014,
-  XED_IFORM_PFPNACC_MMXq_MMXq =2015, +  XED_IFORM_PFPNACC_MMXq_MEMq =2015,
-  XED_IFORM_PFRCP_MMXq_MEMq =2016, +  XED_IFORM_PFPNACC_MMXq_MMXq =2016,
-  XED_IFORM_PFRCP_MMXq_MMXq =2017, +  XED_IFORM_PFRCP_MMXq_MEMq =2017,
-  XED_IFORM_PFRCPIT1_MMXq_MEMq =2018, +  XED_IFORM_PFRCP_MMXq_MMXq =2018,
-  XED_IFORM_PFRCPIT1_MMXq_MMXq =2019, +  XED_IFORM_PFRCPIT1_MMXq_MEMq =2019,
-  XED_IFORM_PFRCPIT2_MMXq_MEMq =2020, +  XED_IFORM_PFRCPIT1_MMXq_MMXq =2020,
-  XED_IFORM_PFRCPIT2_MMXq_MMXq =2021, +  XED_IFORM_PFRCPIT2_MMXq_MEMq =2021,
-  XED_IFORM_PFRSQIT1_MMXq_MEMq =2022, +  XED_IFORM_PFRCPIT2_MMXq_MMXq =2022,
-  XED_IFORM_PFRSQIT1_MMXq_MMXq =2023, +  XED_IFORM_PFRSQIT1_MMXq_MEMq =2023,
-  XED_IFORM_PFRSQRT_MMXq_MEMq =2024, +  XED_IFORM_PFRSQIT1_MMXq_MMXq =2024,
-  XED_IFORM_PFRSQRT_MMXq_MMXq =2025, +  XED_IFORM_PFRSQRT_MMXq_MEMq =2025,
-  XED_IFORM_PFSUB_MMXq_MEMq =2026, +  XED_IFORM_PFRSQRT_MMXq_MMXq =2026,
-  XED_IFORM_PFSUB_MMXq_MMXq =2027, +  XED_IFORM_PFSUB_MMXq_MEMq =2027,
-  XED_IFORM_PFSUBR_MMXq_MEMq =2028, +  XED_IFORM_PFSUB_MMXq_MMXq =2028,
-  XED_IFORM_PFSUBR_MMXq_MMXq =2029, +  XED_IFORM_PFSUBR_MMXq_MEMq =2029,
-  XED_IFORM_PHADDD_MMXq_MEMq =2030, +  XED_IFORM_PFSUBR_MMXq_MMXq =2030,
-  XED_IFORM_PHADDD_MMXq_MMXq =2031, +  XED_IFORM_PHADDD_MMXq_MEMq =2031,
-  XED_IFORM_PHADDD_XMMdq_MEMdq =2032, +  XED_IFORM_PHADDD_MMXq_MMXq =2032,
-  XED_IFORM_PHADDD_XMMdq_XMMdq =2033, +  XED_IFORM_PHADDD_XMMdq_MEMdq =2033,
-  XED_IFORM_PHADDSW_MMXq_MEMq =2034, +  XED_IFORM_PHADDD_XMMdq_XMMdq =2034,
-  XED_IFORM_PHADDSW_MMXq_MMXq =2035, +  XED_IFORM_PHADDSW_MMXq_MEMq =2035,
-  XED_IFORM_PHADDSW_XMMdq_MEMdq =2036, +  XED_IFORM_PHADDSW_MMXq_MMXq =2036,
-  XED_IFORM_PHADDSW_XMMdq_XMMdq =2037, +  XED_IFORM_PHADDSW_XMMdq_MEMdq =2037,
-  XED_IFORM_PHADDW_MMXq_MEMq =2038, +  XED_IFORM_PHADDSW_XMMdq_XMMdq =2038,
-  XED_IFORM_PHADDW_MMXq_MMXq =2039, +  XED_IFORM_PHADDW_MMXq_MEMq =2039,
-  XED_IFORM_PHADDW_XMMdq_MEMdq =2040, +  XED_IFORM_PHADDW_MMXq_MMXq =2040,
-  XED_IFORM_PHADDW_XMMdq_XMMdq =2041, +  XED_IFORM_PHADDW_XMMdq_MEMdq =2041,
-  XED_IFORM_PHMINPOSUW_XMMdq_MEMdq =2042, +  XED_IFORM_PHADDW_XMMdq_XMMdq =2042,
-  XED_IFORM_PHMINPOSUW_XMMdq_XMMdq =2043, +  XED_IFORM_PHMINPOSUW_XMMdq_MEMdq =2043,
-  XED_IFORM_PHSUBD_MMXq_MEMq =2044, +  XED_IFORM_PHMINPOSUW_XMMdq_XMMdq =2044,
-  XED_IFORM_PHSUBD_MMXq_MMXq =2045, +  XED_IFORM_PHSUBD_MMXq_MEMq =2045,
-  XED_IFORM_PHSUBD_XMMdq_MEMdq =2046, +  XED_IFORM_PHSUBD_MMXq_MMXq =2046,
-  XED_IFORM_PHSUBD_XMMdq_XMMdq =2047, +  XED_IFORM_PHSUBD_XMMdq_MEMdq =2047,
-  XED_IFORM_PHSUBSW_MMXq_MEMq =2048, +  XED_IFORM_PHSUBD_XMMdq_XMMdq =2048,
-  XED_IFORM_PHSUBSW_MMXq_MMXq =2049, +  XED_IFORM_PHSUBSW_MMXq_MEMq =2049,
-  XED_IFORM_PHSUBSW_XMMdq_MEMdq =2050, +  XED_IFORM_PHSUBSW_MMXq_MMXq =2050,
-  XED_IFORM_PHSUBSW_XMMdq_XMMdq =2051, +  XED_IFORM_PHSUBSW_XMMdq_MEMdq =2051,
-  XED_IFORM_PHSUBW_MMXq_MEMq =2052, +  XED_IFORM_PHSUBSW_XMMdq_XMMdq =2052,
-  XED_IFORM_PHSUBW_MMXq_MMXq =2053, +  XED_IFORM_PHSUBW_MMXq_MEMq =2053,
-  XED_IFORM_PHSUBW_XMMdq_MEMdq =2054, +  XED_IFORM_PHSUBW_MMXq_MMXq =2054,
-  XED_IFORM_PHSUBW_XMMdq_XMMdq =2055, +  XED_IFORM_PHSUBW_XMMdq_MEMdq =2055,
-  XED_IFORM_PI2FD_MMXq_MEMq =2056, +  XED_IFORM_PHSUBW_XMMdq_XMMdq =2056,
-  XED_IFORM_PI2FD_MMXq_MMXq =2057, +  XED_IFORM_PI2FD_MMXq_MEMq =2057,
-  XED_IFORM_PI2FW_MMXq_MEMq =2058, +  XED_IFORM_PI2FD_MMXq_MMXq =2058,
-  XED_IFORM_PI2FW_MMXq_MMXq =2059, +  XED_IFORM_PI2FW_MMXq_MEMq =2059,
-  XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb =2060, +  XED_IFORM_PI2FW_MMXq_MMXq =2060,
-  XED_IFORM_PINSRB_XMMdq_MEMb_IMMb =2061, +  XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb =2061,
-  XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb =2062, +  XED_IFORM_PINSRB_XMMdq_MEMb_IMMb =2062,
-  XED_IFORM_PINSRD_XMMdq_MEMd_IMMb =2063, +  XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb =2063,
-  XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb =2064, +  XED_IFORM_PINSRD_XMMdq_MEMd_IMMb =2064,
-  XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb =2065, +  XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb =2065,
-  XED_IFORM_PINSRW_MMXq_GPR32_IMMb =2066, +  XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb =2066,
-  XED_IFORM_PINSRW_MMXq_MEMw_IMMb =2067, +  XED_IFORM_PINSRW_MMXq_GPR32_IMMb =2067,
-  XED_IFORM_PINSRW_XMMdq_GPR32_IMMb =2068, +  XED_IFORM_PINSRW_MMXq_MEMw_IMMb =2068,
-  XED_IFORM_PINSRW_XMMdq_MEMw_IMMb =2069, +  XED_IFORM_PINSRW_XMMdq_GPR32_IMMb =2069,
-  XED_IFORM_PMADDUBSW_MMXq_MEMq =2070, +  XED_IFORM_PINSRW_XMMdq_MEMw_IMMb =2070,
-  XED_IFORM_PMADDUBSW_MMXq_MMXq =2071, +  XED_IFORM_PMADDUBSW_MMXq_MEMq =2071,
-  XED_IFORM_PMADDUBSW_XMMdq_MEMdq =2072, +  XED_IFORM_PMADDUBSW_MMXq_MMXq =2072,
-  XED_IFORM_PMADDUBSW_XMMdq_XMMdq =2073, +  XED_IFORM_PMADDUBSW_XMMdq_MEMdq =2073,
-  XED_IFORM_PMADDWD_MMXq_MEMq =2074, +  XED_IFORM_PMADDUBSW_XMMdq_XMMdq =2074,
-  XED_IFORM_PMADDWD_MMXq_MMXq =2075, +  XED_IFORM_PMADDWD_MMXq_MEMq =2075,
-  XED_IFORM_PMADDWD_XMMdq_MEMdq =2076, +  XED_IFORM_PMADDWD_MMXq_MMXq =2076,
-  XED_IFORM_PMADDWD_XMMdq_XMMdq =2077, +  XED_IFORM_PMADDWD_XMMdq_MEMdq =2077,
-  XED_IFORM_PMAXSB_XMMdq_MEMdq =2078, +  XED_IFORM_PMADDWD_XMMdq_XMMdq =2078,
-  XED_IFORM_PMAXSB_XMMdq_XMMdq =2079, +  XED_IFORM_PMAXSB_XMMdq_MEMdq =2079,
-  XED_IFORM_PMAXSD_XMMdq_MEMdq =2080, +  XED_IFORM_PMAXSB_XMMdq_XMMdq =2080,
-  XED_IFORM_PMAXSD_XMMdq_XMMdq =2081, +  XED_IFORM_PMAXSD_XMMdq_MEMdq =2081,
-  XED_IFORM_PMAXSW_MMXq_MEMq =2082, +  XED_IFORM_PMAXSD_XMMdq_XMMdq =2082,
-  XED_IFORM_PMAXSW_MMXq_MMXq =2083, +  XED_IFORM_PMAXSW_MMXq_MEMq =2083,
-  XED_IFORM_PMAXSW_XMMdq_MEMdq =2084, +  XED_IFORM_PMAXSW_MMXq_MMXq =2084,
-  XED_IFORM_PMAXSW_XMMdq_XMMdq =2085, +  XED_IFORM_PMAXSW_XMMdq_MEMdq =2085,
-  XED_IFORM_PMAXUB_MMXq_MEMq =2086, +  XED_IFORM_PMAXSW_XMMdq_XMMdq =2086,
-  XED_IFORM_PMAXUB_MMXq_MMXq =2087, +  XED_IFORM_PMAXUB_MMXq_MEMq =2087,
-  XED_IFORM_PMAXUB_XMMdq_MEMdq =2088, +  XED_IFORM_PMAXUB_MMXq_MMXq =2088,
-  XED_IFORM_PMAXUB_XMMdq_XMMdq =2089, +  XED_IFORM_PMAXUB_XMMdq_MEMdq =2089,
-  XED_IFORM_PMAXUD_XMMdq_MEMdq =2090, +  XED_IFORM_PMAXUB_XMMdq_XMMdq =2090,
-  XED_IFORM_PMAXUD_XMMdq_XMMdq =2091, +  XED_IFORM_PMAXUD_XMMdq_MEMdq =2091,
-  XED_IFORM_PMAXUW_XMMdq_MEMdq =2092, +  XED_IFORM_PMAXUD_XMMdq_XMMdq =2092,
-  XED_IFORM_PMAXUW_XMMdq_XMMdq =2093, +  XED_IFORM_PMAXUW_XMMdq_MEMdq =2093,
-  XED_IFORM_PMINSB_XMMdq_MEMdq =2094, +  XED_IFORM_PMAXUW_XMMdq_XMMdq =2094,
-  XED_IFORM_PMINSB_XMMdq_XMMdq =2095, +  XED_IFORM_PMINSB_XMMdq_MEMdq =2095,
-  XED_IFORM_PMINSD_XMMdq_MEMdq =2096, +  XED_IFORM_PMINSB_XMMdq_XMMdq =2096,
-  XED_IFORM_PMINSD_XMMdq_XMMdq =2097, +  XED_IFORM_PMINSD_XMMdq_MEMdq =2097,
-  XED_IFORM_PMINSW_MMXq_MEMq =2098, +  XED_IFORM_PMINSD_XMMdq_XMMdq =2098,
-  XED_IFORM_PMINSW_MMXq_MMXq =2099, +  XED_IFORM_PMINSW_MMXq_MEMq =2099,
-  XED_IFORM_PMINSW_XMMdq_MEMdq =2100, +  XED_IFORM_PMINSW_MMXq_MMXq =2100,
-  XED_IFORM_PMINSW_XMMdq_XMMdq =2101, +  XED_IFORM_PMINSW_XMMdq_MEMdq =2101,
-  XED_IFORM_PMINUB_MMXq_MEMq =2102, +  XED_IFORM_PMINSW_XMMdq_XMMdq =2102,
-  XED_IFORM_PMINUB_MMXq_MMXq =2103, +  XED_IFORM_PMINUB_MMXq_MEMq =2103,
-  XED_IFORM_PMINUB_XMMdq_MEMdq =2104, +  XED_IFORM_PMINUB_MMXq_MMXq =2104,
-  XED_IFORM_PMINUB_XMMdq_XMMdq =2105, +  XED_IFORM_PMINUB_XMMdq_MEMdq =2105,
-  XED_IFORM_PMINUD_XMMdq_MEMdq =2106, +  XED_IFORM_PMINUB_XMMdq_XMMdq =2106,
-  XED_IFORM_PMINUD_XMMdq_XMMdq =2107, +  XED_IFORM_PMINUD_XMMdq_MEMdq =2107,
-  XED_IFORM_PMINUW_XMMdq_MEMdq =2108, +  XED_IFORM_PMINUD_XMMdq_XMMdq =2108,
-  XED_IFORM_PMINUW_XMMdq_XMMdq =2109, +  XED_IFORM_PMINUW_XMMdq_MEMdq =2109,
-  XED_IFORM_PMOVMSKB_GPR32_MMXq =2110, +  XED_IFORM_PMINUW_XMMdq_XMMdq =2110,
-  XED_IFORM_PMOVMSKB_GPR32_XMMdq =2111, +  XED_IFORM_PMOVMSKB_GPR32_MMXq =2111,
-  XED_IFORM_PMOVSXBD_XMMdq_MEMd =2112, +  XED_IFORM_PMOVMSKB_GPR32_XMMdq =2112,
-  XED_IFORM_PMOVSXBD_XMMdq_XMMd =2113, +  XED_IFORM_PMOVSXBD_XMMdq_MEMd =2113,
-  XED_IFORM_PMOVSXBQ_XMMdq_MEMw =2114, +  XED_IFORM_PMOVSXBD_XMMdq_XMMd =2114,
-  XED_IFORM_PMOVSXBQ_XMMdq_XMMw =2115, +  XED_IFORM_PMOVSXBQ_XMMdq_MEMw =2115,
-  XED_IFORM_PMOVSXBW_XMMdq_MEMq =2116, +  XED_IFORM_PMOVSXBQ_XMMdq_XMMw =2116,
-  XED_IFORM_PMOVSXBW_XMMdq_XMMq =2117, +  XED_IFORM_PMOVSXBW_XMMdq_MEMq =2117,
-  XED_IFORM_PMOVSXDQ_XMMdq_MEMq =2118, +  XED_IFORM_PMOVSXBW_XMMdq_XMMq =2118,
-  XED_IFORM_PMOVSXDQ_XMMdq_XMMq =2119, +  XED_IFORM_PMOVSXDQ_XMMdq_MEMq =2119,
-  XED_IFORM_PMOVSXWD_XMMdq_MEMq =2120, +  XED_IFORM_PMOVSXDQ_XMMdq_XMMq =2120,
-  XED_IFORM_PMOVSXWD_XMMdq_XMMq =2121, +  XED_IFORM_PMOVSXWD_XMMdq_MEMq =2121,
-  XED_IFORM_PMOVSXWQ_XMMdq_MEMd =2122, +  XED_IFORM_PMOVSXWD_XMMdq_XMMq =2122,
-  XED_IFORM_PMOVSXWQ_XMMdq_XMMd =2123, +  XED_IFORM_PMOVSXWQ_XMMdq_MEMd =2123,
-  XED_IFORM_PMOVZXBD_XMMdq_MEMd =2124, +  XED_IFORM_PMOVSXWQ_XMMdq_XMMd =2124,
-  XED_IFORM_PMOVZXBD_XMMdq_XMMd =2125, +  XED_IFORM_PMOVZXBD_XMMdq_MEMd =2125,
-  XED_IFORM_PMOVZXBQ_XMMdq_MEMw =2126, +  XED_IFORM_PMOVZXBD_XMMdq_XMMd =2126,
-  XED_IFORM_PMOVZXBQ_XMMdq_XMMw =2127, +  XED_IFORM_PMOVZXBQ_XMMdq_MEMw =2127,
-  XED_IFORM_PMOVZXBW_XMMdq_MEMq =2128, +  XED_IFORM_PMOVZXBQ_XMMdq_XMMw =2128,
-  XED_IFORM_PMOVZXBW_XMMdq_XMMq =2129, +  XED_IFORM_PMOVZXBW_XMMdq_MEMq =2129,
-  XED_IFORM_PMOVZXDQ_XMMdq_MEMq =2130, +  XED_IFORM_PMOVZXBW_XMMdq_XMMq =2130,
-  XED_IFORM_PMOVZXDQ_XMMdq_XMMq =2131, +  XED_IFORM_PMOVZXDQ_XMMdq_MEMq =2131,
-  XED_IFORM_PMOVZXWD_XMMdq_MEMq =2132, +  XED_IFORM_PMOVZXDQ_XMMdq_XMMq =2132,
-  XED_IFORM_PMOVZXWD_XMMdq_XMMq =2133, +  XED_IFORM_PMOVZXWD_XMMdq_MEMq =2133,
-  XED_IFORM_PMOVZXWQ_XMMdq_MEMd =2134, +  XED_IFORM_PMOVZXWD_XMMdq_XMMq =2134,
-  XED_IFORM_PMOVZXWQ_XMMdq_XMMd =2135, +  XED_IFORM_PMOVZXWQ_XMMdq_MEMd =2135,
-  XED_IFORM_PMULDQ_XMMdq_MEMdq =2136, +  XED_IFORM_PMOVZXWQ_XMMdq_XMMd =2136,
-  XED_IFORM_PMULDQ_XMMdq_XMMdq =2137, +  XED_IFORM_PMULDQ_XMMdq_MEMdq =2137,
-  XED_IFORM_PMULHRSW_MMXq_MEMq =2138, +  XED_IFORM_PMULDQ_XMMdq_XMMdq =2138,
-  XED_IFORM_PMULHRSW_MMXq_MMXq =2139, +  XED_IFORM_PMULHRSW_MMXq_MEMq =2139,
-  XED_IFORM_PMULHRSW_XMMdq_MEMdq =2140, +  XED_IFORM_PMULHRSW_MMXq_MMXq =2140,
-  XED_IFORM_PMULHRSW_XMMdq_XMMdq =2141, +  XED_IFORM_PMULHRSW_XMMdq_MEMdq =2141,
-  XED_IFORM_PMULHRW_MMXq_MEMq =2142, +  XED_IFORM_PMULHRSW_XMMdq_XMMdq =2142,
-  XED_IFORM_PMULHRW_MMXq_MMXq =2143, +  XED_IFORM_PMULHRW_MMXq_MEMq =2143,
-  XED_IFORM_PMULHUW_MMXq_MEMq =2144, +  XED_IFORM_PMULHRW_MMXq_MMXq =2144,
-  XED_IFORM_PMULHUW_MMXq_MMXq =2145, +  XED_IFORM_PMULHUW_MMXq_MEMq =2145,
-  XED_IFORM_PMULHUW_XMMdq_MEMdq =2146, +  XED_IFORM_PMULHUW_MMXq_MMXq =2146,
-  XED_IFORM_PMULHUW_XMMdq_XMMdq =2147, +  XED_IFORM_PMULHUW_XMMdq_MEMdq =2147,
-  XED_IFORM_PMULHW_MMXq_MEMq =2148, +  XED_IFORM_PMULHUW_XMMdq_XMMdq =2148,
-  XED_IFORM_PMULHW_MMXq_MMXq =2149, +  XED_IFORM_PMULHW_MMXq_MEMq =2149,
-  XED_IFORM_PMULHW_XMMdq_MEMdq =2150, +  XED_IFORM_PMULHW_MMXq_MMXq =2150,
-  XED_IFORM_PMULHW_XMMdq_XMMdq =2151, +  XED_IFORM_PMULHW_XMMdq_MEMdq =2151,
-  XED_IFORM_PMULLD_XMMdq_MEMdq =2152, +  XED_IFORM_PMULHW_XMMdq_XMMdq =2152,
-  XED_IFORM_PMULLD_XMMdq_XMMdq =2153, +  XED_IFORM_PMULLD_XMMdq_MEMdq =2153,
-  XED_IFORM_PMULLW_MMXq_MEMq =2154, +  XED_IFORM_PMULLD_XMMdq_XMMdq =2154,
-  XED_IFORM_PMULLW_MMXq_MMXq =2155, +  XED_IFORM_PMULLW_MMXq_MEMq =2155,
-  XED_IFORM_PMULLW_XMMdq_MEMdq =2156, +  XED_IFORM_PMULLW_MMXq_MMXq =2156,
-  XED_IFORM_PMULLW_XMMdq_XMMdq =2157, +  XED_IFORM_PMULLW_XMMdq_MEMdq =2157,
-  XED_IFORM_PMULUDQ_MMXq_MEMq =2158, +  XED_IFORM_PMULLW_XMMdq_XMMdq =2158,
-  XED_IFORM_PMULUDQ_MMXq_MMXq =2159, +  XED_IFORM_PMULUDQ_MMXq_MEMq =2159,
-  XED_IFORM_PMULUDQ_XMMdq_MEMdq =2160, +  XED_IFORM_PMULUDQ_MMXq_MMXq =2160,
-  XED_IFORM_PMULUDQ_XMMdq_XMMdq =2161, +  XED_IFORM_PMULUDQ_XMMdq_MEMdq =2161,
-  XED_IFORM_POP_DS =2162, +  XED_IFORM_PMULUDQ_XMMdq_XMMdq =2162,
-  XED_IFORM_POP_ES =2163, +  XED_IFORM_POP_DS =2163,
-  XED_IFORM_POP_FS =2164, +  XED_IFORM_POP_ES =2164,
-  XED_IFORM_POP_GPRv_58 =2165, +  XED_IFORM_POP_FS =2165,
-  XED_IFORM_POP_GPRv_8F =2166, +  XED_IFORM_POP_GPRv_58 =2166,
-  XED_IFORM_POP_GS =2167, +  XED_IFORM_POP_GPRv_8F =2167,
-  XED_IFORM_POP_MEMv =2168, +  XED_IFORM_POP_GS =2168,
-  XED_IFORM_POP_SS =2169, +  XED_IFORM_POP_MEMv =2169,
-  XED_IFORM_POP2_GPR64u64_GPR64u64_APX =2170, +  XED_IFORM_POP_SS =2170,
-  XED_IFORM_POP2P_GPR64u64_GPR64u64_APX =2171, +  XED_IFORM_POP2_GPR64u64_GPR64u64_APX =2171,
-  XED_IFORM_POPA =2172, +  XED_IFORM_POP2P_GPR64u64_GPR64u64_APX =2172,
-  XED_IFORM_POPAD =2173, +  XED_IFORM_POPA =2173,
-  XED_IFORM_POPCNT_GPRv_GPRv =2174, +  XED_IFORM_POPAD =2174,
-  XED_IFORM_POPCNT_GPRv_GPRv_APX =2175, +  XED_IFORM_POPCNT_GPRv_GPRv =2175,
-  XED_IFORM_POPCNT_GPRv_MEMv =2176, +  XED_IFORM_POPCNT_GPRv_GPRv_APX =2176,
-  XED_IFORM_POPCNT_GPRv_MEMv_APX =2177, +  XED_IFORM_POPCNT_GPRv_MEMv =2177,
-  XED_IFORM_POPF =2178, +  XED_IFORM_POPCNT_GPRv_MEMv_APX =2178,
-  XED_IFORM_POPFD =2179, +  XED_IFORM_POPF =2179,
-  XED_IFORM_POPFQ =2180, +  XED_IFORM_POPFD =2180,
-  XED_IFORM_POPP_GPR64 =2181, +  XED_IFORM_POPFQ =2181,
-  XED_IFORM_POR_MMXq_MEMq =2182, +  XED_IFORM_POPP_GPR64 =2182,
-  XED_IFORM_POR_MMXq_MMXq =2183, +  XED_IFORM_POR_MMXq_MEMq =2183,
-  XED_IFORM_POR_XMMdq_MEMdq =2184, +  XED_IFORM_POR_MMXq_MMXq =2184,
-  XED_IFORM_POR_XMMdq_XMMdq =2185, +  XED_IFORM_POR_XMMdq_MEMdq =2185,
-  XED_IFORM_PREFETCHIT0_MEMu8 =2186, +  XED_IFORM_POR_XMMdq_XMMdq =2186,
-  XED_IFORM_PREFETCHIT1_MEMu8 =2187, +  XED_IFORM_PREFETCHIT0_MEMu8 =2187,
-  XED_IFORM_PREFETCHNTA_MEMmprefetch =2188, +  XED_IFORM_PREFETCHIT1_MEMu8 =2188,
-  XED_IFORM_PREFETCHT0_MEMmprefetch =2189, +  XED_IFORM_PREFETCHNTA_MEMmprefetch =2189,
-  XED_IFORM_PREFETCHT1_MEMmprefetch =2190, +  XED_IFORM_PREFETCHRST2_MEMu8 =2190,
-  XED_IFORM_PREFETCHT2_MEMmprefetch =2191, +  XED_IFORM_PREFETCHT0_MEMmprefetch =2191,
-  XED_IFORM_PREFETCHW_0F0Dr1 =2192, +  XED_IFORM_PREFETCHT1_MEMmprefetch =2192,
-  XED_IFORM_PREFETCHW_0F0Dr3 =2193, +  XED_IFORM_PREFETCHT2_MEMmprefetch =2193,
-  XED_IFORM_PREFETCHWT1_MEMu8 =2194, +  XED_IFORM_PREFETCHW_0F0Dr1 =2194,
-  XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch =2195, +  XED_IFORM_PREFETCHW_0F0Dr3 =2195,
-  XED_IFORM_PREFETCH_RESERVED_0F0Dr4 =2196, +  XED_IFORM_PREFETCHWT1_MEMu8 =2196,
-  XED_IFORM_PREFETCH_RESERVED_0F0Dr5 =2197, +  XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch =2197,
-  XED_IFORM_PREFETCH_RESERVED_0F0Dr6 =2198, +  XED_IFORM_PREFETCH_RESERVED_0F0Dr4 =2198,
-  XED_IFORM_PREFETCH_RESERVED_0F0Dr7 =2199, +  XED_IFORM_PREFETCH_RESERVED_0F0Dr5 =2199,
-  XED_IFORM_PSADBW_MMXq_MEMq =2200, +  XED_IFORM_PREFETCH_RESERVED_0F0Dr6 =2200,
-  XED_IFORM_PSADBW_MMXq_MMXq =2201, +  XED_IFORM_PREFETCH_RESERVED_0F0Dr7 =2201,
-  XED_IFORM_PSADBW_XMMdq_MEMdq =2202, +  XED_IFORM_PSADBW_MMXq_MEMq =2202,
-  XED_IFORM_PSADBW_XMMdq_XMMdq =2203, +  XED_IFORM_PSADBW_MMXq_MMXq =2203,
-  XED_IFORM_PSHUFB_MMXq_MEMq =2204, +  XED_IFORM_PSADBW_XMMdq_MEMdq =2204,
-  XED_IFORM_PSHUFB_MMXq_MMXq =2205, +  XED_IFORM_PSADBW_XMMdq_XMMdq =2205,
-  XED_IFORM_PSHUFB_XMMdq_MEMdq =2206, +  XED_IFORM_PSHUFB_MMXq_MEMq =2206,
-  XED_IFORM_PSHUFB_XMMdq_XMMdq =2207, +  XED_IFORM_PSHUFB_MMXq_MMXq =2207,
-  XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb =2208, +  XED_IFORM_PSHUFB_XMMdq_MEMdq =2208,
-  XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb =2209, +  XED_IFORM_PSHUFB_XMMdq_XMMdq =2209,
-  XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb =2210, +  XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb =2210,
-  XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb =2211, +  XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb =2211,
-  XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb =2212, +  XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb =2212,
-  XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb =2213, +  XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb =2213,
-  XED_IFORM_PSHUFW_MMXq_MEMq_IMMb =2214, +  XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb =2214,
-  XED_IFORM_PSHUFW_MMXq_MMXq_IMMb =2215, +  XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb =2215,
-  XED_IFORM_PSIGNB_MMXq_MEMq =2216, +  XED_IFORM_PSHUFW_MMXq_MEMq_IMMb =2216,
-  XED_IFORM_PSIGNB_MMXq_MMXq =2217, +  XED_IFORM_PSHUFW_MMXq_MMXq_IMMb =2217,
-  XED_IFORM_PSIGNB_XMMdq_MEMdq =2218, +  XED_IFORM_PSIGNB_MMXq_MEMq =2218,
-  XED_IFORM_PSIGNB_XMMdq_XMMdq =2219, +  XED_IFORM_PSIGNB_MMXq_MMXq =2219,
-  XED_IFORM_PSIGND_MMXq_MEMq =2220, +  XED_IFORM_PSIGNB_XMMdq_MEMdq =2220,
-  XED_IFORM_PSIGND_MMXq_MMXq =2221, +  XED_IFORM_PSIGNB_XMMdq_XMMdq =2221,
-  XED_IFORM_PSIGND_XMMdq_MEMdq =2222, +  XED_IFORM_PSIGND_MMXq_MEMq =2222,
-  XED_IFORM_PSIGND_XMMdq_XMMdq =2223, +  XED_IFORM_PSIGND_MMXq_MMXq =2223,
-  XED_IFORM_PSIGNW_MMXq_MEMq =2224, +  XED_IFORM_PSIGND_XMMdq_MEMdq =2224,
-  XED_IFORM_PSIGNW_MMXq_MMXq =2225, +  XED_IFORM_PSIGND_XMMdq_XMMdq =2225,
-  XED_IFORM_PSIGNW_XMMdq_MEMdq =2226, +  XED_IFORM_PSIGNW_MMXq_MEMq =2226,
-  XED_IFORM_PSIGNW_XMMdq_XMMdq =2227, +  XED_IFORM_PSIGNW_MMXq_MMXq =2227,
-  XED_IFORM_PSLLD_MMXq_IMMb =2228, +  XED_IFORM_PSIGNW_XMMdq_MEMdq =2228,
-  XED_IFORM_PSLLD_MMXq_MEMq =2229, +  XED_IFORM_PSIGNW_XMMdq_XMMdq =2229,
-  XED_IFORM_PSLLD_MMXq_MMXq =2230, +  XED_IFORM_PSLLD_MMXq_IMMb =2230,
-  XED_IFORM_PSLLD_XMMdq_IMMb =2231, +  XED_IFORM_PSLLD_MMXq_MEMq =2231,
-  XED_IFORM_PSLLD_XMMdq_MEMdq =2232, +  XED_IFORM_PSLLD_MMXq_MMXq =2232,
-  XED_IFORM_PSLLD_XMMdq_XMMdq =2233, +  XED_IFORM_PSLLD_XMMdq_IMMb =2233,
-  XED_IFORM_PSLLDQ_XMMdq_IMMb =2234, +  XED_IFORM_PSLLD_XMMdq_MEMdq =2234,
-  XED_IFORM_PSLLQ_MMXq_IMMb =2235, +  XED_IFORM_PSLLD_XMMdq_XMMdq =2235,
-  XED_IFORM_PSLLQ_MMXq_MEMq =2236, +  XED_IFORM_PSLLDQ_XMMdq_IMMb =2236,
-  XED_IFORM_PSLLQ_MMXq_MMXq =2237, +  XED_IFORM_PSLLQ_MMXq_IMMb =2237,
-  XED_IFORM_PSLLQ_XMMdq_IMMb =2238, +  XED_IFORM_PSLLQ_MMXq_MEMq =2238,
-  XED_IFORM_PSLLQ_XMMdq_MEMdq =2239, +  XED_IFORM_PSLLQ_MMXq_MMXq =2239,
-  XED_IFORM_PSLLQ_XMMdq_XMMdq =2240, +  XED_IFORM_PSLLQ_XMMdq_IMMb =2240,
-  XED_IFORM_PSLLW_MMXq_IMMb =2241, +  XED_IFORM_PSLLQ_XMMdq_MEMdq =2241,
-  XED_IFORM_PSLLW_MMXq_MEMq =2242, +  XED_IFORM_PSLLQ_XMMdq_XMMdq =2242,
-  XED_IFORM_PSLLW_MMXq_MMXq =2243, +  XED_IFORM_PSLLW_MMXq_IMMb =2243,
-  XED_IFORM_PSLLW_XMMdq_IMMb =2244, +  XED_IFORM_PSLLW_MMXq_MEMq =2244,
-  XED_IFORM_PSLLW_XMMdq_MEMdq =2245, +  XED_IFORM_PSLLW_MMXq_MMXq =2245,
-  XED_IFORM_PSLLW_XMMdq_XMMdq =2246, +  XED_IFORM_PSLLW_XMMdq_IMMb =2246,
-  XED_IFORM_PSMASH_RAX =2247, +  XED_IFORM_PSLLW_XMMdq_MEMdq =2247,
-  XED_IFORM_PSRAD_MMXq_IMMb =2248, +  XED_IFORM_PSLLW_XMMdq_XMMdq =2248,
-  XED_IFORM_PSRAD_MMXq_MEMq =2249, +  XED_IFORM_PSMASH_RAX =2249,
-  XED_IFORM_PSRAD_MMXq_MMXq =2250, +  XED_IFORM_PSRAD_MMXq_IMMb =2250,
-  XED_IFORM_PSRAD_XMMdq_IMMb =2251, +  XED_IFORM_PSRAD_MMXq_MEMq =2251,
-  XED_IFORM_PSRAD_XMMdq_MEMdq =2252, +  XED_IFORM_PSRAD_MMXq_MMXq =2252,
-  XED_IFORM_PSRAD_XMMdq_XMMdq =2253, +  XED_IFORM_PSRAD_XMMdq_IMMb =2253,
-  XED_IFORM_PSRAW_MMXq_IMMb =2254, +  XED_IFORM_PSRAD_XMMdq_MEMdq =2254,
-  XED_IFORM_PSRAW_MMXq_MEMq =2255, +  XED_IFORM_PSRAD_XMMdq_XMMdq =2255,
-  XED_IFORM_PSRAW_MMXq_MMXq =2256, +  XED_IFORM_PSRAW_MMXq_IMMb =2256,
-  XED_IFORM_PSRAW_XMMdq_IMMb =2257, +  XED_IFORM_PSRAW_MMXq_MEMq =2257,
-  XED_IFORM_PSRAW_XMMdq_MEMdq =2258, +  XED_IFORM_PSRAW_MMXq_MMXq =2258,
-  XED_IFORM_PSRAW_XMMdq_XMMdq =2259, +  XED_IFORM_PSRAW_XMMdq_IMMb =2259,
-  XED_IFORM_PSRLD_MMXq_IMMb =2260, +  XED_IFORM_PSRAW_XMMdq_MEMdq =2260,
-  XED_IFORM_PSRLD_MMXq_MEMq =2261, +  XED_IFORM_PSRAW_XMMdq_XMMdq =2261,
-  XED_IFORM_PSRLD_MMXq_MMXq =2262, +  XED_IFORM_PSRLD_MMXq_IMMb =2262,
-  XED_IFORM_PSRLD_XMMdq_IMMb =2263, +  XED_IFORM_PSRLD_MMXq_MEMq =2263,
-  XED_IFORM_PSRLD_XMMdq_MEMdq =2264, +  XED_IFORM_PSRLD_MMXq_MMXq =2264,
-  XED_IFORM_PSRLD_XMMdq_XMMdq =2265, +  XED_IFORM_PSRLD_XMMdq_IMMb =2265,
-  XED_IFORM_PSRLDQ_XMMdq_IMMb =2266, +  XED_IFORM_PSRLD_XMMdq_MEMdq =2266,
-  XED_IFORM_PSRLQ_MMXq_IMMb =2267, +  XED_IFORM_PSRLD_XMMdq_XMMdq =2267,
-  XED_IFORM_PSRLQ_MMXq_MEMq =2268, +  XED_IFORM_PSRLDQ_XMMdq_IMMb =2268,
-  XED_IFORM_PSRLQ_MMXq_MMXq =2269, +  XED_IFORM_PSRLQ_MMXq_IMMb =2269,
-  XED_IFORM_PSRLQ_XMMdq_IMMb =2270, +  XED_IFORM_PSRLQ_MMXq_MEMq =2270,
-  XED_IFORM_PSRLQ_XMMdq_MEMdq =2271, +  XED_IFORM_PSRLQ_MMXq_MMXq =2271,
-  XED_IFORM_PSRLQ_XMMdq_XMMdq =2272, +  XED_IFORM_PSRLQ_XMMdq_IMMb =2272,
-  XED_IFORM_PSRLW_MMXq_IMMb =2273, +  XED_IFORM_PSRLQ_XMMdq_MEMdq =2273,
-  XED_IFORM_PSRLW_MMXq_MEMq =2274, +  XED_IFORM_PSRLQ_XMMdq_XMMdq =2274,
-  XED_IFORM_PSRLW_MMXq_MMXq =2275, +  XED_IFORM_PSRLW_MMXq_IMMb =2275,
-  XED_IFORM_PSRLW_XMMdq_IMMb =2276, +  XED_IFORM_PSRLW_MMXq_MEMq =2276,
-  XED_IFORM_PSRLW_XMMdq_MEMdq =2277, +  XED_IFORM_PSRLW_MMXq_MMXq =2277,
-  XED_IFORM_PSRLW_XMMdq_XMMdq =2278, +  XED_IFORM_PSRLW_XMMdq_IMMb =2278,
-  XED_IFORM_PSUBB_MMXq_MEMq =2279, +  XED_IFORM_PSRLW_XMMdq_MEMdq =2279,
-  XED_IFORM_PSUBB_MMXq_MMXq =2280, +  XED_IFORM_PSRLW_XMMdq_XMMdq =2280,
-  XED_IFORM_PSUBB_XMMdq_MEMdq =2281, +  XED_IFORM_PSUBB_MMXq_MEMq =2281,
-  XED_IFORM_PSUBB_XMMdq_XMMdq =2282, +  XED_IFORM_PSUBB_MMXq_MMXq =2282,
-  XED_IFORM_PSUBD_MMXq_MEMq =2283, +  XED_IFORM_PSUBB_XMMdq_MEMdq =2283,
-  XED_IFORM_PSUBD_MMXq_MMXq =2284, +  XED_IFORM_PSUBB_XMMdq_XMMdq =2284,
-  XED_IFORM_PSUBD_XMMdq_MEMdq =2285, +  XED_IFORM_PSUBD_MMXq_MEMq =2285,
-  XED_IFORM_PSUBD_XMMdq_XMMdq =2286, +  XED_IFORM_PSUBD_MMXq_MMXq =2286,
-  XED_IFORM_PSUBQ_MMXq_MEMq =2287, +  XED_IFORM_PSUBD_XMMdq_MEMdq =2287,
-  XED_IFORM_PSUBQ_MMXq_MMXq =2288, +  XED_IFORM_PSUBD_XMMdq_XMMdq =2288,
-  XED_IFORM_PSUBQ_XMMdq_MEMdq =2289, +  XED_IFORM_PSUBQ_MMXq_MEMq =2289,
-  XED_IFORM_PSUBQ_XMMdq_XMMdq =2290, +  XED_IFORM_PSUBQ_MMXq_MMXq =2290,
-  XED_IFORM_PSUBSB_MMXq_MEMq =2291, +  XED_IFORM_PSUBQ_XMMdq_MEMdq =2291,
-  XED_IFORM_PSUBSB_MMXq_MMXq =2292, +  XED_IFORM_PSUBQ_XMMdq_XMMdq =2292,
-  XED_IFORM_PSUBSB_XMMdq_MEMdq =2293, +  XED_IFORM_PSUBSB_MMXq_MEMq =2293,
-  XED_IFORM_PSUBSB_XMMdq_XMMdq =2294, +  XED_IFORM_PSUBSB_MMXq_MMXq =2294,
-  XED_IFORM_PSUBSW_MMXq_MEMq =2295, +  XED_IFORM_PSUBSB_XMMdq_MEMdq =2295,
-  XED_IFORM_PSUBSW_MMXq_MMXq =2296, +  XED_IFORM_PSUBSB_XMMdq_XMMdq =2296,
-  XED_IFORM_PSUBSW_XMMdq_MEMdq =2297, +  XED_IFORM_PSUBSW_MMXq_MEMq =2297,
-  XED_IFORM_PSUBSW_XMMdq_XMMdq =2298, +  XED_IFORM_PSUBSW_MMXq_MMXq =2298,
-  XED_IFORM_PSUBUSB_MMXq_MEMq =2299, +  XED_IFORM_PSUBSW_XMMdq_MEMdq =2299,
-  XED_IFORM_PSUBUSB_MMXq_MMXq =2300, +  XED_IFORM_PSUBSW_XMMdq_XMMdq =2300,
-  XED_IFORM_PSUBUSB_XMMdq_MEMdq =2301, +  XED_IFORM_PSUBUSB_MMXq_MEMq =2301,
-  XED_IFORM_PSUBUSB_XMMdq_XMMdq =2302, +  XED_IFORM_PSUBUSB_MMXq_MMXq =2302,
-  XED_IFORM_PSUBUSW_MMXq_MEMq =2303, +  XED_IFORM_PSUBUSB_XMMdq_MEMdq =2303,
-  XED_IFORM_PSUBUSW_MMXq_MMXq =2304, +  XED_IFORM_PSUBUSB_XMMdq_XMMdq =2304,
-  XED_IFORM_PSUBUSW_XMMdq_MEMdq =2305, +  XED_IFORM_PSUBUSW_MMXq_MEMq =2305,
-  XED_IFORM_PSUBUSW_XMMdq_XMMdq =2306, +  XED_IFORM_PSUBUSW_MMXq_MMXq =2306,
-  XED_IFORM_PSUBW_MMXq_MEMq =2307, +  XED_IFORM_PSUBUSW_XMMdq_MEMdq =2307,
-  XED_IFORM_PSUBW_MMXq_MMXq =2308, +  XED_IFORM_PSUBUSW_XMMdq_XMMdq =2308,
-  XED_IFORM_PSUBW_XMMdq_MEMdq =2309, +  XED_IFORM_PSUBW_MMXq_MEMq =2309,
-  XED_IFORM_PSUBW_XMMdq_XMMdq =2310, +  XED_IFORM_PSUBW_MMXq_MMXq =2310,
-  XED_IFORM_PSWAPD_MMXq_MEMq =2311, +  XED_IFORM_PSUBW_XMMdq_MEMdq =2311,
-  XED_IFORM_PSWAPD_MMXq_MMXq =2312, +  XED_IFORM_PSUBW_XMMdq_XMMdq =2312,
-  XED_IFORM_PTEST_XMMdq_MEMdq =2313, +  XED_IFORM_PSWAPD_MMXq_MEMq =2313,
-  XED_IFORM_PTEST_XMMdq_XMMdq =2314, +  XED_IFORM_PSWAPD_MMXq_MMXq =2314,
-  XED_IFORM_PTWRITE_GPRy =2315, +  XED_IFORM_PTEST_XMMdq_MEMdq =2315,
-  XED_IFORM_PTWRITE_MEMy =2316, +  XED_IFORM_PTEST_XMMdq_XMMdq =2316,
-  XED_IFORM_PUNPCKHBW_MMXq_MEMq =2317, +  XED_IFORM_PTWRITE_GPRy =2317,
-  XED_IFORM_PUNPCKHBW_MMXq_MMXd =2318, +  XED_IFORM_PTWRITE_MEMy =2318,
-  XED_IFORM_PUNPCKHBW_XMMdq_MEMdq =2319, +  XED_IFORM_PUNPCKHBW_MMXq_MEMq =2319,
-  XED_IFORM_PUNPCKHBW_XMMdq_XMMq =2320, +  XED_IFORM_PUNPCKHBW_MMXq_MMXd =2320,
-  XED_IFORM_PUNPCKHDQ_MMXq_MEMq =2321, +  XED_IFORM_PUNPCKHBW_XMMdq_MEMdq =2321,
-  XED_IFORM_PUNPCKHDQ_MMXq_MMXd =2322, +  XED_IFORM_PUNPCKHBW_XMMdq_XMMq =2322,
-  XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq =2323, +  XED_IFORM_PUNPCKHDQ_MMXq_MEMq =2323,
-  XED_IFORM_PUNPCKHDQ_XMMdq_XMMq =2324, +  XED_IFORM_PUNPCKHDQ_MMXq_MMXd =2324,
-  XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq =2325, +  XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq =2325,
-  XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq =2326, +  XED_IFORM_PUNPCKHDQ_XMMdq_XMMq =2326,
-  XED_IFORM_PUNPCKHWD_MMXq_MEMq =2327, +  XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq =2327,
-  XED_IFORM_PUNPCKHWD_MMXq_MMXd =2328, +  XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq =2328,
-  XED_IFORM_PUNPCKHWD_XMMdq_MEMdq =2329, +  XED_IFORM_PUNPCKHWD_MMXq_MEMq =2329,
-  XED_IFORM_PUNPCKHWD_XMMdq_XMMq =2330, +  XED_IFORM_PUNPCKHWD_MMXq_MMXd =2330,
-  XED_IFORM_PUNPCKLBW_MMXq_MEMd =2331, +  XED_IFORM_PUNPCKHWD_XMMdq_MEMdq =2331,
-  XED_IFORM_PUNPCKLBW_MMXq_MMXd =2332, +  XED_IFORM_PUNPCKHWD_XMMdq_XMMq =2332,
-  XED_IFORM_PUNPCKLBW_XMMdq_MEMdq =2333, +  XED_IFORM_PUNPCKLBW_MMXq_MEMd =2333,
-  XED_IFORM_PUNPCKLBW_XMMdq_XMMq =2334, +  XED_IFORM_PUNPCKLBW_MMXq_MMXd =2334,
-  XED_IFORM_PUNPCKLDQ_MMXq_MEMd =2335, +  XED_IFORM_PUNPCKLBW_XMMdq_MEMdq =2335,
-  XED_IFORM_PUNPCKLDQ_MMXq_MMXd =2336, +  XED_IFORM_PUNPCKLBW_XMMdq_XMMq =2336,
-  XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq =2337, +  XED_IFORM_PUNPCKLDQ_MMXq_MEMd =2337,
-  XED_IFORM_PUNPCKLDQ_XMMdq_XMMq =2338, +  XED_IFORM_PUNPCKLDQ_MMXq_MMXd =2338,
-  XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq =2339, +  XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq =2339,
-  XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq =2340, +  XED_IFORM_PUNPCKLDQ_XMMdq_XMMq =2340,
-  XED_IFORM_PUNPCKLWD_MMXq_MEMd =2341, +  XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq =2341,
-  XED_IFORM_PUNPCKLWD_MMXq_MMXd =2342, +  XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq =2342,
-  XED_IFORM_PUNPCKLWD_XMMdq_MEMdq =2343, +  XED_IFORM_PUNPCKLWD_MMXq_MEMd =2343,
-  XED_IFORM_PUNPCKLWD_XMMdq_XMMq =2344, +  XED_IFORM_PUNPCKLWD_MMXq_MMXd =2344,
-  XED_IFORM_PUSH_CS =2345, +  XED_IFORM_PUNPCKLWD_XMMdq_MEMdq =2345,
-  XED_IFORM_PUSH_DS =2346, +  XED_IFORM_PUNPCKLWD_XMMdq_XMMq =2346,
-  XED_IFORM_PUSH_ES =2347, +  XED_IFORM_PUSH_CS =2347,
-  XED_IFORM_PUSH_FS =2348, +  XED_IFORM_PUSH_DS =2348,
-  XED_IFORM_PUSH_GPRv_50 =2349, +  XED_IFORM_PUSH_ES =2349,
-  XED_IFORM_PUSH_GPRv_FFr6 =2350, +  XED_IFORM_PUSH_FS =2350,
-  XED_IFORM_PUSH_GS =2351, +  XED_IFORM_PUSH_GPRv_50 =2351,
-  XED_IFORM_PUSH_IMMb =2352, +  XED_IFORM_PUSH_GPRv_FFr6 =2352,
-  XED_IFORM_PUSH_IMMz =2353, +  XED_IFORM_PUSH_GS =2353,
-  XED_IFORM_PUSH_MEMv =2354, +  XED_IFORM_PUSH_IMMb =2354,
-  XED_IFORM_PUSH_SS =2355, +  XED_IFORM_PUSH_IMMz =2355,
-  XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX =2356, +  XED_IFORM_PUSH_MEMv =2356,
-  XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX =2357, +  XED_IFORM_PUSH_SS =2357,
-  XED_IFORM_PUSHA =2358, +  XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX =2358,
-  XED_IFORM_PUSHAD =2359, +  XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX =2359,
-  XED_IFORM_PUSHF =2360, +  XED_IFORM_PUSHA =2360,
-  XED_IFORM_PUSHFD =2361, +  XED_IFORM_PUSHAD =2361,
-  XED_IFORM_PUSHFQ =2362, +  XED_IFORM_PUSHF =2362,
-  XED_IFORM_PUSHP_GPR64 =2363, +  XED_IFORM_PUSHFD =2363,
-  XED_IFORM_PVALIDATE_RAX_ECX_EDX =2364, +  XED_IFORM_PUSHFQ =2364,
-  XED_IFORM_PXOR_MMXq_MEMq =2365, +  XED_IFORM_PUSHP_GPR64 =2365,
-  XED_IFORM_PXOR_MMXq_MMXq =2366, +  XED_IFORM_PVALIDATE_RAX_ECX_EDX =2366,
-  XED_IFORM_PXOR_XMMdq_MEMdq =2367, +  XED_IFORM_PXOR_MMXq_MEMq =2367,
-  XED_IFORM_PXOR_XMMdq_XMMdq =2368, +  XED_IFORM_PXOR_MMXq_MMXq =2368,
-  XED_IFORM_RCL_GPR8_CL =2369, +  XED_IFORM_PXOR_XMMdq_MEMdq =2369,
-  XED_IFORM_RCL_GPR8_IMMb =2370, +  XED_IFORM_PXOR_XMMdq_XMMdq =2370,
-  XED_IFORM_RCL_GPR8_ONE =2371, +  XED_IFORM_RCL_GPR8_CL =2371,
-  XED_IFORM_RCL_GPR8i8_CL_APX =2372, +  XED_IFORM_RCL_GPR8_IMMb =2372,
-  XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX =2373, +  XED_IFORM_RCL_GPR8_ONE =2373,
-  XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX =2374, +  XED_IFORM_RCL_GPR8i8_CL_APX =2374,
-  XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX =2375, +  XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX =2375,
-  XED_IFORM_RCL_GPR8i8_IMM8_APX =2376, +  XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX =2376,
-  XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX =2377, +  XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX =2377,
-  XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX =2378, +  XED_IFORM_RCL_GPR8i8_IMM8_APX =2378,
-  XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX =2379, +  XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX =2379,
-  XED_IFORM_RCL_GPR8i8_ONE_APX =2380, +  XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX =2380,
-  XED_IFORM_RCL_GPRv_CL =2381, +  XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX =2381,
-  XED_IFORM_RCL_GPRv_CL_APX =2382, +  XED_IFORM_RCL_GPR8i8_ONE_APX =2382,
-  XED_IFORM_RCL_GPRv_GPRv_CL_APX =2383, +  XED_IFORM_RCL_GPRv_CL =2383,
-  XED_IFORM_RCL_GPRv_GPRv_IMM8_APX =2384, +  XED_IFORM_RCL_GPRv_CL_APX =2384,
-  XED_IFORM_RCL_GPRv_GPRv_ONE_APX =2385, +  XED_IFORM_RCL_GPRv_GPRv_CL_APX =2385,
-  XED_IFORM_RCL_GPRv_IMM8_APX =2386, +  XED_IFORM_RCL_GPRv_GPRv_IMM8_APX =2386,
-  XED_IFORM_RCL_GPRv_IMMb =2387, +  XED_IFORM_RCL_GPRv_GPRv_ONE_APX =2387,
-  XED_IFORM_RCL_GPRv_MEMv_CL_APX =2388, +  XED_IFORM_RCL_GPRv_IMM8_APX =2388,
-  XED_IFORM_RCL_GPRv_MEMv_IMM8_APX =2389, +  XED_IFORM_RCL_GPRv_IMMb =2389,
-  XED_IFORM_RCL_GPRv_MEMv_ONE_APX =2390, +  XED_IFORM_RCL_GPRv_MEMv_CL_APX =2390,
-  XED_IFORM_RCL_GPRv_ONE =2391, +  XED_IFORM_RCL_GPRv_MEMv_IMM8_APX =2391,
-  XED_IFORM_RCL_GPRv_ONE_APX =2392, +  XED_IFORM_RCL_GPRv_MEMv_ONE_APX =2392,
-  XED_IFORM_RCL_MEMb_CL =2393, +  XED_IFORM_RCL_GPRv_ONE =2393,
-  XED_IFORM_RCL_MEMb_IMMb =2394, +  XED_IFORM_RCL_GPRv_ONE_APX =2394,
-  XED_IFORM_RCL_MEMb_ONE =2395, +  XED_IFORM_RCL_MEMb_CL =2395,
-  XED_IFORM_RCL_MEMi8_CL_APX =2396, +  XED_IFORM_RCL_MEMb_IMMb =2396,
-  XED_IFORM_RCL_MEMi8_IMM8_APX =2397, +  XED_IFORM_RCL_MEMb_ONE =2397,
-  XED_IFORM_RCL_MEMi8_ONE_APX =2398, +  XED_IFORM_RCL_MEMi8_CL_APX =2398,
-  XED_IFORM_RCL_MEMv_CL =2399, +  XED_IFORM_RCL_MEMi8_IMM8_APX =2399,
-  XED_IFORM_RCL_MEMv_CL_APX =2400, +  XED_IFORM_RCL_MEMi8_ONE_APX =2400,
-  XED_IFORM_RCL_MEMv_IMM8_APX =2401, +  XED_IFORM_RCL_MEMv_CL =2401,
-  XED_IFORM_RCL_MEMv_IMMb =2402, +  XED_IFORM_RCL_MEMv_CL_APX =2402,
-  XED_IFORM_RCL_MEMv_ONE =2403, +  XED_IFORM_RCL_MEMv_IMM8_APX =2403,
-  XED_IFORM_RCL_MEMv_ONE_APX =2404, +  XED_IFORM_RCL_MEMv_IMMb =2404,
-  XED_IFORM_RCPPS_XMMps_MEMps =2405, +  XED_IFORM_RCL_MEMv_ONE =2405,
-  XED_IFORM_RCPPS_XMMps_XMMps =2406, +  XED_IFORM_RCL_MEMv_ONE_APX =2406,
-  XED_IFORM_RCPSS_XMMss_MEMss =2407, +  XED_IFORM_RCPPS_XMMps_MEMps =2407,
-  XED_IFORM_RCPSS_XMMss_XMMss =2408, +  XED_IFORM_RCPPS_XMMps_XMMps =2408,
-  XED_IFORM_RCR_GPR8_CL =2409, +  XED_IFORM_RCPSS_XMMss_MEMss =2409,
-  XED_IFORM_RCR_GPR8_IMMb =2410, +  XED_IFORM_RCPSS_XMMss_XMMss =2410,
-  XED_IFORM_RCR_GPR8_ONE =2411, +  XED_IFORM_RCR_GPR8_CL =2411,
-  XED_IFORM_RCR_GPR8i8_CL_APX =2412, +  XED_IFORM_RCR_GPR8_IMMb =2412,
-  XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX =2413, +  XED_IFORM_RCR_GPR8_ONE =2413,
-  XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX =2414, +  XED_IFORM_RCR_GPR8i8_CL_APX =2414,
-  XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX =2415, +  XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX =2415,
-  XED_IFORM_RCR_GPR8i8_IMM8_APX =2416, +  XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX =2416,
-  XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX =2417, +  XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX =2417,
-  XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX =2418, +  XED_IFORM_RCR_GPR8i8_IMM8_APX =2418,
-  XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX =2419, +  XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX =2419,
-  XED_IFORM_RCR_GPR8i8_ONE_APX =2420, +  XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX =2420,
-  XED_IFORM_RCR_GPRv_CL =2421, +  XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX =2421,
-  XED_IFORM_RCR_GPRv_CL_APX =2422, +  XED_IFORM_RCR_GPR8i8_ONE_APX =2422,
-  XED_IFORM_RCR_GPRv_GPRv_CL_APX =2423, +  XED_IFORM_RCR_GPRv_CL =2423,
-  XED_IFORM_RCR_GPRv_GPRv_IMM8_APX =2424, +  XED_IFORM_RCR_GPRv_CL_APX =2424,
-  XED_IFORM_RCR_GPRv_GPRv_ONE_APX =2425, +  XED_IFORM_RCR_GPRv_GPRv_CL_APX =2425,
-  XED_IFORM_RCR_GPRv_IMM8_APX =2426, +  XED_IFORM_RCR_GPRv_GPRv_IMM8_APX =2426,
-  XED_IFORM_RCR_GPRv_IMMb =2427, +  XED_IFORM_RCR_GPRv_GPRv_ONE_APX =2427,
-  XED_IFORM_RCR_GPRv_MEMv_CL_APX =2428, +  XED_IFORM_RCR_GPRv_IMM8_APX =2428,
-  XED_IFORM_RCR_GPRv_MEMv_IMM8_APX =2429, +  XED_IFORM_RCR_GPRv_IMMb =2429,
-  XED_IFORM_RCR_GPRv_MEMv_ONE_APX =2430, +  XED_IFORM_RCR_GPRv_MEMv_CL_APX =2430,
-  XED_IFORM_RCR_GPRv_ONE =2431, +  XED_IFORM_RCR_GPRv_MEMv_IMM8_APX =2431,
-  XED_IFORM_RCR_GPRv_ONE_APX =2432, +  XED_IFORM_RCR_GPRv_MEMv_ONE_APX =2432,
-  XED_IFORM_RCR_MEMb_CL =2433, +  XED_IFORM_RCR_GPRv_ONE =2433,
-  XED_IFORM_RCR_MEMb_IMMb =2434, +  XED_IFORM_RCR_GPRv_ONE_APX =2434,
-  XED_IFORM_RCR_MEMb_ONE =2435, +  XED_IFORM_RCR_MEMb_CL =2435,
-  XED_IFORM_RCR_MEMi8_CL_APX =2436, +  XED_IFORM_RCR_MEMb_IMMb =2436,
-  XED_IFORM_RCR_MEMi8_IMM8_APX =2437, +  XED_IFORM_RCR_MEMb_ONE =2437,
-  XED_IFORM_RCR_MEMi8_ONE_APX =2438, +  XED_IFORM_RCR_MEMi8_CL_APX =2438,
-  XED_IFORM_RCR_MEMv_CL =2439, +  XED_IFORM_RCR_MEMi8_IMM8_APX =2439,
-  XED_IFORM_RCR_MEMv_CL_APX =2440, +  XED_IFORM_RCR_MEMi8_ONE_APX =2440,
-  XED_IFORM_RCR_MEMv_IMM8_APX =2441, +  XED_IFORM_RCR_MEMv_CL =2441,
-  XED_IFORM_RCR_MEMv_IMMb =2442, +  XED_IFORM_RCR_MEMv_CL_APX =2442,
-  XED_IFORM_RCR_MEMv_ONE =2443, +  XED_IFORM_RCR_MEMv_IMM8_APX =2443,
-  XED_IFORM_RCR_MEMv_ONE_APX =2444, +  XED_IFORM_RCR_MEMv_IMMb =2444,
-  XED_IFORM_RDFSBASE_GPRy =2445, +  XED_IFORM_RCR_MEMv_ONE =2445,
-  XED_IFORM_RDGSBASE_GPRy =2446, +  XED_IFORM_RCR_MEMv_ONE_APX =2446,
-  XED_IFORM_RDMSR =2447, +  XED_IFORM_RDFSBASE_GPRy =2447,
-  XED_IFORM_RDMSRLIST =2448, +  XED_IFORM_RDGSBASE_GPRy =2448,
-  XED_IFORM_RDPID_GPR32u32 =2449, +  XED_IFORM_RDMSR =2449,
-  XED_IFORM_RDPID_GPR64u64 =2450, +  XED_IFORM_RDMSR_GPR64u64_IMM32 =2450,
-  XED_IFORM_RDPKRU =2451, +  XED_IFORM_RDMSR_GPR64u64_IMM32_APX =2451,
-  XED_IFORM_RDPMC =2452, +  XED_IFORM_RDMSRLIST =2452,
-  XED_IFORM_RDPRU =2453, +  XED_IFORM_RDPID_GPR32u32 =2453,
-  XED_IFORM_RDRAND_GPRv =2454, +  XED_IFORM_RDPID_GPR64u64 =2454,
-  XED_IFORM_RDSEED_GPRv =2455, +  XED_IFORM_RDPKRU =2455,
-  XED_IFORM_RDSSPD_GPR32u32 =2456, +  XED_IFORM_RDPMC =2456,
-  XED_IFORM_RDSSPQ_GPR64u64 =2457, +  XED_IFORM_RDPRU =2457,
-  XED_IFORM_RDTSC =2458, +  XED_IFORM_RDRAND_GPRv =2458,
-  XED_IFORM_RDTSCP =2459, +  XED_IFORM_RDSEED_GPRv =2459,
-  XED_IFORM_REPE_CMPSB =2460, +  XED_IFORM_RDSSPD_GPR32u32 =2460,
-  XED_IFORM_REPE_CMPSD =2461, +  XED_IFORM_RDSSPQ_GPR64u64 =2461,
-  XED_IFORM_REPE_CMPSQ =2462, +  XED_IFORM_RDTSC =2462,
-  XED_IFORM_REPE_CMPSW =2463, +  XED_IFORM_RDTSCP =2463,
-  XED_IFORM_REPE_SCASB =2464, +  XED_IFORM_REPE_CMPSB =2464,
-  XED_IFORM_REPE_SCASD =2465, +  XED_IFORM_REPE_CMPSD =2465,
-  XED_IFORM_REPE_SCASQ =2466, +  XED_IFORM_REPE_CMPSQ =2466,
-  XED_IFORM_REPE_SCASW =2467, +  XED_IFORM_REPE_CMPSW =2467,
-  XED_IFORM_REPNE_CMPSB =2468, +  XED_IFORM_REPE_SCASB =2468,
-  XED_IFORM_REPNE_CMPSD =2469, +  XED_IFORM_REPE_SCASD =2469,
-  XED_IFORM_REPNE_CMPSQ =2470, +  XED_IFORM_REPE_SCASQ =2470,
-  XED_IFORM_REPNE_CMPSW =2471, +  XED_IFORM_REPE_SCASW =2471,
-  XED_IFORM_REPNE_SCASB =2472, +  XED_IFORM_REPNE_CMPSB =2472,
-  XED_IFORM_REPNE_SCASD =2473, +  XED_IFORM_REPNE_CMPSD =2473,
-  XED_IFORM_REPNE_SCASQ =2474, +  XED_IFORM_REPNE_CMPSQ =2474,
-  XED_IFORM_REPNE_SCASW =2475, +  XED_IFORM_REPNE_CMPSW =2475,
-  XED_IFORM_REP_INSB =2476, +  XED_IFORM_REPNE_SCASB =2476,
-  XED_IFORM_REP_INSD =2477, +  XED_IFORM_REPNE_SCASD =2477,
-  XED_IFORM_REP_INSW =2478, +  XED_IFORM_REPNE_SCASQ =2478,
-  XED_IFORM_REP_LODSB =2479, +  XED_IFORM_REPNE_SCASW =2479,
-  XED_IFORM_REP_LODSD =2480, +  XED_IFORM_REP_INSB =2480,
-  XED_IFORM_REP_LODSQ =2481, +  XED_IFORM_REP_INSD =2481,
-  XED_IFORM_REP_LODSW =2482, +  XED_IFORM_REP_INSW =2482,
-  XED_IFORM_REP_MONTMUL =2483, +  XED_IFORM_REP_LODSB =2483,
-  XED_IFORM_REP_MOVSB =2484, +  XED_IFORM_REP_LODSD =2484,
-  XED_IFORM_REP_MOVSD =2485, +  XED_IFORM_REP_LODSQ =2485,
-  XED_IFORM_REP_MOVSQ =2486, +  XED_IFORM_REP_LODSW =2486,
-  XED_IFORM_REP_MOVSW =2487, +  XED_IFORM_REP_MONTMUL =2487,
-  XED_IFORM_REP_OUTSB =2488, +  XED_IFORM_REP_MOVSB =2488,
-  XED_IFORM_REP_OUTSD =2489, +  XED_IFORM_REP_MOVSD =2489,
-  XED_IFORM_REP_OUTSW =2490, +  XED_IFORM_REP_MOVSQ =2490,
-  XED_IFORM_REP_STOSB =2491, +  XED_IFORM_REP_MOVSW =2491,
-  XED_IFORM_REP_STOSD =2492, +  XED_IFORM_REP_OUTSB =2492,
-  XED_IFORM_REP_STOSQ =2493, +  XED_IFORM_REP_OUTSD =2493,
-  XED_IFORM_REP_STOSW =2494, +  XED_IFORM_REP_OUTSW =2494,
-  XED_IFORM_REP_XCRYPTCBC =2495, +  XED_IFORM_REP_STOSB =2495,
-  XED_IFORM_REP_XCRYPTCFB =2496, +  XED_IFORM_REP_STOSD =2496,
-  XED_IFORM_REP_XCRYPTCTR =2497, +  XED_IFORM_REP_STOSQ =2497,
-  XED_IFORM_REP_XCRYPTECB =2498, +  XED_IFORM_REP_STOSW =2498,
-  XED_IFORM_REP_XCRYPTOFB =2499, +  XED_IFORM_REP_XCRYPTCBC =2499,
-  XED_IFORM_REP_XSHA1 =2500, +  XED_IFORM_REP_XCRYPTCFB =2500,
-  XED_IFORM_REP_XSHA256 =2501, +  XED_IFORM_REP_XCRYPTCTR =2501,
-  XED_IFORM_REP_XSTORE =2502, +  XED_IFORM_REP_XCRYPTECB =2502,
-  XED_IFORM_RET_FAR =2503, +  XED_IFORM_REP_XCRYPTOFB =2503,
-  XED_IFORM_RET_FAR_IMMw =2504, +  XED_IFORM_REP_XSHA1 =2504,
-  XED_IFORM_RET_NEAR =2505, +  XED_IFORM_REP_XSHA256 =2505,
-  XED_IFORM_RET_NEAR_IMMw =2506, +  XED_IFORM_REP_XSTORE =2506,
-  XED_IFORM_RMPADJUST_RAX_RCX_RDX =2507, +  XED_IFORM_RET_FAR =2507,
-  XED_IFORM_RMPUPDATE_RAX_RCX =2508, +  XED_IFORM_RET_FAR_IMMw =2508,
-  XED_IFORM_ROL_GPR8_CL =2509, +  XED_IFORM_RET_NEAR =2509,
-  XED_IFORM_ROL_GPR8_IMMb =2510, +  XED_IFORM_RET_NEAR_IMMw =2510,
-  XED_IFORM_ROL_GPR8_ONE =2511, +  XED_IFORM_RMPADJUST_RAX_RCX_RDX =2511,
-  XED_IFORM_ROL_GPR8i8_CL_APX =2512, +  XED_IFORM_RMPUPDATE_RAX_RCX =2512,
-  XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX =2513, +  XED_IFORM_ROL_GPR8_CL =2513,
-  XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX =2514, +  XED_IFORM_ROL_GPR8_IMMb =2514,
-  XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX =2515, +  XED_IFORM_ROL_GPR8_ONE =2515,
-  XED_IFORM_ROL_GPR8i8_IMM8_APX =2516, +  XED_IFORM_ROL_GPR8i8_CL_APX =2516,
-  XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX =2517, +  XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX =2517,
-  XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX =2518, +  XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX =2518,
-  XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX =2519, +  XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX =2519,
-  XED_IFORM_ROL_GPR8i8_ONE_APX =2520, +  XED_IFORM_ROL_GPR8i8_IMM8_APX =2520,
-  XED_IFORM_ROL_GPRv_CL =2521, +  XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX =2521,
-  XED_IFORM_ROL_GPRv_CL_APX =2522, +  XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX =2522,
-  XED_IFORM_ROL_GPRv_GPRv_CL_APX =2523, +  XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX =2523,
-  XED_IFORM_ROL_GPRv_GPRv_IMM8_APX =2524, +  XED_IFORM_ROL_GPR8i8_ONE_APX =2524,
-  XED_IFORM_ROL_GPRv_GPRv_ONE_APX =2525, +  XED_IFORM_ROL_GPRv_CL =2525,
-  XED_IFORM_ROL_GPRv_IMM8_APX =2526, +  XED_IFORM_ROL_GPRv_CL_APX =2526,
-  XED_IFORM_ROL_GPRv_IMMb =2527, +  XED_IFORM_ROL_GPRv_GPRv_CL_APX =2527,
-  XED_IFORM_ROL_GPRv_MEMv_CL_APX =2528, +  XED_IFORM_ROL_GPRv_GPRv_IMM8_APX =2528,
-  XED_IFORM_ROL_GPRv_MEMv_IMM8_APX =2529, +  XED_IFORM_ROL_GPRv_GPRv_ONE_APX =2529,
-  XED_IFORM_ROL_GPRv_MEMv_ONE_APX =2530, +  XED_IFORM_ROL_GPRv_IMM8_APX =2530,
-  XED_IFORM_ROL_GPRv_ONE =2531, +  XED_IFORM_ROL_GPRv_IMMb =2531,
-  XED_IFORM_ROL_GPRv_ONE_APX =2532, +  XED_IFORM_ROL_GPRv_MEMv_CL_APX =2532,
-  XED_IFORM_ROL_MEMb_CL =2533, +  XED_IFORM_ROL_GPRv_MEMv_IMM8_APX =2533,
-  XED_IFORM_ROL_MEMb_IMMb =2534, +  XED_IFORM_ROL_GPRv_MEMv_ONE_APX =2534,
-  XED_IFORM_ROL_MEMb_ONE =2535, +  XED_IFORM_ROL_GPRv_ONE =2535,
-  XED_IFORM_ROL_MEMi8_CL_APX =2536, +  XED_IFORM_ROL_GPRv_ONE_APX =2536,
-  XED_IFORM_ROL_MEMi8_IMM8_APX =2537, +  XED_IFORM_ROL_MEMb_CL =2537,
-  XED_IFORM_ROL_MEMi8_ONE_APX =2538, +  XED_IFORM_ROL_MEMb_IMMb =2538,
-  XED_IFORM_ROL_MEMv_CL =2539, +  XED_IFORM_ROL_MEMb_ONE =2539,
-  XED_IFORM_ROL_MEMv_CL_APX =2540, +  XED_IFORM_ROL_MEMi8_CL_APX =2540,
-  XED_IFORM_ROL_MEMv_IMM8_APX =2541, +  XED_IFORM_ROL_MEMi8_IMM8_APX =2541,
-  XED_IFORM_ROL_MEMv_IMMb =2542, +  XED_IFORM_ROL_MEMi8_ONE_APX =2542,
-  XED_IFORM_ROL_MEMv_ONE =2543, +  XED_IFORM_ROL_MEMv_CL =2543,
-  XED_IFORM_ROL_MEMv_ONE_APX =2544, +  XED_IFORM_ROL_MEMv_CL_APX =2544,
-  XED_IFORM_ROR_GPR8_CL =2545, +  XED_IFORM_ROL_MEMv_IMM8_APX =2545,
-  XED_IFORM_ROR_GPR8_IMMb =2546, +  XED_IFORM_ROL_MEMv_IMMb =2546,
-  XED_IFORM_ROR_GPR8_ONE =2547, +  XED_IFORM_ROL_MEMv_ONE =2547,
-  XED_IFORM_ROR_GPR8i8_CL_APX =2548, +  XED_IFORM_ROL_MEMv_ONE_APX =2548,
-  XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX =2549, +  XED_IFORM_ROR_GPR8_CL =2549,
-  XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX =2550, +  XED_IFORM_ROR_GPR8_IMMb =2550,
-  XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX =2551, +  XED_IFORM_ROR_GPR8_ONE =2551,
-  XED_IFORM_ROR_GPR8i8_IMM8_APX =2552, +  XED_IFORM_ROR_GPR8i8_CL_APX =2552,
-  XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX =2553, +  XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX =2553,
-  XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX =2554, +  XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX =2554,
-  XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX =2555, +  XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX =2555,
-  XED_IFORM_ROR_GPR8i8_ONE_APX =2556, +  XED_IFORM_ROR_GPR8i8_IMM8_APX =2556,
-  XED_IFORM_ROR_GPRv_CL =2557, +  XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX =2557,
-  XED_IFORM_ROR_GPRv_CL_APX =2558, +  XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX =2558,
-  XED_IFORM_ROR_GPRv_GPRv_CL_APX =2559, +  XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX =2559,
-  XED_IFORM_ROR_GPRv_GPRv_IMM8_APX =2560, +  XED_IFORM_ROR_GPR8i8_ONE_APX =2560,
-  XED_IFORM_ROR_GPRv_GPRv_ONE_APX =2561, +  XED_IFORM_ROR_GPRv_CL =2561,
-  XED_IFORM_ROR_GPRv_IMM8_APX =2562, +  XED_IFORM_ROR_GPRv_CL_APX =2562,
-  XED_IFORM_ROR_GPRv_IMMb =2563, +  XED_IFORM_ROR_GPRv_GPRv_CL_APX =2563,
-  XED_IFORM_ROR_GPRv_MEMv_CL_APX =2564, +  XED_IFORM_ROR_GPRv_GPRv_IMM8_APX =2564,
-  XED_IFORM_ROR_GPRv_MEMv_IMM8_APX =2565, +  XED_IFORM_ROR_GPRv_GPRv_ONE_APX =2565,
-  XED_IFORM_ROR_GPRv_MEMv_ONE_APX =2566, +  XED_IFORM_ROR_GPRv_IMM8_APX =2566,
-  XED_IFORM_ROR_GPRv_ONE =2567, +  XED_IFORM_ROR_GPRv_IMMb =2567,
-  XED_IFORM_ROR_GPRv_ONE_APX =2568, +  XED_IFORM_ROR_GPRv_MEMv_CL_APX =2568,
-  XED_IFORM_ROR_MEMb_CL =2569, +  XED_IFORM_ROR_GPRv_MEMv_IMM8_APX =2569,
-  XED_IFORM_ROR_MEMb_IMMb =2570, +  XED_IFORM_ROR_GPRv_MEMv_ONE_APX =2570,
-  XED_IFORM_ROR_MEMb_ONE =2571, +  XED_IFORM_ROR_GPRv_ONE =2571,
-  XED_IFORM_ROR_MEMi8_CL_APX =2572, +  XED_IFORM_ROR_GPRv_ONE_APX =2572,
-  XED_IFORM_ROR_MEMi8_IMM8_APX =2573, +  XED_IFORM_ROR_MEMb_CL =2573,
-  XED_IFORM_ROR_MEMi8_ONE_APX =2574, +  XED_IFORM_ROR_MEMb_IMMb =2574,
-  XED_IFORM_ROR_MEMv_CL =2575, +  XED_IFORM_ROR_MEMb_ONE =2575,
-  XED_IFORM_ROR_MEMv_CL_APX =2576, +  XED_IFORM_ROR_MEMi8_CL_APX =2576,
-  XED_IFORM_ROR_MEMv_IMM8_APX =2577, +  XED_IFORM_ROR_MEMi8_IMM8_APX =2577,
-  XED_IFORM_ROR_MEMv_IMMb =2578, +  XED_IFORM_ROR_MEMi8_ONE_APX =2578,
-  XED_IFORM_ROR_MEMv_ONE =2579, +  XED_IFORM_ROR_MEMv_CL =2579,
-  XED_IFORM_ROR_MEMv_ONE_APX =2580, +  XED_IFORM_ROR_MEMv_CL_APX =2580,
-  XED_IFORM_RORX_GPR32d_GPR32d_IMMb =2581, +  XED_IFORM_ROR_MEMv_IMM8_APX =2581,
-  XED_IFORM_RORX_GPR32d_MEMd_IMMb =2582, +  XED_IFORM_ROR_MEMv_IMMb =2582,
-  XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX =2583, +  XED_IFORM_ROR_MEMv_ONE =2583,
-  XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX =2584, +  XED_IFORM_ROR_MEMv_ONE_APX =2584,
-  XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX =2585, +  XED_IFORM_RORX_GPR32d_GPR32d_IMMb =2585,
-  XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX =2586, +  XED_IFORM_RORX_GPR32d_MEMd_IMMb =2586,
-  XED_IFORM_RORX_GPR64q_GPR64q_IMMb =2587, +  XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX =2587,
-  XED_IFORM_RORX_GPR64q_MEMq_IMMb =2588, +  XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX =2588,
-  XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb =2589, +  XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX =2589,
-  XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb =2590, +  XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX =2590,
-  XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb =2591, +  XED_IFORM_RORX_GPR64q_GPR64q_IMMb =2591,
-  XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb =2592, +  XED_IFORM_RORX_GPR64q_MEMq_IMMb =2592,
-  XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb =2593, +  XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb =2593,
-  XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb =2594, +  XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb =2594,
-  XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb =2595, +  XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb =2595,
-  XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb =2596, +  XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb =2596,
-  XED_IFORM_RSM =2597, +  XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb =2597,
-  XED_IFORM_RSQRTPS_XMMps_MEMps =2598, +  XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb =2598,
-  XED_IFORM_RSQRTPS_XMMps_XMMps =2599, +  XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb =2599,
-  XED_IFORM_RSQRTSS_XMMss_MEMss =2600, +  XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb =2600,
-  XED_IFORM_RSQRTSS_XMMss_XMMss =2601, +  XED_IFORM_RSM =2601,
-  XED_IFORM_RSTORSSP_MEMu64 =2602, +  XED_IFORM_RSQRTPS_XMMps_MEMps =2602,
-  XED_IFORM_SAHF =2603, +  XED_IFORM_RSQRTPS_XMMps_XMMps =2603,
-  XED_IFORM_SALC =2604, +  XED_IFORM_RSQRTSS_XMMss_MEMss =2604,
-  XED_IFORM_SAR_GPR8_CL =2605, +  XED_IFORM_RSQRTSS_XMMss_XMMss =2605,
-  XED_IFORM_SAR_GPR8_IMMb =2606, +  XED_IFORM_RSTORSSP_MEMu64 =2606,
-  XED_IFORM_SAR_GPR8_ONE =2607, +  XED_IFORM_SAHF =2607,
-  XED_IFORM_SAR_GPR8i8_CL_APX =2608, +  XED_IFORM_SALC =2608,
-  XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX =2609, +  XED_IFORM_SAR_GPR8_CL =2609,
-  XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX =2610, +  XED_IFORM_SAR_GPR8_IMMb =2610,
-  XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX =2611, +  XED_IFORM_SAR_GPR8_ONE =2611,
-  XED_IFORM_SAR_GPR8i8_IMM8_APX =2612, +  XED_IFORM_SAR_GPR8i8_CL_APX =2612,
-  XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX =2613, +  XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX =2613,
-  XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX =2614, +  XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX =2614,
-  XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX =2615, +  XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX =2615,
-  XED_IFORM_SAR_GPR8i8_ONE_APX =2616, +  XED_IFORM_SAR_GPR8i8_IMM8_APX =2616,
-  XED_IFORM_SAR_GPRv_CL =2617, +  XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX =2617,
-  XED_IFORM_SAR_GPRv_CL_APX =2618, +  XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX =2618,
-  XED_IFORM_SAR_GPRv_GPRv_CL_APX =2619, +  XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX =2619,
-  XED_IFORM_SAR_GPRv_GPRv_IMM8_APX =2620, +  XED_IFORM_SAR_GPR8i8_ONE_APX =2620,
-  XED_IFORM_SAR_GPRv_GPRv_ONE_APX =2621, +  XED_IFORM_SAR_GPRv_CL =2621,
-  XED_IFORM_SAR_GPRv_IMM8_APX =2622, +  XED_IFORM_SAR_GPRv_CL_APX =2622,
-  XED_IFORM_SAR_GPRv_IMMb =2623, +  XED_IFORM_SAR_GPRv_GPRv_CL_APX =2623,
-  XED_IFORM_SAR_GPRv_MEMv_CL_APX =2624, +  XED_IFORM_SAR_GPRv_GPRv_IMM8_APX =2624,
-  XED_IFORM_SAR_GPRv_MEMv_IMM8_APX =2625, +  XED_IFORM_SAR_GPRv_GPRv_ONE_APX =2625,
-  XED_IFORM_SAR_GPRv_MEMv_ONE_APX =2626, +  XED_IFORM_SAR_GPRv_IMM8_APX =2626,
-  XED_IFORM_SAR_GPRv_ONE =2627, +  XED_IFORM_SAR_GPRv_IMMb =2627,
-  XED_IFORM_SAR_GPRv_ONE_APX =2628, +  XED_IFORM_SAR_GPRv_MEMv_CL_APX =2628,
-  XED_IFORM_SAR_MEMb_CL =2629, +  XED_IFORM_SAR_GPRv_MEMv_IMM8_APX =2629,
-  XED_IFORM_SAR_MEMb_IMMb =2630, +  XED_IFORM_SAR_GPRv_MEMv_ONE_APX =2630,
-  XED_IFORM_SAR_MEMb_ONE =2631, +  XED_IFORM_SAR_GPRv_ONE =2631,
-  XED_IFORM_SAR_MEMi8_CL_APX =2632, +  XED_IFORM_SAR_GPRv_ONE_APX =2632,
-  XED_IFORM_SAR_MEMi8_IMM8_APX =2633, +  XED_IFORM_SAR_MEMb_CL =2633,
-  XED_IFORM_SAR_MEMi8_ONE_APX =2634, +  XED_IFORM_SAR_MEMb_IMMb =2634,
-  XED_IFORM_SAR_MEMv_CL =2635, +  XED_IFORM_SAR_MEMb_ONE =2635,
-  XED_IFORM_SAR_MEMv_CL_APX =2636, +  XED_IFORM_SAR_MEMi8_CL_APX =2636,
-  XED_IFORM_SAR_MEMv_IMM8_APX =2637, +  XED_IFORM_SAR_MEMi8_IMM8_APX =2637,
-  XED_IFORM_SAR_MEMv_IMMb =2638, +  XED_IFORM_SAR_MEMi8_ONE_APX =2638,
-  XED_IFORM_SAR_MEMv_ONE =2639, +  XED_IFORM_SAR_MEMv_CL =2639,
-  XED_IFORM_SAR_MEMv_ONE_APX =2640, +  XED_IFORM_SAR_MEMv_CL_APX =2640,
-  XED_IFORM_SARX_GPR32d_GPR32d_GPR32d =2641, +  XED_IFORM_SAR_MEMv_IMM8_APX =2641,
-  XED_IFORM_SARX_GPR32d_MEMd_GPR32d =2642, +  XED_IFORM_SAR_MEMv_IMMb =2642,
-  XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX =2643, +  XED_IFORM_SAR_MEMv_ONE =2643,
-  XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX =2644, +  XED_IFORM_SAR_MEMv_ONE_APX =2644,
-  XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX =2645, +  XED_IFORM_SARX_GPR32d_GPR32d_GPR32d =2645,
-  XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX =2646, +  XED_IFORM_SARX_GPR32d_MEMd_GPR32d =2646,
-  XED_IFORM_SARX_GPR64q_GPR64q_GPR64q =2647, +  XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX =2647,
-  XED_IFORM_SARX_GPR64q_MEMq_GPR64q =2648, +  XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX =2648,
-  XED_IFORM_SAVEPREVSSP =2649, +  XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX =2649,
-  XED_IFORM_SBB_AL_IMMb =2650, +  XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX =2650,
-  XED_IFORM_SBB_GPR8_GPR8_18 =2651, +  XED_IFORM_SARX_GPR64q_GPR64q_GPR64q =2651,
-  XED_IFORM_SBB_GPR8_GPR8_1A =2652, +  XED_IFORM_SARX_GPR64q_MEMq_GPR64q =2652,
-  XED_IFORM_SBB_GPR8_IMMb_80r3 =2653, +  XED_IFORM_SAVEPREVSSP =2653,
-  XED_IFORM_SBB_GPR8_IMMb_82r3 =2654, +  XED_IFORM_SBB_AL_IMMb =2654,
-  XED_IFORM_SBB_GPR8_MEMb =2655, +  XED_IFORM_SBB_GPR8_GPR8_18 =2655,
-  XED_IFORM_SBB_GPR8i8_GPR8i8_APX =2656, +  XED_IFORM_SBB_GPR8_GPR8_1A =2656,
-  XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX =2657, +  XED_IFORM_SBB_GPR8_IMMb_80r3 =2657,
-  XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX =2658, +  XED_IFORM_SBB_GPR8_IMMb_82r3 =2658,
-  XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX =2659, +  XED_IFORM_SBB_GPR8_MEMb =2659,
-  XED_IFORM_SBB_GPR8i8_IMM8_APX =2660, +  XED_IFORM_SBB_GPR8i8_GPR8i8_APX =2660,
-  XED_IFORM_SBB_GPR8i8_MEMi8_APX =2661, +  XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX =2661,
-  XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX =2662, +  XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX =2662,
-  XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX =2663, +  XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX =2663,
-  XED_IFORM_SBB_GPRv_GPRv_19 =2664, +  XED_IFORM_SBB_GPR8i8_IMM8_APX =2664,
-  XED_IFORM_SBB_GPRv_GPRv_1B =2665, +  XED_IFORM_SBB_GPR8i8_MEMi8_APX =2665,
-  XED_IFORM_SBB_GPRv_GPRv_APX =2666, +  XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX =2666,
-  XED_IFORM_SBB_GPRv_GPRv_GPRv_APX =2667, +  XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX =2667,
-  XED_IFORM_SBB_GPRv_GPRv_IMM8_APX =2668, +  XED_IFORM_SBB_GPRv_GPRv_19 =2668,
-  XED_IFORM_SBB_GPRv_GPRv_IMMz_APX =2669, +  XED_IFORM_SBB_GPRv_GPRv_1B =2669,
-  XED_IFORM_SBB_GPRv_GPRv_MEMv_APX =2670, +  XED_IFORM_SBB_GPRv_GPRv_APX =2670,
-  XED_IFORM_SBB_GPRv_IMM8_APX =2671, +  XED_IFORM_SBB_GPRv_GPRv_GPRv_APX =2671,
-  XED_IFORM_SBB_GPRv_IMMb =2672, +  XED_IFORM_SBB_GPRv_GPRv_IMM8_APX =2672,
-  XED_IFORM_SBB_GPRv_IMMz =2673, +  XED_IFORM_SBB_GPRv_GPRv_IMMz_APX =2673,
-  XED_IFORM_SBB_GPRv_IMMz_APX =2674, +  XED_IFORM_SBB_GPRv_GPRv_MEMv_APX =2674,
-  XED_IFORM_SBB_GPRv_MEMv =2675, +  XED_IFORM_SBB_GPRv_IMM8_APX =2675,
-  XED_IFORM_SBB_GPRv_MEMv_APX =2676, +  XED_IFORM_SBB_GPRv_IMMb =2676,
-  XED_IFORM_SBB_GPRv_MEMv_GPRv_APX =2677, +  XED_IFORM_SBB_GPRv_IMMz =2677,
-  XED_IFORM_SBB_GPRv_MEMv_IMM8_APX =2678, +  XED_IFORM_SBB_GPRv_IMMz_APX =2678,
-  XED_IFORM_SBB_GPRv_MEMv_IMMz_APX =2679, +  XED_IFORM_SBB_GPRv_MEMv =2679,
-  XED_IFORM_SBB_MEMb_GPR8 =2680, +  XED_IFORM_SBB_GPRv_MEMv_APX =2680,
-  XED_IFORM_SBB_MEMb_IMMb_80r3 =2681, +  XED_IFORM_SBB_GPRv_MEMv_GPRv_APX =2681,
-  XED_IFORM_SBB_MEMb_IMMb_82r3 =2682, +  XED_IFORM_SBB_GPRv_MEMv_IMM8_APX =2682,
-  XED_IFORM_SBB_MEMi8_GPR8i8_APX =2683, +  XED_IFORM_SBB_GPRv_MEMv_IMMz_APX =2683,
-  XED_IFORM_SBB_MEMi8_IMM8_APX =2684, +  XED_IFORM_SBB_MEMb_GPR8 =2684,
-  XED_IFORM_SBB_MEMv_GPRv =2685, +  XED_IFORM_SBB_MEMb_IMMb_80r3 =2685,
-  XED_IFORM_SBB_MEMv_GPRv_APX =2686, +  XED_IFORM_SBB_MEMb_IMMb_82r3 =2686,
-  XED_IFORM_SBB_MEMv_IMM8_APX =2687, +  XED_IFORM_SBB_MEMi8_GPR8i8_APX =2687,
-  XED_IFORM_SBB_MEMv_IMMb =2688, +  XED_IFORM_SBB_MEMi8_IMM8_APX =2688,
-  XED_IFORM_SBB_MEMv_IMMz =2689, +  XED_IFORM_SBB_MEMv_GPRv =2689,
-  XED_IFORM_SBB_MEMv_IMMz_APX =2690, +  XED_IFORM_SBB_MEMv_GPRv_APX =2690,
-  XED_IFORM_SBB_OrAX_IMMz =2691, +  XED_IFORM_SBB_MEMv_IMM8_APX =2691,
-  XED_IFORM_SBB_LOCK_MEMb_GPR8 =2692, +  XED_IFORM_SBB_MEMv_IMMb =2692,
-  XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 =2693, +  XED_IFORM_SBB_MEMv_IMMz =2693,
-  XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 =2694, +  XED_IFORM_SBB_MEMv_IMMz_APX =2694,
-  XED_IFORM_SBB_LOCK_MEMv_GPRv =2695, +  XED_IFORM_SBB_OrAX_IMMz =2695,
-  XED_IFORM_SBB_LOCK_MEMv_IMMb =2696, +  XED_IFORM_SBB_LOCK_MEMb_GPR8 =2696,
-  XED_IFORM_SBB_LOCK_MEMv_IMMz =2697, +  XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 =2697,
-  XED_IFORM_SCASB =2698, +  XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 =2698,
-  XED_IFORM_SCASD =2699, +  XED_IFORM_SBB_LOCK_MEMv_GPRv =2699,
-  XED_IFORM_SCASQ =2700, +  XED_IFORM_SBB_LOCK_MEMv_IMMb =2700,
-  XED_IFORM_SCASW =2701, +  XED_IFORM_SBB_LOCK_MEMv_IMMz =2701,
-  XED_IFORM_SEAMCALL =2702, +  XED_IFORM_SCASB =2702,
-  XED_IFORM_SEAMOPS =2703, +  XED_IFORM_SCASD =2703,
-  XED_IFORM_SEAMRET =2704, +  XED_IFORM_SCASQ =2704,
-  XED_IFORM_SENDUIPI_GPR64u32 =2705, +  XED_IFORM_SCASW =2705,
-  XED_IFORM_SERIALIZE =2706, +  XED_IFORM_SEAMCALL =2706,
-  XED_IFORM_SETB_GPR8 =2707, +  XED_IFORM_SEAMOPS =2707,
-  XED_IFORM_SETB_GPR8i8_APX =2708, +  XED_IFORM_SEAMRET =2708,
-  XED_IFORM_SETB_GPR8i8_APX_ZU =2709, +  XED_IFORM_SENDUIPI_GPR64u32 =2709,
-  XED_IFORM_SETB_MEMb =2710, +  XED_IFORM_SERIALIZE =2710,
-  XED_IFORM_SETB_MEMi8_APX =2711, +  XED_IFORM_SETB_GPR8 =2711,
-  XED_IFORM_SETB_MEMi8_APX_ZU =2712, +  XED_IFORM_SETB_GPR8i8_APX =2712,
-  XED_IFORM_SETBE_GPR8 =2713, +  XED_IFORM_SETB_GPR8i8_APX_ZU =2713,
-  XED_IFORM_SETBE_GPR8i8_APX =2714, +  XED_IFORM_SETB_MEMb =2714,
-  XED_IFORM_SETBE_GPR8i8_APX_ZU =2715, +  XED_IFORM_SETB_MEMi8_APX =2715,
-  XED_IFORM_SETBE_MEMb =2716, +  XED_IFORM_SETB_MEMi8_APX_ZU =2716,
-  XED_IFORM_SETBE_MEMi8_APX =2717, +  XED_IFORM_SETBE_GPR8 =2717,
-  XED_IFORM_SETBE_MEMi8_APX_ZU =2718, +  XED_IFORM_SETBE_GPR8i8_APX =2718,
-  XED_IFORM_SETL_GPR8 =2719, +  XED_IFORM_SETBE_GPR8i8_APX_ZU =2719,
-  XED_IFORM_SETL_GPR8i8_APX =2720, +  XED_IFORM_SETBE_MEMb =2720,
-  XED_IFORM_SETL_GPR8i8_APX_ZU =2721, +  XED_IFORM_SETBE_MEMi8_APX =2721,
-  XED_IFORM_SETL_MEMb =2722, +  XED_IFORM_SETBE_MEMi8_APX_ZU =2722,
-  XED_IFORM_SETL_MEMi8_APX =2723, +  XED_IFORM_SETL_GPR8 =2723,
-  XED_IFORM_SETL_MEMi8_APX_ZU =2724, +  XED_IFORM_SETL_GPR8i8_APX =2724,
-  XED_IFORM_SETLE_GPR8 =2725, +  XED_IFORM_SETL_GPR8i8_APX_ZU =2725,
-  XED_IFORM_SETLE_GPR8i8_APX =2726, +  XED_IFORM_SETL_MEMb =2726,
-  XED_IFORM_SETLE_GPR8i8_APX_ZU =2727, +  XED_IFORM_SETL_MEMi8_APX =2727,
-  XED_IFORM_SETLE_MEMb =2728, +  XED_IFORM_SETL_MEMi8_APX_ZU =2728,
-  XED_IFORM_SETLE_MEMi8_APX =2729, +  XED_IFORM_SETLE_GPR8 =2729,
-  XED_IFORM_SETLE_MEMi8_APX_ZU =2730, +  XED_IFORM_SETLE_GPR8i8_APX =2730,
-  XED_IFORM_SETNB_GPR8 =2731, +  XED_IFORM_SETLE_GPR8i8_APX_ZU =2731,
-  XED_IFORM_SETNB_GPR8i8_APX =2732, +  XED_IFORM_SETLE_MEMb =2732,
-  XED_IFORM_SETNB_GPR8i8_APX_ZU =2733, +  XED_IFORM_SETLE_MEMi8_APX =2733,
-  XED_IFORM_SETNB_MEMb =2734, +  XED_IFORM_SETLE_MEMi8_APX_ZU =2734,
-  XED_IFORM_SETNB_MEMi8_APX =2735, +  XED_IFORM_SETNB_GPR8 =2735,
-  XED_IFORM_SETNB_MEMi8_APX_ZU =2736, +  XED_IFORM_SETNB_GPR8i8_APX =2736,
-  XED_IFORM_SETNBE_GPR8 =2737, +  XED_IFORM_SETNB_GPR8i8_APX_ZU =2737,
-  XED_IFORM_SETNBE_GPR8i8_APX =2738, +  XED_IFORM_SETNB_MEMb =2738,
-  XED_IFORM_SETNBE_GPR8i8_APX_ZU =2739, +  XED_IFORM_SETNB_MEMi8_APX =2739,
-  XED_IFORM_SETNBE_MEMb =2740, +  XED_IFORM_SETNB_MEMi8_APX_ZU =2740,
-  XED_IFORM_SETNBE_MEMi8_APX =2741, +  XED_IFORM_SETNBE_GPR8 =2741,
-  XED_IFORM_SETNBE_MEMi8_APX_ZU =2742, +  XED_IFORM_SETNBE_GPR8i8_APX =2742,
-  XED_IFORM_SETNL_GPR8 =2743, +  XED_IFORM_SETNBE_GPR8i8_APX_ZU =2743,
-  XED_IFORM_SETNL_GPR8i8_APX =2744, +  XED_IFORM_SETNBE_MEMb =2744,
-  XED_IFORM_SETNL_GPR8i8_APX_ZU =2745, +  XED_IFORM_SETNBE_MEMi8_APX =2745,
-  XED_IFORM_SETNL_MEMb =2746, +  XED_IFORM_SETNBE_MEMi8_APX_ZU =2746,
-  XED_IFORM_SETNL_MEMi8_APX =2747, +  XED_IFORM_SETNL_GPR8 =2747,
-  XED_IFORM_SETNL_MEMi8_APX_ZU =2748, +  XED_IFORM_SETNL_GPR8i8_APX =2748,
-  XED_IFORM_SETNLE_GPR8 =2749, +  XED_IFORM_SETNL_GPR8i8_APX_ZU =2749,
-  XED_IFORM_SETNLE_GPR8i8_APX =2750, +  XED_IFORM_SETNL_MEMb =2750,
-  XED_IFORM_SETNLE_GPR8i8_APX_ZU =2751, +  XED_IFORM_SETNL_MEMi8_APX =2751,
-  XED_IFORM_SETNLE_MEMb =2752, +  XED_IFORM_SETNL_MEMi8_APX_ZU =2752,
-  XED_IFORM_SETNLE_MEMi8_APX =2753, +  XED_IFORM_SETNLE_GPR8 =2753,
-  XED_IFORM_SETNLE_MEMi8_APX_ZU =2754, +  XED_IFORM_SETNLE_GPR8i8_APX =2754,
-  XED_IFORM_SETNO_GPR8 =2755, +  XED_IFORM_SETNLE_GPR8i8_APX_ZU =2755,
-  XED_IFORM_SETNO_GPR8i8_APX =2756, +  XED_IFORM_SETNLE_MEMb =2756,
-  XED_IFORM_SETNO_GPR8i8_APX_ZU =2757, +  XED_IFORM_SETNLE_MEMi8_APX =2757,
-  XED_IFORM_SETNO_MEMb =2758, +  XED_IFORM_SETNLE_MEMi8_APX_ZU =2758,
-  XED_IFORM_SETNO_MEMi8_APX =2759, +  XED_IFORM_SETNO_GPR8 =2759,
-  XED_IFORM_SETNO_MEMi8_APX_ZU =2760, +  XED_IFORM_SETNO_GPR8i8_APX =2760,
-  XED_IFORM_SETNP_GPR8 =2761, +  XED_IFORM_SETNO_GPR8i8_APX_ZU =2761,
-  XED_IFORM_SETNP_GPR8i8_APX =2762, +  XED_IFORM_SETNO_MEMb =2762,
-  XED_IFORM_SETNP_GPR8i8_APX_ZU =2763, +  XED_IFORM_SETNO_MEMi8_APX =2763,
-  XED_IFORM_SETNP_MEMb =2764, +  XED_IFORM_SETNO_MEMi8_APX_ZU =2764,
-  XED_IFORM_SETNP_MEMi8_APX =2765, +  XED_IFORM_SETNP_GPR8 =2765,
-  XED_IFORM_SETNP_MEMi8_APX_ZU =2766, +  XED_IFORM_SETNP_GPR8i8_APX =2766,
-  XED_IFORM_SETNS_GPR8 =2767, +  XED_IFORM_SETNP_GPR8i8_APX_ZU =2767,
-  XED_IFORM_SETNS_GPR8i8_APX =2768, +  XED_IFORM_SETNP_MEMb =2768,
-  XED_IFORM_SETNS_GPR8i8_APX_ZU =2769, +  XED_IFORM_SETNP_MEMi8_APX =2769,
-  XED_IFORM_SETNS_MEMb =2770, +  XED_IFORM_SETNP_MEMi8_APX_ZU =2770,
-  XED_IFORM_SETNS_MEMi8_APX =2771, +  XED_IFORM_SETNS_GPR8 =2771,
-  XED_IFORM_SETNS_MEMi8_APX_ZU =2772, +  XED_IFORM_SETNS_GPR8i8_APX =2772,
-  XED_IFORM_SETNZ_GPR8 =2773, +  XED_IFORM_SETNS_GPR8i8_APX_ZU =2773,
-  XED_IFORM_SETNZ_GPR8i8_APX =2774, +  XED_IFORM_SETNS_MEMb =2774,
-  XED_IFORM_SETNZ_GPR8i8_APX_ZU =2775, +  XED_IFORM_SETNS_MEMi8_APX =2775,
-  XED_IFORM_SETNZ_MEMb =2776, +  XED_IFORM_SETNS_MEMi8_APX_ZU =2776,
-  XED_IFORM_SETNZ_MEMi8_APX =2777, +  XED_IFORM_SETNZ_GPR8 =2777,
-  XED_IFORM_SETNZ_MEMi8_APX_ZU =2778, +  XED_IFORM_SETNZ_GPR8i8_APX =2778,
-  XED_IFORM_SETO_GPR8 =2779, +  XED_IFORM_SETNZ_GPR8i8_APX_ZU =2779,
-  XED_IFORM_SETO_GPR8i8_APX =2780, +  XED_IFORM_SETNZ_MEMb =2780,
-  XED_IFORM_SETO_GPR8i8_APX_ZU =2781, +  XED_IFORM_SETNZ_MEMi8_APX =2781,
-  XED_IFORM_SETO_MEMb =2782, +  XED_IFORM_SETNZ_MEMi8_APX_ZU =2782,
-  XED_IFORM_SETO_MEMi8_APX =2783, +  XED_IFORM_SETO_GPR8 =2783,
-  XED_IFORM_SETO_MEMi8_APX_ZU =2784, +  XED_IFORM_SETO_GPR8i8_APX =2784,
-  XED_IFORM_SETP_GPR8 =2785, +  XED_IFORM_SETO_GPR8i8_APX_ZU =2785,
-  XED_IFORM_SETP_GPR8i8_APX =2786, +  XED_IFORM_SETO_MEMb =2786,
-  XED_IFORM_SETP_GPR8i8_APX_ZU =2787, +  XED_IFORM_SETO_MEMi8_APX =2787,
-  XED_IFORM_SETP_MEMb =2788, +  XED_IFORM_SETO_MEMi8_APX_ZU =2788,
-  XED_IFORM_SETP_MEMi8_APX =2789, +  XED_IFORM_SETP_GPR8 =2789,
-  XED_IFORM_SETP_MEMi8_APX_ZU =2790, +  XED_IFORM_SETP_GPR8i8_APX =2790,
-  XED_IFORM_SETS_GPR8 =2791, +  XED_IFORM_SETP_GPR8i8_APX_ZU =2791,
-  XED_IFORM_SETS_GPR8i8_APX =2792, +  XED_IFORM_SETP_MEMb =2792,
-  XED_IFORM_SETS_GPR8i8_APX_ZU =2793, +  XED_IFORM_SETP_MEMi8_APX =2793,
-  XED_IFORM_SETS_MEMb =2794, +  XED_IFORM_SETP_MEMi8_APX_ZU =2794,
-  XED_IFORM_SETS_MEMi8_APX =2795, +  XED_IFORM_SETS_GPR8 =2795,
-  XED_IFORM_SETS_MEMi8_APX_ZU =2796, +  XED_IFORM_SETS_GPR8i8_APX =2796,
-  XED_IFORM_SETSSBSY =2797, +  XED_IFORM_SETS_GPR8i8_APX_ZU =2797,
-  XED_IFORM_SETZ_GPR8 =2798, +  XED_IFORM_SETS_MEMb =2798,
-  XED_IFORM_SETZ_GPR8i8_APX =2799, +  XED_IFORM_SETS_MEMi8_APX =2799,
-  XED_IFORM_SETZ_GPR8i8_APX_ZU =2800, +  XED_IFORM_SETS_MEMi8_APX_ZU =2800,
-  XED_IFORM_SETZ_MEMb =2801, +  XED_IFORM_SETSSBSY =2801,
-  XED_IFORM_SETZ_MEMi8_APX =2802, +  XED_IFORM_SETZ_GPR8 =2802,
-  XED_IFORM_SETZ_MEMi8_APX_ZU =2803, +  XED_IFORM_SETZ_GPR8i8_APX =2803,
-  XED_IFORM_SFENCE =2804, +  XED_IFORM_SETZ_GPR8i8_APX_ZU =2804,
-  XED_IFORM_SGDT_MEMs =2805, +  XED_IFORM_SETZ_MEMb =2805,
-  XED_IFORM_SGDT_MEMs64 =2806, +  XED_IFORM_SETZ_MEMi8_APX =2806,
-  XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA =2807, +  XED_IFORM_SETZ_MEMi8_APX_ZU =2807,
-  XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA =2808, +  XED_IFORM_SFENCE =2808,
-  XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA =2809, +  XED_IFORM_SGDT_MEMs =2809,
-  XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA =2810, +  XED_IFORM_SGDT_MEMs64 =2810,
-  XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA =2811, +  XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA =2811,
-  XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA =2812, +  XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA =2812,
-  XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA =2813, +  XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA =2813,
-  XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA =2814, +  XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA =2814,
-  XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA =2815, +  XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA =2815,
-  XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA =2816, +  XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA =2816,
-  XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA =2817, +  XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA =2817,
-  XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA =2818, +  XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA =2818,
-  XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA =2819, +  XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA =2819,
-  XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA =2820, +  XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA =2820,
-  XED_IFORM_SHL_GPR8_CL_D2r4 =2821, +  XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA =2821,
-  XED_IFORM_SHL_GPR8_CL_D2r6 =2822, +  XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA =2822,
-  XED_IFORM_SHL_GPR8_IMMb_C0r4 =2823, +  XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA =2823,
-  XED_IFORM_SHL_GPR8_IMMb_C0r6 =2824, +  XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA =2824,
-  XED_IFORM_SHL_GPR8_ONE_D0r4 =2825, +  XED_IFORM_SHL_GPR8_CL_D2r4 =2825,
-  XED_IFORM_SHL_GPR8_ONE_D0r6 =2826, +  XED_IFORM_SHL_GPR8_CL_D2r6 =2826,
-  XED_IFORM_SHL_GPR8i8_CL_APX =2827, +  XED_IFORM_SHL_GPR8_IMMb_C0r4 =2827,
-  XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX =2828, +  XED_IFORM_SHL_GPR8_IMMb_C0r6 =2828,
-  XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX =2829, +  XED_IFORM_SHL_GPR8_ONE_D0r4 =2829,
-  XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX =2830, +  XED_IFORM_SHL_GPR8_ONE_D0r6 =2830,
-  XED_IFORM_SHL_GPR8i8_IMM8_APX =2831, +  XED_IFORM_SHL_GPR8i8_CL_APX =2831,
-  XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX =2832, +  XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX =2832,
-  XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX =2833, +  XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX =2833,
-  XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX =2834, +  XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX =2834,
-  XED_IFORM_SHL_GPR8i8_ONE_APX =2835, +  XED_IFORM_SHL_GPR8i8_IMM8_APX =2835,
-  XED_IFORM_SHL_GPRv_CL_APX =2836, +  XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX =2836,
-  XED_IFORM_SHL_GPRv_CL_D3r4 =2837, +  XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX =2837,
-  XED_IFORM_SHL_GPRv_CL_D3r6 =2838, +  XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX =2838,
-  XED_IFORM_SHL_GPRv_GPRv_CL_APX =2839, +  XED_IFORM_SHL_GPR8i8_ONE_APX =2839,
-  XED_IFORM_SHL_GPRv_GPRv_IMM8_APX =2840, +  XED_IFORM_SHL_GPRv_CL_APX =2840,
-  XED_IFORM_SHL_GPRv_GPRv_ONE_APX =2841, +  XED_IFORM_SHL_GPRv_CL_D3r4 =2841,
-  XED_IFORM_SHL_GPRv_IMM8_APX =2842, +  XED_IFORM_SHL_GPRv_CL_D3r6 =2842,
-  XED_IFORM_SHL_GPRv_IMMb_C1r4 =2843, +  XED_IFORM_SHL_GPRv_GPRv_CL_APX =2843,
-  XED_IFORM_SHL_GPRv_IMMb_C1r6 =2844, +  XED_IFORM_SHL_GPRv_GPRv_IMM8_APX =2844,
-  XED_IFORM_SHL_GPRv_MEMv_CL_APX =2845, +  XED_IFORM_SHL_GPRv_GPRv_ONE_APX =2845,
-  XED_IFORM_SHL_GPRv_MEMv_IMM8_APX =2846, +  XED_IFORM_SHL_GPRv_IMM8_APX =2846,
-  XED_IFORM_SHL_GPRv_MEMv_ONE_APX =2847, +  XED_IFORM_SHL_GPRv_IMMb_C1r4 =2847,
-  XED_IFORM_SHL_GPRv_ONE_APX =2848, +  XED_IFORM_SHL_GPRv_IMMb_C1r6 =2848,
-  XED_IFORM_SHL_GPRv_ONE_D1r4 =2849, +  XED_IFORM_SHL_GPRv_MEMv_CL_APX =2849,
-  XED_IFORM_SHL_GPRv_ONE_D1r6 =2850, +  XED_IFORM_SHL_GPRv_MEMv_IMM8_APX =2850,
-  XED_IFORM_SHL_MEMb_CL_D2r4 =2851, +  XED_IFORM_SHL_GPRv_MEMv_ONE_APX =2851,
-  XED_IFORM_SHL_MEMb_CL_D2r6 =2852, +  XED_IFORM_SHL_GPRv_ONE_APX =2852,
-  XED_IFORM_SHL_MEMb_IMMb_C0r4 =2853, +  XED_IFORM_SHL_GPRv_ONE_D1r4 =2853,
-  XED_IFORM_SHL_MEMb_IMMb_C0r6 =2854, +  XED_IFORM_SHL_GPRv_ONE_D1r6 =2854,
-  XED_IFORM_SHL_MEMb_ONE_D0r4 =2855, +  XED_IFORM_SHL_MEMb_CL_D2r4 =2855,
-  XED_IFORM_SHL_MEMb_ONE_D0r6 =2856, +  XED_IFORM_SHL_MEMb_CL_D2r6 =2856,
-  XED_IFORM_SHL_MEMi8_CL_APX =2857, +  XED_IFORM_SHL_MEMb_IMMb_C0r4 =2857,
-  XED_IFORM_SHL_MEMi8_IMM8_APX =2858, +  XED_IFORM_SHL_MEMb_IMMb_C0r6 =2858,
-  XED_IFORM_SHL_MEMi8_ONE_APX =2859, +  XED_IFORM_SHL_MEMb_ONE_D0r4 =2859,
-  XED_IFORM_SHL_MEMv_CL_APX =2860, +  XED_IFORM_SHL_MEMb_ONE_D0r6 =2860,
-  XED_IFORM_SHL_MEMv_CL_D3r4 =2861, +  XED_IFORM_SHL_MEMi8_CL_APX =2861,
-  XED_IFORM_SHL_MEMv_CL_D3r6 =2862, +  XED_IFORM_SHL_MEMi8_IMM8_APX =2862,
-  XED_IFORM_SHL_MEMv_IMM8_APX =2863, +  XED_IFORM_SHL_MEMi8_ONE_APX =2863,
-  XED_IFORM_SHL_MEMv_IMMb_C1r4 =2864, +  XED_IFORM_SHL_MEMv_CL_APX =2864,
-  XED_IFORM_SHL_MEMv_IMMb_C1r6 =2865, +  XED_IFORM_SHL_MEMv_CL_D3r4 =2865,
-  XED_IFORM_SHL_MEMv_ONE_APX =2866, +  XED_IFORM_SHL_MEMv_CL_D3r6 =2866,
-  XED_IFORM_SHL_MEMv_ONE_D1r4 =2867, +  XED_IFORM_SHL_MEMv_IMM8_APX =2867,
-  XED_IFORM_SHL_MEMv_ONE_D1r6 =2868, +  XED_IFORM_SHL_MEMv_IMMb_C1r4 =2868,
-  XED_IFORM_SHLD_GPRv_GPRv_CL =2869, +  XED_IFORM_SHL_MEMv_IMMb_C1r6 =2869,
-  XED_IFORM_SHLD_GPRv_GPRv_CL_APX =2870, +  XED_IFORM_SHL_MEMv_ONE_APX =2870,
-  XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX =2871, +  XED_IFORM_SHL_MEMv_ONE_D1r4 =2871,
-  XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX =2872, +  XED_IFORM_SHL_MEMv_ONE_D1r6 =2872,
-  XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX =2873, +  XED_IFORM_SHLD_GPRv_GPRv_CL =2873,
-  XED_IFORM_SHLD_GPRv_GPRv_IMMb =2874, +  XED_IFORM_SHLD_GPRv_GPRv_CL_APX =2874,
-  XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX =2875, +  XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX =2875,
-  XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX =2876, +  XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX =2876,
-  XED_IFORM_SHLD_MEMv_GPRv_CL =2877, +  XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX =2877,
-  XED_IFORM_SHLD_MEMv_GPRv_CL_APX =2878, +  XED_IFORM_SHLD_GPRv_GPRv_IMMb =2878,
-  XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX =2879, +  XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX =2879,
-  XED_IFORM_SHLD_MEMv_GPRv_IMMb =2880, +  XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX =2880,
-  XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d =2881, +  XED_IFORM_SHLD_MEMv_GPRv_CL =2881,
-  XED_IFORM_SHLX_GPR32d_MEMd_GPR32d =2882, +  XED_IFORM_SHLD_MEMv_GPRv_CL_APX =2882,
-  XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX =2883, +  XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX =2883,
-  XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX =2884, +  XED_IFORM_SHLD_MEMv_GPRv_IMMb =2884,
-  XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX =2885, +  XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d =2885,
-  XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX =2886, +  XED_IFORM_SHLX_GPR32d_MEMd_GPR32d =2886,
-  XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q =2887, +  XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX =2887,
-  XED_IFORM_SHLX_GPR64q_MEMq_GPR64q =2888, +  XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX =2888,
-  XED_IFORM_SHR_GPR8_CL =2889, +  XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX =2889,
-  XED_IFORM_SHR_GPR8_IMMb =2890, +  XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX =2890,
-  XED_IFORM_SHR_GPR8_ONE =2891, +  XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q =2891,
-  XED_IFORM_SHR_GPR8i8_CL_APX =2892, +  XED_IFORM_SHLX_GPR64q_MEMq_GPR64q =2892,
-  XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX =2893, +  XED_IFORM_SHR_GPR8_CL =2893,
-  XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX =2894, +  XED_IFORM_SHR_GPR8_IMMb =2894,
-  XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX =2895, +  XED_IFORM_SHR_GPR8_ONE =2895,
-  XED_IFORM_SHR_GPR8i8_IMM8_APX =2896, +  XED_IFORM_SHR_GPR8i8_CL_APX =2896,
-  XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX =2897, +  XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX =2897,
-  XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX =2898, +  XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX =2898,
-  XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX =2899, +  XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX =2899,
-  XED_IFORM_SHR_GPR8i8_ONE_APX =2900, +  XED_IFORM_SHR_GPR8i8_IMM8_APX =2900,
-  XED_IFORM_SHR_GPRv_CL =2901, +  XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX =2901,
-  XED_IFORM_SHR_GPRv_CL_APX =2902, +  XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX =2902,
-  XED_IFORM_SHR_GPRv_GPRv_CL_APX =2903, +  XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX =2903,
-  XED_IFORM_SHR_GPRv_GPRv_IMM8_APX =2904, +  XED_IFORM_SHR_GPR8i8_ONE_APX =2904,
-  XED_IFORM_SHR_GPRv_GPRv_ONE_APX =2905, +  XED_IFORM_SHR_GPRv_CL =2905,
-  XED_IFORM_SHR_GPRv_IMM8_APX =2906, +  XED_IFORM_SHR_GPRv_CL_APX =2906,
-  XED_IFORM_SHR_GPRv_IMMb =2907, +  XED_IFORM_SHR_GPRv_GPRv_CL_APX =2907,
-  XED_IFORM_SHR_GPRv_MEMv_CL_APX =2908, +  XED_IFORM_SHR_GPRv_GPRv_IMM8_APX =2908,
-  XED_IFORM_SHR_GPRv_MEMv_IMM8_APX =2909, +  XED_IFORM_SHR_GPRv_GPRv_ONE_APX =2909,
-  XED_IFORM_SHR_GPRv_MEMv_ONE_APX =2910, +  XED_IFORM_SHR_GPRv_IMM8_APX =2910,
-  XED_IFORM_SHR_GPRv_ONE =2911, +  XED_IFORM_SHR_GPRv_IMMb =2911,
-  XED_IFORM_SHR_GPRv_ONE_APX =2912, +  XED_IFORM_SHR_GPRv_MEMv_CL_APX =2912,
-  XED_IFORM_SHR_MEMb_CL =2913, +  XED_IFORM_SHR_GPRv_MEMv_IMM8_APX =2913,
-  XED_IFORM_SHR_MEMb_IMMb =2914, +  XED_IFORM_SHR_GPRv_MEMv_ONE_APX =2914,
-  XED_IFORM_SHR_MEMb_ONE =2915, +  XED_IFORM_SHR_GPRv_ONE =2915,
-  XED_IFORM_SHR_MEMi8_CL_APX =2916, +  XED_IFORM_SHR_GPRv_ONE_APX =2916,
-  XED_IFORM_SHR_MEMi8_IMM8_APX =2917, +  XED_IFORM_SHR_MEMb_CL =2917,
-  XED_IFORM_SHR_MEMi8_ONE_APX =2918, +  XED_IFORM_SHR_MEMb_IMMb =2918,
-  XED_IFORM_SHR_MEMv_CL =2919, +  XED_IFORM_SHR_MEMb_ONE =2919,
-  XED_IFORM_SHR_MEMv_CL_APX =2920, +  XED_IFORM_SHR_MEMi8_CL_APX =2920,
-  XED_IFORM_SHR_MEMv_IMM8_APX =2921, +  XED_IFORM_SHR_MEMi8_IMM8_APX =2921,
-  XED_IFORM_SHR_MEMv_IMMb =2922, +  XED_IFORM_SHR_MEMi8_ONE_APX =2922,
-  XED_IFORM_SHR_MEMv_ONE =2923, +  XED_IFORM_SHR_MEMv_CL =2923,
-  XED_IFORM_SHR_MEMv_ONE_APX =2924, +  XED_IFORM_SHR_MEMv_CL_APX =2924,
-  XED_IFORM_SHRD_GPRv_GPRv_CL =2925, +  XED_IFORM_SHR_MEMv_IMM8_APX =2925,
-  XED_IFORM_SHRD_GPRv_GPRv_CL_APX =2926, +  XED_IFORM_SHR_MEMv_IMMb =2926,
-  XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX =2927, +  XED_IFORM_SHR_MEMv_ONE =2927,
-  XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX =2928, +  XED_IFORM_SHR_MEMv_ONE_APX =2928,
-  XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX =2929, +  XED_IFORM_SHRD_GPRv_GPRv_CL =2929,
-  XED_IFORM_SHRD_GPRv_GPRv_IMMb =2930, +  XED_IFORM_SHRD_GPRv_GPRv_CL_APX =2930,
-  XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX =2931, +  XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX =2931,
-  XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX =2932, +  XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX =2932,
-  XED_IFORM_SHRD_MEMv_GPRv_CL =2933, +  XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX =2933,
-  XED_IFORM_SHRD_MEMv_GPRv_CL_APX =2934, +  XED_IFORM_SHRD_GPRv_GPRv_IMMb =2934,
-  XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX =2935, +  XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX =2935,
-  XED_IFORM_SHRD_MEMv_GPRv_IMMb =2936, +  XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX =2936,
-  XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d =2937, +  XED_IFORM_SHRD_MEMv_GPRv_CL =2937,
-  XED_IFORM_SHRX_GPR32d_MEMd_GPR32d =2938, +  XED_IFORM_SHRD_MEMv_GPRv_CL_APX =2938,
-  XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX =2939, +  XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX =2939,
-  XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX =2940, +  XED_IFORM_SHRD_MEMv_GPRv_IMMb =2940,
-  XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX =2941, +  XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d =2941,
-  XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX =2942, +  XED_IFORM_SHRX_GPR32d_MEMd_GPR32d =2942,
-  XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q =2943, +  XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX =2943,
-  XED_IFORM_SHRX_GPR64q_MEMq_GPR64q =2944, +  XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX =2944,
-  XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb =2945, +  XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX =2945,
-  XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb =2946, +  XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX =2946,
-  XED_IFORM_SHUFPS_XMMps_MEMps_IMMb =2947, +  XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q =2947,
-  XED_IFORM_SHUFPS_XMMps_XMMps_IMMb =2948, +  XED_IFORM_SHRX_GPR64q_MEMq_GPR64q =2948,
-  XED_IFORM_SIDT_MEMs =2949, +  XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb =2949,
-  XED_IFORM_SIDT_MEMs64 =2950, +  XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb =2950,
-  XED_IFORM_SKINIT_EAX =2951, +  XED_IFORM_SHUFPS_XMMps_MEMps_IMMb =2951,
-  XED_IFORM_SLDT_GPRv =2952, +  XED_IFORM_SHUFPS_XMMps_XMMps_IMMb =2952,
-  XED_IFORM_SLDT_MEMw =2953, +  XED_IFORM_SIDT_MEMs =2953,
-  XED_IFORM_SLWPCB_GPRyy =2954, +  XED_IFORM_SIDT_MEMs64 =2954,
-  XED_IFORM_SMSW_GPRv =2955, +  XED_IFORM_SKINIT_EAX =2955,
-  XED_IFORM_SMSW_MEMw =2956, +  XED_IFORM_SLDT_GPRv =2956,
-  XED_IFORM_SQRTPD_XMMpd_MEMpd =2957, +  XED_IFORM_SLDT_MEMw =2957,
-  XED_IFORM_SQRTPD_XMMpd_XMMpd =2958, +  XED_IFORM_SLWPCB_GPRyy =2958,
-  XED_IFORM_SQRTPS_XMMps_MEMps =2959, +  XED_IFORM_SMSW_GPRv =2959,
-  XED_IFORM_SQRTPS_XMMps_XMMps =2960, +  XED_IFORM_SMSW_MEMw =2960,
-  XED_IFORM_SQRTSD_XMMsd_MEMsd =2961, +  XED_IFORM_SQRTPD_XMMpd_MEMpd =2961,
-  XED_IFORM_SQRTSD_XMMsd_XMMsd =2962, +  XED_IFORM_SQRTPD_XMMpd_XMMpd =2962,
-  XED_IFORM_SQRTSS_XMMss_MEMss =2963, +  XED_IFORM_SQRTPS_XMMps_MEMps =2963,
-  XED_IFORM_SQRTSS_XMMss_XMMss =2964, +  XED_IFORM_SQRTPS_XMMps_XMMps =2964,
-  XED_IFORM_STAC =2965, +  XED_IFORM_SQRTSD_XMMsd_MEMsd =2965,
-  XED_IFORM_STC =2966, +  XED_IFORM_SQRTSD_XMMsd_XMMsd =2966,
-  XED_IFORM_STD =2967, +  XED_IFORM_SQRTSS_XMMss_MEMss =2967,
-  XED_IFORM_STGI =2968, +  XED_IFORM_SQRTSS_XMMss_XMMss =2968,
-  XED_IFORM_STI =2969, +  XED_IFORM_STAC =2969,
-  XED_IFORM_STMXCSR_MEMd =2970, +  XED_IFORM_STC =2970,
-  XED_IFORM_STOSB =2971, +  XED_IFORM_STD =2971,
-  XED_IFORM_STOSD =2972, +  XED_IFORM_STGI =2972,
-  XED_IFORM_STOSQ =2973, +  XED_IFORM_STI =2973,
-  XED_IFORM_STOSW =2974, +  XED_IFORM_STMXCSR_MEMd =2974,
-  XED_IFORM_STR_GPRv =2975, +  XED_IFORM_STOSB =2975,
-  XED_IFORM_STR_MEMw =2976, +  XED_IFORM_STOSD =2976,
-  XED_IFORM_STTILECFG_MEM =2977, +  XED_IFORM_STOSQ =2977,
-  XED_IFORM_STTILECFG_MEM_APX =2978, +  XED_IFORM_STOSW =2978,
-  XED_IFORM_STUI =2979, +  XED_IFORM_STR_GPRv =2979,
-  XED_IFORM_SUB_AL_IMMb =2980, +  XED_IFORM_STR_MEMw =2980,
-  XED_IFORM_SUB_GPR8_GPR8_28 =2981, +  XED_IFORM_STTILECFG_MEM =2981,
-  XED_IFORM_SUB_GPR8_GPR8_2A =2982, +  XED_IFORM_STTILECFG_MEM_APX =2982,
-  XED_IFORM_SUB_GPR8_IMMb_80r5 =2983, +  XED_IFORM_STUI =2983,
-  XED_IFORM_SUB_GPR8_IMMb_82r5 =2984, +  XED_IFORM_SUB_AL_IMMb =2984,
-  XED_IFORM_SUB_GPR8_MEMb =2985, +  XED_IFORM_SUB_GPR8_GPR8_28 =2985,
-  XED_IFORM_SUB_GPR8i8_GPR8i8_APX =2986, +  XED_IFORM_SUB_GPR8_GPR8_2A =2986,
-  XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX =2987, +  XED_IFORM_SUB_GPR8_IMMb_80r5 =2987,
-  XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX =2988, +  XED_IFORM_SUB_GPR8_IMMb_82r5 =2988,
-  XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX =2989, +  XED_IFORM_SUB_GPR8_MEMb =2989,
-  XED_IFORM_SUB_GPR8i8_IMM8_APX =2990, +  XED_IFORM_SUB_GPR8i8_GPR8i8_APX =2990,
-  XED_IFORM_SUB_GPR8i8_MEMi8_APX =2991, +  XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX =2991,
-  XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX =2992, +  XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX =2992,
-  XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX =2993, +  XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX =2993,
-  XED_IFORM_SUB_GPRv_GPRv_29 =2994, +  XED_IFORM_SUB_GPR8i8_IMM8_APX =2994,
-  XED_IFORM_SUB_GPRv_GPRv_2B =2995, +  XED_IFORM_SUB_GPR8i8_MEMi8_APX =2995,
-  XED_IFORM_SUB_GPRv_GPRv_APX =2996, +  XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX =2996,
-  XED_IFORM_SUB_GPRv_GPRv_GPRv_APX =2997, +  XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX =2997,
-  XED_IFORM_SUB_GPRv_GPRv_IMM8_APX =2998, +  XED_IFORM_SUB_GPRv_GPRv_29 =2998,
-  XED_IFORM_SUB_GPRv_GPRv_IMMz_APX =2999, +  XED_IFORM_SUB_GPRv_GPRv_2B =2999,
-  XED_IFORM_SUB_GPRv_GPRv_MEMv_APX =3000, +  XED_IFORM_SUB_GPRv_GPRv_APX =3000,
-  XED_IFORM_SUB_GPRv_IMM8_APX =3001, +  XED_IFORM_SUB_GPRv_GPRv_GPRv_APX =3001,
-  XED_IFORM_SUB_GPRv_IMMb =3002, +  XED_IFORM_SUB_GPRv_GPRv_IMM8_APX =3002,
-  XED_IFORM_SUB_GPRv_IMMz =3003, +  XED_IFORM_SUB_GPRv_GPRv_IMMz_APX =3003,
-  XED_IFORM_SUB_GPRv_IMMz_APX =3004, +  XED_IFORM_SUB_GPRv_GPRv_MEMv_APX =3004,
-  XED_IFORM_SUB_GPRv_MEMv =3005, +  XED_IFORM_SUB_GPRv_IMM8_APX =3005,
-  XED_IFORM_SUB_GPRv_MEMv_APX =3006, +  XED_IFORM_SUB_GPRv_IMMb =3006,
-  XED_IFORM_SUB_GPRv_MEMv_GPRv_APX =3007, +  XED_IFORM_SUB_GPRv_IMMz =3007,
-  XED_IFORM_SUB_GPRv_MEMv_IMM8_APX =3008, +  XED_IFORM_SUB_GPRv_IMMz_APX =3008,
-  XED_IFORM_SUB_GPRv_MEMv_IMMz_APX =3009, +  XED_IFORM_SUB_GPRv_MEMv =3009,
-  XED_IFORM_SUB_MEMb_GPR8 =3010, +  XED_IFORM_SUB_GPRv_MEMv_APX =3010,
-  XED_IFORM_SUB_MEMb_IMMb_80r5 =3011, +  XED_IFORM_SUB_GPRv_MEMv_GPRv_APX =3011,
-  XED_IFORM_SUB_MEMb_IMMb_82r5 =3012, +  XED_IFORM_SUB_GPRv_MEMv_IMM8_APX =3012,
-  XED_IFORM_SUB_MEMi8_GPR8i8_APX =3013, +  XED_IFORM_SUB_GPRv_MEMv_IMMz_APX =3013,
-  XED_IFORM_SUB_MEMi8_IMM8_APX =3014, +  XED_IFORM_SUB_MEMb_GPR8 =3014,
-  XED_IFORM_SUB_MEMv_GPRv =3015, +  XED_IFORM_SUB_MEMb_IMMb_80r5 =3015,
-  XED_IFORM_SUB_MEMv_GPRv_APX =3016, +  XED_IFORM_SUB_MEMb_IMMb_82r5 =3016,
-  XED_IFORM_SUB_MEMv_IMM8_APX =3017, +  XED_IFORM_SUB_MEMi8_GPR8i8_APX =3017,
-  XED_IFORM_SUB_MEMv_IMMb =3018, +  XED_IFORM_SUB_MEMi8_IMM8_APX =3018,
-  XED_IFORM_SUB_MEMv_IMMz =3019, +  XED_IFORM_SUB_MEMv_GPRv =3019,
-  XED_IFORM_SUB_MEMv_IMMz_APX =3020, +  XED_IFORM_SUB_MEMv_GPRv_APX =3020,
-  XED_IFORM_SUB_OrAX_IMMz =3021, +  XED_IFORM_SUB_MEMv_IMM8_APX =3021,
-  XED_IFORM_SUBPD_XMMpd_MEMpd =3022, +  XED_IFORM_SUB_MEMv_IMMb =3022,
-  XED_IFORM_SUBPD_XMMpd_XMMpd =3023, +  XED_IFORM_SUB_MEMv_IMMz =3023,
-  XED_IFORM_SUBPS_XMMps_MEMps =3024, +  XED_IFORM_SUB_MEMv_IMMz_APX =3024,
-  XED_IFORM_SUBPS_XMMps_XMMps =3025, +  XED_IFORM_SUB_OrAX_IMMz =3025,
-  XED_IFORM_SUBSD_XMMsd_MEMsd =3026, +  XED_IFORM_SUBPD_XMMpd_MEMpd =3026,
-  XED_IFORM_SUBSD_XMMsd_XMMsd =3027, +  XED_IFORM_SUBPD_XMMpd_XMMpd =3027,
-  XED_IFORM_SUBSS_XMMss_MEMss =3028, +  XED_IFORM_SUBPS_XMMps_MEMps =3028,
-  XED_IFORM_SUBSS_XMMss_XMMss =3029, +  XED_IFORM_SUBPS_XMMps_XMMps =3029,
-  XED_IFORM_SUB_LOCK_MEMb_GPR8 =3030, +  XED_IFORM_SUBSD_XMMsd_MEMsd =3030,
-  XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 =3031, +  XED_IFORM_SUBSD_XMMsd_XMMsd =3031,
-  XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 =3032, +  XED_IFORM_SUBSS_XMMss_MEMss =3032,
-  XED_IFORM_SUB_LOCK_MEMv_GPRv =3033, +  XED_IFORM_SUBSS_XMMss_XMMss =3033,
-  XED_IFORM_SUB_LOCK_MEMv_IMMb =3034, +  XED_IFORM_SUB_LOCK_MEMb_GPR8 =3034,
-  XED_IFORM_SUB_LOCK_MEMv_IMMz =3035, +  XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 =3035,
-  XED_IFORM_SWAPGS =3036, +  XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 =3036,
-  XED_IFORM_SYSCALL =3037, +  XED_IFORM_SUB_LOCK_MEMv_GPRv =3037,
-  XED_IFORM_SYSCALL_32 =3038, +  XED_IFORM_SUB_LOCK_MEMv_IMMb =3038,
-  XED_IFORM_SYSENTER =3039, +  XED_IFORM_SUB_LOCK_MEMv_IMMz =3039,
-  XED_IFORM_SYSEXIT =3040, +  XED_IFORM_SWAPGS =3040,
-  XED_IFORM_SYSRET =3041, +  XED_IFORM_SYSCALL =3041,
-  XED_IFORM_SYSRET64 =3042, +  XED_IFORM_SYSCALL_32 =3042,
-  XED_IFORM_SYSRET_AMD =3043, +  XED_IFORM_SYSENTER =3043,
-  XED_IFORM_T1MSKC_GPR32d_GPR32d =3044, +  XED_IFORM_SYSEXIT =3044,
-  XED_IFORM_T1MSKC_GPR32d_MEMd =3045, +  XED_IFORM_SYSRET =3045,
-  XED_IFORM_T1MSKC_GPRyy_GPRyy =3046, +  XED_IFORM_SYSRET64 =3046,
-  XED_IFORM_T1MSKC_GPRyy_MEMy =3047, +  XED_IFORM_SYSRET_AMD =3047,
-  XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3048, +  XED_IFORM_T1MSKC_GPR32d_GPR32d =3048,
-  XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 =3049, +  XED_IFORM_T1MSKC_GPR32d_MEMd =3049,
-  XED_IFORM_TDCALL =3050, +  XED_IFORM_T1MSKC_GPRyy_GPRyy =3050,
-  XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 =3051, +  XED_IFORM_T1MSKC_GPRyy_MEMy =3051,
-  XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8 =3052, +  XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16 =3052,
-  XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8 =3053, +  XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16 =3053,
-  XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8 =3054, +  XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16 =3054,
-  XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8 =3055, +  XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16 =3055,
-  XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16 =3056, +  XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16 =3056,
-  XED_IFORM_TEST_AL_IMMb =3057, +  XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16 =3057,
-  XED_IFORM_TEST_GPR8_GPR8 =3058, +  XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16 =3058,
-  XED_IFORM_TEST_GPR8_IMMb_F6r0 =3059, +  XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16 =3059,
-  XED_IFORM_TEST_GPR8_IMMb_F6r1 =3060, +  XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3060,
-  XED_IFORM_TEST_GPRv_GPRv =3061, +  XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 =3061,
-  XED_IFORM_TEST_GPRv_IMMz_F7r0 =3062, +  XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3062,
-  XED_IFORM_TEST_GPRv_IMMz_F7r1 =3063, +  XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16 =3063,
-  XED_IFORM_TEST_MEMb_GPR8 =3064, +  XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32 =3064,
-  XED_IFORM_TEST_MEMb_IMMb_F6r0 =3065, +  XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8 =3065,
-  XED_IFORM_TEST_MEMb_IMMb_F6r1 =3066, +  XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32 =3066,
-  XED_IFORM_TEST_MEMv_GPRv =3067, +  XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8 =3067,
-  XED_IFORM_TEST_MEMv_IMMz_F7r0 =3068, +  XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32 =3068,
-  XED_IFORM_TEST_MEMv_IMMz_F7r1 =3069, +  XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8 =3069,
-  XED_IFORM_TEST_OrAX_IMMz =3070, +  XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32 =3070,
-  XED_IFORM_TESTUI =3071, +  XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8 =3071,
-  XED_IFORM_TILELOADD_TMMu32_MEMu32 =3072, +  XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32 =3072,
-  XED_IFORM_TILELOADD_TMMu32_MEMu32_APX =3073, +  XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8 =3073,
-  XED_IFORM_TILELOADDT1_TMMu32_MEMu32 =3074, +  XED_IFORM_TDCALL =3074,
-  XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX =3075, +  XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 =3075,
-  XED_IFORM_TILERELEASE =3076, +  XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8 =3076,
-  XED_IFORM_TILESTORED_MEMu32_TMMu32 =3077, +  XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8 =3077,
-  XED_IFORM_TILESTORED_MEMu32_TMMu32_APX =3078, +  XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8 =3078,
-  XED_IFORM_TILEZERO_TMMu32 =3079, +  XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8 =3079,
-  XED_IFORM_TLBSYNC =3080, +  XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8 =3080,
-  XED_IFORM_TPAUSE_GPR32u32 =3081, +  XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8 =3081,
-  XED_IFORM_TZCNT_GPRv_GPRv =3082, +  XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16 =3082,
-  XED_IFORM_TZCNT_GPRv_GPRv_APX =3083, +  XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8 =3083,
-  XED_IFORM_TZCNT_GPRv_MEMv =3084, +  XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8 =3084,
-  XED_IFORM_TZCNT_GPRv_MEMv_APX =3085, +  XED_IFORM_TEST_AL_IMMb =3085,
-  XED_IFORM_TZMSK_GPR32d_GPR32d =3086, +  XED_IFORM_TEST_GPR8_GPR8 =3086,
-  XED_IFORM_TZMSK_GPR32d_MEMd =3087, +  XED_IFORM_TEST_GPR8_IMMb_F6r0 =3087,
-  XED_IFORM_TZMSK_GPRyy_GPRyy =3088, +  XED_IFORM_TEST_GPR8_IMMb_F6r1 =3088,
-  XED_IFORM_TZMSK_GPRyy_MEMy =3089, +  XED_IFORM_TEST_GPRv_GPRv =3089,
-  XED_IFORM_UCOMISD_XMMsd_MEMsd =3090, +  XED_IFORM_TEST_GPRv_IMMz_F7r0 =3090,
-  XED_IFORM_UCOMISD_XMMsd_XMMsd =3091, +  XED_IFORM_TEST_GPRv_IMMz_F7r1 =3091,
-  XED_IFORM_UCOMISS_XMMss_MEMss =3092, +  XED_IFORM_TEST_MEMb_GPR8 =3092,
-  XED_IFORM_UCOMISS_XMMss_XMMss =3093, +  XED_IFORM_TEST_MEMb_IMMb_F6r0 =3093,
-  XED_IFORM_UD0 =3094, +  XED_IFORM_TEST_MEMb_IMMb_F6r1 =3094,
-  XED_IFORM_UD0_GPR32_GPR32 =3095, +  XED_IFORM_TEST_MEMv_GPRv =3095,
-  XED_IFORM_UD0_GPR32_MEMd =3096, +  XED_IFORM_TEST_MEMv_IMMz_F7r0 =3096,
-  XED_IFORM_UD1_GPR32_GPR32 =3097, +  XED_IFORM_TEST_MEMv_IMMz_F7r1 =3097,
-  XED_IFORM_UD1_GPR32_MEMd =3098, +  XED_IFORM_TEST_OrAX_IMMz =3098,
-  XED_IFORM_UD2 =3099, +  XED_IFORM_TESTUI =3099,
-  XED_IFORM_UIRET =3100, +  XED_IFORM_TILELOADD_TMMu32_MEMu32 =3100,
-  XED_IFORM_UMONITOR_GPRa =3101, +  XED_IFORM_TILELOADD_TMMu32_MEMu32_APX =3101,
-  XED_IFORM_UMWAIT_GPR32 =3102, +  XED_IFORM_TILELOADDRS_TMMu32_MEMu32 =3102,
-  XED_IFORM_UNPCKHPD_XMMpd_MEMdq =3103, +  XED_IFORM_TILELOADDRST1_TMMu32_MEMu32 =3103,
-  XED_IFORM_UNPCKHPD_XMMpd_XMMq =3104, +  XED_IFORM_TILELOADDT1_TMMu32_MEMu32 =3104,
-  XED_IFORM_UNPCKHPS_XMMps_MEMdq =3105, +  XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX =3105,
-  XED_IFORM_UNPCKHPS_XMMps_XMMdq =3106, +  XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32 =3106,
-  XED_IFORM_UNPCKLPD_XMMpd_MEMdq =3107, +  XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8 =3107,
-  XED_IFORM_UNPCKLPD_XMMpd_XMMq =3108, +  XED_IFORM_TILERELEASE =3108,
-  XED_IFORM_UNPCKLPS_XMMps_MEMdq =3109, +  XED_IFORM_TILESTORED_MEMu32_TMMu32 =3109,
-  XED_IFORM_UNPCKLPS_XMMps_XMMq =3110, +  XED_IFORM_TILESTORED_MEMu32_TMMu32_APX =3110,
-  XED_IFORM_URDMSR_GPR64u64_GPR64u64 =3111, +  XED_IFORM_TILEZERO_TMMu32 =3111,
-  XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX =3112, +  XED_IFORM_TLBSYNC =3112,
-  XED_IFORM_URDMSR_GPR64u64_IMM32 =3113, +  XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32 =3113,
-  XED_IFORM_URDMSR_GPR64u64_IMM32_APX =3114, +  XED_IFORM_TPAUSE_GPR32u32 =3114,
-  XED_IFORM_UWRMSR_GPR64u64_GPR64u64 =3115, +  XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3115,
-  XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX =3116, +  XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 =3116,
-  XED_IFORM_UWRMSR_IMM32_GPR64u64 =3117, +  XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16 =3117,
-  XED_IFORM_UWRMSR_IMM32_GPR64u64_APX =3118, +  XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16 =3118,
-  XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3119, +  XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32 =3119,
-  XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3120, +  XED_IFORM_TTRANSPOSED_TMMu32_TMMu32 =3120,
-  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3121, +  XED_IFORM_TZCNT_GPRv_GPRv =3121,
-  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3122, +  XED_IFORM_TZCNT_GPRv_GPRv_APX =3122,
-  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq =3123, +  XED_IFORM_TZCNT_GPRv_MEMv =3123,
-  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq =3124, +  XED_IFORM_TZCNT_GPRv_MEMv_APX =3124,
-  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3125, +  XED_IFORM_TZMSK_GPR32d_GPR32d =3125,
-  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3126, +  XED_IFORM_TZMSK_GPR32d_MEMd =3126,
-  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3127, +  XED_IFORM_TZMSK_GPRyy_GPRyy =3127,
-  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3128, +  XED_IFORM_TZMSK_GPRyy_MEMy =3128,
-  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq =3129, +  XED_IFORM_UCOMISD_XMMsd_MEMsd =3129,
-  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq =3130, +  XED_IFORM_UCOMISD_XMMsd_XMMsd =3130,
-  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3131, +  XED_IFORM_UCOMISS_XMMss_MEMss =3131,
-  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3132, +  XED_IFORM_UCOMISS_XMMss_XMMss =3132,
-  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3133, +  XED_IFORM_UD0 =3133,
-  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3134, +  XED_IFORM_UD0_GPR32_GPR32 =3134,
-  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =3135, +  XED_IFORM_UD0_GPR32_MEMd =3135,
-  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =3136, +  XED_IFORM_UD1_GPR32_GPR32 =3136,
-  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =3137, +  XED_IFORM_UD1_GPR32_MEMd =3137,
-  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =3138, +  XED_IFORM_UD2 =3138,
-  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq =3139, +  XED_IFORM_UIRET =3139,
-  XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq =3140, +  XED_IFORM_UMONITOR_GPRa =3140,
-  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3141, +  XED_IFORM_UMWAIT_GPR32 =3141,
-  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3142, +  XED_IFORM_UNPCKHPD_XMMpd_MEMdq =3142,
-  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3143, +  XED_IFORM_UNPCKHPD_XMMpd_XMMq =3143,
-  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3144, +  XED_IFORM_UNPCKHPS_XMMps_MEMdq =3144,
-  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq =3145, +  XED_IFORM_UNPCKHPS_XMMps_XMMdq =3145,
-  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq =3146, +  XED_IFORM_UNPCKLPD_XMMpd_MEMdq =3146,
-  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3147, +  XED_IFORM_UNPCKLPD_XMMpd_XMMq =3147,
-  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3148, +  XED_IFORM_UNPCKLPS_XMMps_MEMdq =3148,
-  XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq =3149, +  XED_IFORM_UNPCKLPS_XMMps_XMMq =3149,
-  XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq =3150, +  XED_IFORM_URDMSR_GPR64u64_GPR64u64 =3150,
-  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3151, +  XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX =3151,
-  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3152, +  XED_IFORM_URDMSR_GPR64u64_IMM32 =3152,
-  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3153, +  XED_IFORM_URDMSR_GPR64u64_IMM32_APX =3153,
-  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3154, +  XED_IFORM_UWRMSR_GPR64u64_GPR64u64 =3154,
-  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd =3155, +  XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX =3155,
-  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd =3156, +  XED_IFORM_UWRMSR_IMM32_GPR64u64 =3156,
-  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3157, +  XED_IFORM_UWRMSR_IMM32_GPR64u64_APX =3157,
-  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3158, +  XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3158,
-  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq =3159, +  XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3159,
-  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq =3160, +  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3160,
-  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq =3161, +  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3161,
-  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq =3162, +  XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =3162,
-  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq =3163, +  XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =3163,
-  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq =3164, +  XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =3164,
-  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq =3165, +  XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =3165,
-  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq =3166, +  XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =3166,
-  XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq =3167, +  XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =3167,
-  XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq =3168, +  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq =3168,
-  XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 =3169, +  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq =3169,
-  XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 =3170, +  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3170,
-  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 =3171, +  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3171,
-  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 =3172, +  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3172,
-  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 =3173, +  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3173,
-  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 =3174, +  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =3174,
-  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 =3175, +  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq =3175,
-  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3176, +  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq =3176,
-  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq =3177, +  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3177,
-  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq =3178, +  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3178,
-  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 =3179, +  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3179,
-  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 =3180, +  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3180,
-  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 =3181, +  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =3181,
-  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 =3182, +  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =3182,
-  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 =3183, +  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =3183,
-  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 =3184, +  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =3184,
-  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3185, +  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =3185,
-  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3186, +  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq =3186,
-  XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq =3187, +  XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq =3187,
-  XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq =3188, +  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3188,
-  XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 =3189, +  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3189,
-  XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 =3190, +  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3190,
-  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 =3191, +  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3191,
-  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 =3192, +  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =3192,
-  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 =3193, +  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq =3193,
-  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 =3194, +  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq =3194,
-  XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 =3195, +  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3195,
-  XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3196, +  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3196,
-  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq =3197, +  XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq =3197,
-  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq =3198, +  XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq =3198,
-  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 =3199, +  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3199,
-  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 =3200, +  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3200,
-  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 =3201, +  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =3201,
-  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 =3202, +  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3202,
-  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 =3203, +  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3203,
-  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 =3204, +  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =3204,
-  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3205, +  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd =3205,
-  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3206, +  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd =3206,
-  XED_IFORM_VAESIMC_XMMdq_MEMdq =3207, +  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3207,
-  XED_IFORM_VAESIMC_XMMdq_XMMdq =3208, +  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3208,
-  XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb =3209, +  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =3209,
-  XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb =3210, +  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq =3210,
-  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =3211, +  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq =3211,
-  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =3212, +  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq =3212,
-  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =3213, +  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq =3213,
-  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =3214, +  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq =3214,
-  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =3215, +  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq =3215,
-  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =3216, +  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq =3216,
-  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =3217, +  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq =3217,
-  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =3218, +  XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq =3218,
-  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =3219, +  XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq =3219,
-  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =3220, +  XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 =3220,
-  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =3221, +  XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 =3221,
-  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =3222, +  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 =3222,
-  XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq =3223, +  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 =3223,
-  XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq =3224, +  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 =3224,
-  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3225, +  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 =3225,
-  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3226, +  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 =3226,
-  XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq =3227, +  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3227,
-  XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq =3228, +  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq =3228,
-  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3229, +  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq =3229,
-  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3230, +  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 =3230,
-  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3231, +  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 =3231,
-  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3232, +  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 =3232,
-  XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq =3233, +  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 =3233,
-  XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq =3234, +  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 =3234,
-  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3235, +  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 =3235,
-  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3236, +  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3236,
-  XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq =3237, +  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3237,
-  XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq =3238, +  XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq =3238,
-  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3239, +  XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq =3239,
-  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3240, +  XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 =3240,
-  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3241, +  XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 =3241,
-  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3242, +  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 =3242,
-  XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq =3243, +  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 =3243,
-  XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq =3244, +  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 =3244,
-  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3245, +  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 =3245,
-  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3246, +  XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 =3246,
-  XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq =3247, +  XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3247,
-  XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq =3248, +  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq =3248,
-  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3249, +  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq =3249,
-  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3250, +  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 =3250,
-  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3251, +  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 =3251,
-  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3252, +  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 =3252,
-  XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq =3253, +  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 =3253,
-  XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq =3254, +  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 =3254,
-  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3255, +  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 =3255,
-  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3256, +  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3256,
-  XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq =3257, +  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3257,
-  XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq =3258, +  XED_IFORM_VAESIMC_XMMdq_MEMdq =3258,
-  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3259, +  XED_IFORM_VAESIMC_XMMdq_XMMdq =3259,
-  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3260, +  XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb =3260,
-  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3261, +  XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb =3261,
-  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3262, +  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =3262,
-  XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16 =3263, +  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =3263,
-  XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16 =3264, +  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =3264,
-  XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16 =3265, +  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =3265,
-  XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16 =3266, +  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =3266,
-  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3267, +  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =3267,
-  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3268, +  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =3268,
-  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3269, +  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =3269,
-  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3270, +  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =3270,
-  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3271, +  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =3271,
-  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3272, +  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =3272,
-  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3273, +  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =3273,
-  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3274, +  XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq =3274,
-  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3275, +  XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq =3275,
-  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3276, +  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3276,
-  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3277, +  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3277,
-  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3278, +  XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq =3278,
-  XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb =3279, +  XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq =3279,
-  XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb =3280, +  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3280,
-  XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb =3281, +  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3281,
-  XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb =3282, +  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3282,
-  XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb =3283, +  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3283,
-  XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb =3284, +  XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq =3284,
-  XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb =3285, +  XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq =3285,
-  XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb =3286, +  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3286,
-  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq =3287, +  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3287,
-  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq =3288, +  XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq =3288,
-  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq =3289, +  XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq =3289,
-  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq =3290, +  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3290,
-  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq =3291, +  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3291,
-  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq =3292, +  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3292,
-  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq =3293, +  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3293,
-  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq =3294, +  XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq =3294,
-  XED_IFORM_VBROADCASTF128_YMMqq_MEMdq =3295, +  XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq =3295,
-  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 =3296, +  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3296,
-  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 =3297, +  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3297,
-  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 =3298, +  XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq =3298,
-  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 =3299, +  XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq =3299,
-  XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 =3300, +  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3300,
-  XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 =3301, +  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3301,
-  XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 =3302, +  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3302,
-  XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 =3303, +  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3303,
-  XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 =3304, +  XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq =3304,
-  XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 =3305, +  XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq =3305,
-  XED_IFORM_VBROADCASTI128_YMMqq_MEMdq =3306, +  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3306,
-  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 =3307, +  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3307,
-  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 =3308, +  XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq =3308,
-  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 =3309, +  XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq =3309,
-  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 =3310, +  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3310,
-  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 =3311, +  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3311,
-  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 =3312, +  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3312,
-  XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 =3313, +  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3313,
-  XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 =3314, +  XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16 =3314,
-  XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 =3315, +  XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16 =3315,
-  XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 =3316, +  XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16 =3316,
-  XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 =3317, +  XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16 =3317,
-  XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 =3318, +  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3318,
-  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 =3319, +  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3319,
-  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 =3320, +  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3320,
-  XED_IFORM_VBROADCASTSD_YMMqq_MEMq =3321, +  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3321,
-  XED_IFORM_VBROADCASTSD_YMMqq_XMMdq =3322, +  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3322,
-  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 =3323, +  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3323,
-  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 =3324, +  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3324,
-  XED_IFORM_VBROADCASTSS_XMMdq_MEMd =3325, +  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3325,
-  XED_IFORM_VBROADCASTSS_XMMdq_XMMdq =3326, +  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3326,
-  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 =3327, +  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3327,
-  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 =3328, +  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3328,
-  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 =3329, +  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3329,
-  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 =3330, +  XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb =3330,
-  XED_IFORM_VBROADCASTSS_YMMqq_MEMd =3331, +  XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb =3331,
-  XED_IFORM_VBROADCASTSS_YMMqq_XMMdq =3332, +  XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb =3332,
-  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 =3333, +  XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb =3333,
-  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 =3334, +  XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb =3334,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3335, +  XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb =3335,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3336, +  XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb =3336,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =3337, +  XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb =3337,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =3338, +  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq =3338,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =3339, +  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq =3339,
-  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =3340, +  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq =3340,
-  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb =3341, +  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq =3341,
-  XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb =3342, +  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq =3342,
-  XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb =3343, +  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq =3343,
-  XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb =3344, +  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq =3344,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3345, +  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq =3345,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3346, +  XED_IFORM_VBROADCASTF128_YMMqq_MEMdq =3346,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 =3347, +  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 =3347,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 =3348, +  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 =3348,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 =3349, +  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 =3349,
-  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 =3350, +  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 =3350,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3351, +  XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 =3351,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3352, +  XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 =3352,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =3353, +  XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 =3353,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =3354, +  XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 =3354,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =3355, +  XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 =3355,
-  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =3356, +  XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 =3356,
-  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb =3357, +  XED_IFORM_VBROADCASTI128_YMMqq_MEMdq =3357,
-  XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb =3358, +  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 =3358,
-  XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb =3359, +  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 =3359,
-  XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb =3360, +  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 =3360,
-  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3361, +  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 =3361,
-  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3362, +  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 =3362,
-  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb =3363, +  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 =3363,
-  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb =3364, +  XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 =3364,
-  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3365, +  XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 =3365,
-  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3366, +  XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 =3366,
-  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3367, +  XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 =3367,
-  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3368, +  XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 =3368,
-  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb =3369, +  XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 =3369,
-  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb =3370, +  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 =3370,
-  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 =3371, +  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 =3371,
-  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 =3372, +  XED_IFORM_VBROADCASTSD_YMMqq_MEMq =3372,
-  XED_IFORM_VCOMISD_XMMq_MEMq =3373, +  XED_IFORM_VBROADCASTSD_YMMqq_XMMdq =3373,
-  XED_IFORM_VCOMISD_XMMq_XMMq =3374, +  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 =3374,
-  XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512 =3375, +  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 =3375,
-  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512 =3376, +  XED_IFORM_VBROADCASTSS_XMMdq_MEMd =3376,
-  XED_IFORM_VCOMISS_XMMd_MEMd =3377, +  XED_IFORM_VBROADCASTSS_XMMdq_XMMdq =3377,
-  XED_IFORM_VCOMISS_XMMd_XMMd =3378, +  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 =3378,
-  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 =3379, +  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 =3379,
-  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 =3380, +  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 =3380,
-  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 =3381, +  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 =3381,
-  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 =3382, +  XED_IFORM_VBROADCASTSS_YMMqq_MEMd =3382,
-  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 =3383, +  XED_IFORM_VBROADCASTSS_YMMqq_XMMdq =3383,
-  XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 =3384, +  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 =3384,
-  XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 =3385, +  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 =3385,
-  XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =3386, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 =3386,
-  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 =3387, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 =3387,
-  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 =3388, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 =3388,
-  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 =3389, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 =3389,
-  XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 =3390, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 =3390,
-  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 =3391, +  XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 =3391,
-  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =3392, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3392,
-  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq =3393, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3393,
-  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq =3394, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =3394,
-  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 =3395, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =3395,
-  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 =3396, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC =3396,
-  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 =3397, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =3397,
-  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 =3398, +  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =3398,
-  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq =3399, +  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb =3399,
-  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq =3400, +  XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb =3400,
-  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 =3401, +  XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb =3401,
-  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 =3402, +  XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb =3402,
-  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 =3403, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3403,
-  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 =3404, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3404,
-  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 =3405, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 =3405,
-  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 =3406, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 =3406,
-  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 =3407, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC =3407,
-  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 =3408, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 =3408,
-  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq =3409, +  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 =3409,
-  XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq =3410, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3410,
-  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 =3411, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3411,
-  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 =3412, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =3412,
-  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 =3413, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =3413,
-  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 =3414, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC =3414,
-  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq =3415, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =3415,
-  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq =3416, +  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =3416,
-  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 =3417, +  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb =3417,
-  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 =3418, +  XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb =3418,
-  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 =3419, +  XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb =3419,
-  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 =3420, +  XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb =3420,
-  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 =3421, +  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3421,
-  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 =3422, +  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3422,
-  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 =3423, +  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =3423,
-  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 =3424, +  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb =3424,
-  XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16 =3425, +  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb =3425,
-  XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16 =3426, +  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3426,
-  XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16 =3427, +  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3427,
-  XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16 =3428, +  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC =3428,
-  XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16 =3429, +  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3429,
-  XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16 =3430, +  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3430,
-  XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16 =3431, +  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =3431,
-  XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16 =3432, +  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb =3432,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 =3433, +  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb =3433,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 =3434, +  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 =3434,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 =3435, +  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 =3435,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 =3436, +  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC =3436,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 =3437, +  XED_IFORM_VCOMISD_XMMq_MEMq =3437,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 =3438, +  XED_IFORM_VCOMISD_XMMq_XMMq =3438,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32 =3439, +  XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512 =3439,
-  XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32 =3440, +  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512 =3440,
-  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 =3441, +  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC =3441,
-  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 =3442, +  XED_IFORM_VCOMISS_XMMd_MEMd =3442,
-  XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq =3443, +  XED_IFORM_VCOMISS_XMMd_XMMd =3443,
-  XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq =3444, +  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 =3444,
-  XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq =3445, +  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 =3445,
-  XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq =3446, +  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC =3446,
-  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3447, +  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 =3447,
-  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3448, +  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 =3448,
-  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3449, +  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 =3449,
-  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3450, +  XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 =3450,
-  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3451, +  XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 =3451,
-  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3452, +  XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =3452,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 =3453, +  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 =3453,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 =3454, +  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 =3454,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 =3455, +  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 =3455,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 =3456, +  XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 =3456,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 =3457, +  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 =3457,
-  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 =3458, +  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =3458,
-  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq =3459, +  XED_IFORM_VCOMSBF16_XMMbf16_MEMbf16_AVX512 =3459,
-  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq =3460, +  XED_IFORM_VCOMSBF16_XMMbf16_XMMbf16_AVX512 =3460,
-  XED_IFORM_VCVTPD2PS_XMMdq_XMMdq =3461, +  XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512 =3461,
-  XED_IFORM_VCVTPD2PS_XMMdq_YMMqq =3462, +  XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512 =3462,
-  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 =3463, +  XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512 =3463,
-  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 =3464, +  XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512 =3464,
-  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 =3465, +  XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512 =3465,
-  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 =3466, +  XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512 =3466,
-  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 =3467, +  XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512 =3467,
-  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 =3468, +  XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512 =3468,
-  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3469, +  XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512 =3469,
-  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3470, +  XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512 =3470,
-  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3471, +  XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512 =3471,
-  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3472, +  XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512 =3472,
-  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3473, +  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3473,
-  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3474, +  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3474,
-  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3475, +  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3475,
-  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3476, +  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3476,
-  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3477, +  XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3477,
-  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3478, +  XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3478,
-  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3479, +  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3479,
-  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3480, +  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3480,
-  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3481, +  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3481,
-  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3482, +  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3482,
-  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3483, +  XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3483,
-  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3484, +  XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3484,
-  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3485, +  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3485,
-  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3486, +  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3486,
-  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3487, +  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3487,
-  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =3488, +  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3488,
-  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =3489, +  XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3489,
-  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =3490, +  XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3490,
-  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =3491, +  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3491,
-  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =3492, +  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3492,
-  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 =3493, +  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3493,
-  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 =3494, +  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3494,
-  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 =3495, +  XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3495,
-  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 =3496, +  XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3496,
-  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 =3497, +  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq =3497,
-  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 =3498, +  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq =3498,
-  XED_IFORM_VCVTPH2PS_XMMdq_MEMq =3499, +  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 =3499,
-  XED_IFORM_VCVTPH2PS_XMMdq_XMMq =3500, +  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 =3500,
-  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 =3501, +  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 =3501,
-  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 =3502, +  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 =3502,
-  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 =3503, +  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC =3503,
-  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 =3504, +  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq =3504,
-  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq =3505, +  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq =3505,
-  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq =3506, +  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 =3506,
-  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 =3507, +  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 =3507,
-  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 =3508, +  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 =3508,
-  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 =3509, +  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 =3509,
-  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 =3510, +  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 =3510,
-  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 =3511, +  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 =3511,
-  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 =3512, +  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC =3512,
-  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 =3513, +  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 =3513,
-  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 =3514, +  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 =3514,
-  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =3515, +  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq =3515,
-  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =3516, +  XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq =3516,
-  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =3517, +  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 =3517,
-  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =3518, +  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 =3518,
-  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =3519, +  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 =3519,
-  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =3520, +  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 =3520,
-  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =3521, +  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC =3521,
-  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =3522, +  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq =3522,
-  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =3523, +  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq =3523,
-  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =3524, +  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 =3524,
-  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =3525, +  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 =3525,
-  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =3526, +  XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512 =3526,
-  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =3527, +  XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512 =3527,
-  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =3528, +  XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512 =3528,
-  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =3529, +  XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512 =3529,
-  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =3530, +  XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512 =3530,
-  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =3531, +  XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512 =3531,
-  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =3532, +  XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 =3532,
-  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =3533, +  XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 =3533,
-  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =3534, +  XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 =3534,
-  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =3535, +  XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 =3535,
-  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =3536, +  XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3536,
-  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =3537, +  XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3537,
-  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =3538, +  XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 =3538,
-  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =3539, +  XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 =3539,
-  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =3540, +  XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 =3540,
-  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =3541, +  XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 =3541,
-  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =3542, +  XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3542,
-  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =3543, +  XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3543,
-  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =3544, +  XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 =3544,
-  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq =3545, +  XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 =3545,
-  XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq =3546, +  XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 =3546,
-  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =3547, +  XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 =3547,
-  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =3548, +  XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3548,
-  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =3549, +  XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3549,
-  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =3550, +  XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 =3550,
-  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq =3551, +  XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 =3551,
-  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq =3552, +  XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 =3552,
-  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =3553, +  XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 =3553,
-  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =3554, +  XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3554,
-  XED_IFORM_VCVTPS2PD_XMMdq_MEMq =3555, +  XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3555,
-  XED_IFORM_VCVTPS2PD_XMMdq_XMMq =3556, +  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 =3556,
-  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 =3557, +  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 =3557,
-  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 =3558, +  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 =3558,
-  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 =3559, +  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 =3559,
-  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 =3560, +  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 =3560,
-  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq =3561, +  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 =3561,
-  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq =3562, +  XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 =3562,
-  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 =3563, +  XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 =3563,
-  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 =3564, +  XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 =3564,
-  XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb =3565, +  XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 =3565,
-  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 =3566, +  XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 =3566,
-  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 =3567, +  XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 =3567,
-  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3568, +  XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 =3568,
-  XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb =3569, +  XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 =3569,
-  XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb =3570, +  XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 =3570,
-  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 =3571, +  XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 =3571,
-  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 =3572, +  XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 =3572,
-  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb =3573, +  XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 =3573,
-  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3574, +  XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16 =3574,
-  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 =3575, +  XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16 =3575,
-  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 =3576, +  XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16 =3576,
-  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 =3577, +  XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16 =3577,
-  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 =3578, +  XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16 =3578,
-  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 =3579, +  XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16 =3579,
-  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 =3580, +  XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16 =3580,
-  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =3581, +  XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16 =3581,
-  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =3582, +  XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 =3582,
-  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =3583, +  XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 =3583,
-  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =3584, +  XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512 =3584,
-  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =3585, +  XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512 =3585,
-  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =3586, +  XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 =3586,
-  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =3587, +  XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512 =3587,
-  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =3588, +  XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 =3588,
-  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =3589, +  XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 =3589,
-  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =3590, +  XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512 =3590,
-  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =3591, +  XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512 =3591,
-  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =3592, +  XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 =3592,
-  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =3593, +  XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512 =3593,
-  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =3594, +  XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 =3594,
-  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =3595, +  XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 =3595,
-  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =3596, +  XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512 =3596,
-  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =3597, +  XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512 =3597,
-  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =3598, +  XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 =3598,
-  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 =3599, +  XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512 =3599,
-  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 =3600, +  XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 =3600,
-  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 =3601, +  XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 =3601,
-  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 =3602, +  XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512 =3602,
-  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 =3603, +  XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512 =3603,
-  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 =3604, +  XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 =3604,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =3605, +  XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512 =3605,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =3606, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 =3606,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =3607, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 =3607,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =3608, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 =3608,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =3609, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 =3609,
-  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =3610, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 =3610,
-  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =3611, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 =3611,
-  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =3612, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32 =3612,
-  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =3613, +  XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32 =3613,
-  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =3614, +  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 =3614,
-  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =3615, +  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 =3615,
-  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =3616, +  XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq =3616,
-  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 =3617, +  XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq =3617,
-  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 =3618, +  XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq =3618,
-  XED_IFORM_VCVTSD2SI_GPR32d_MEMq =3619, +  XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq =3619,
-  XED_IFORM_VCVTSD2SI_GPR32d_XMMq =3620, +  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3620,
-  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 =3621, +  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3621,
-  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 =3622, +  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3622,
-  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 =3623, +  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3623,
-  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 =3624, +  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256 =3624,
-  XED_IFORM_VCVTSD2SI_GPR64q_MEMq =3625, +  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3625,
-  XED_IFORM_VCVTSD2SI_GPR64q_XMMq =3626, +  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3626,
-  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq =3627, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 =3627,
-  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq =3628, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 =3628,
-  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 =3629, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 =3629,
-  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 =3630, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 =3630,
-  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 =3631, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 =3631,
-  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 =3632, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC =3632,
-  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 =3633, +  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 =3633,
-  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 =3634, +  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq =3634,
-  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 =3635, +  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq =3635,
-  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 =3636, +  XED_IFORM_VCVTPD2PS_XMMdq_XMMdq =3636,
-  XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512 =3637, +  XED_IFORM_VCVTPD2PS_XMMdq_YMMqq =3637,
-  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512 =3638, +  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 =3638,
-  XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512 =3639, +  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 =3639,
-  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512 =3640, +  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 =3640,
-  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 =3641, +  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 =3641,
-  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 =3642, +  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256 =3642,
-  XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512 =3643, +  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 =3643,
-  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512 =3644, +  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 =3644,
-  XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512 =3645, +  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3645,
-  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512 =3646, +  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3646,
-  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d =3647, +  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3647,
-  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q =3648, +  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3648,
-  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd =3649, +  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC =3649,
-  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq =3650, +  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3650,
-  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 =3651, +  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3651,
-  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 =3652, +  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3652,
-  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 =3653, +  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3653,
-  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 =3654, +  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3654,
-  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 =3655, +  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3655,
-  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 =3656, +  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256 =3656,
-  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 =3657, +  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3657,
-  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 =3658, +  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3658,
-  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d =3659, +  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3659,
-  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q =3660, +  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3660,
-  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd =3661, +  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3661,
-  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq =3662, +  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3662,
-  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 =3663, +  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC =3663,
-  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 =3664, +  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3664,
-  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 =3665, +  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3665,
-  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 =3666, +  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3666,
-  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd =3667, +  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =3667,
-  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd =3668, +  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =3668,
-  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 =3669, +  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =3669,
-  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 =3670, +  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC =3670,
-  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 =3671, +  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =3671,
-  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 =3672, +  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =3672,
-  XED_IFORM_VCVTSS2SI_GPR32d_MEMd =3673, +  XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 =3673,
-  XED_IFORM_VCVTSS2SI_GPR32d_XMMd =3674, +  XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 =3674,
-  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 =3675, +  XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 =3675,
-  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 =3676, +  XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 =3676,
-  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 =3677, +  XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 =3677,
-  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 =3678, +  XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 =3678,
-  XED_IFORM_VCVTSS2SI_GPR64q_MEMd =3679, +  XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 =3679,
-  XED_IFORM_VCVTSS2SI_GPR64q_XMMd =3680, +  XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 =3680,
-  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 =3681, +  XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 =3681,
-  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 =3682, +  XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 =3682,
-  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 =3683, +  XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 =3683,
-  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 =3684, +  XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 =3684,
-  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq =3685, +  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 =3685,
-  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq =3686, +  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 =3686,
-  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq =3687, +  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 =3687,
-  XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq =3688, +  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 =3688,
-  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3689, +  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC =3689,
-  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3690, +  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 =3690,
-  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3691, +  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 =3691,
-  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3692, +  XED_IFORM_VCVTPH2PS_XMMdq_MEMq =3692,
-  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3693, +  XED_IFORM_VCVTPH2PS_XMMdq_XMMq =3693,
-  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3694, +  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 =3694,
-  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3695, +  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 =3695,
-  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3696, +  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 =3696,
-  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3697, +  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 =3697,
-  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3698, +  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC =3698,
-  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3699, +  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq =3699,
-  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3700, +  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq =3700,
-  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3701, +  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 =3701,
-  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3702, +  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 =3702,
-  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3703, +  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 =3703,
-  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3704, +  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 =3704,
-  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3705, +  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 =3705,
-  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3706, +  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 =3706,
-  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3707, +  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC =3707,
-  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3708, +  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 =3708,
-  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3709, +  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 =3709,
-  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3710, +  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =3710,
-  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3711, +  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =3711,
-  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3712, +  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =3712,
-  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3713, +  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =3713,
-  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =3714, +  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC =3714,
-  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =3715, +  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =3715,
-  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =3716, +  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =3716,
-  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =3717, +  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =3717,
-  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =3718, +  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =3718,
-  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =3719, +  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =3719,
-  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =3720, +  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =3720,
-  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =3721, +  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC =3721,
-  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =3722, +  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =3722,
-  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =3723, +  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =3723,
-  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =3724, +  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =3724,
-  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =3725, +  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =3725,
-  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =3726, +  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =3726,
-  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =3727, +  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =3727,
-  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =3728, +  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC =3728,
-  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =3729, +  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =3729,
-  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =3730, +  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =3730,
-  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =3731, +  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =3731,
-  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =3732, +  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =3732,
-  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =3733, +  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =3733,
-  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =3734, +  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =3734,
-  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =3735, +  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC =3735,
-  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =3736, +  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =3736,
-  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =3737, +  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =3737,
-  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =3738, +  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =3738,
-  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =3739, +  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =3739,
-  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =3740, +  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =3740,
-  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =3741, +  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =3741,
-  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =3742, +  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC =3742,
-  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =3743, +  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =3743,
-  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =3744, +  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =3744,
-  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =3745, +  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq =3745,
-  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =3746, +  XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq =3746,
-  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =3747, +  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =3747,
-  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =3748, +  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =3748,
-  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq =3749, +  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =3749,
-  XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq =3750, +  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =3750,
-  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =3751, +  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC =3751,
-  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =3752, +  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq =3752,
-  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =3753, +  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq =3753,
-  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =3754, +  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =3754,
-  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq =3755, +  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =3755,
-  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq =3756, +  XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 =3756,
-  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =3757, +  XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 =3757,
-  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =3758, +  XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 =3758,
-  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =3759, +  XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 =3759,
-  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =3760, +  XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 =3760,
-  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =3761, +  XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 =3761,
-  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =3762, +  XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 =3762,
-  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =3763, +  XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 =3763,
-  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =3764, +  XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 =3764,
-  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =3765, +  XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 =3765,
-  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =3766, +  XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 =3766,
-  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =3767, +  XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 =3767,
-  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =3768, +  XED_IFORM_VCVTPS2PD_XMMdq_MEMq =3768,
-  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =3769, +  XED_IFORM_VCVTPS2PD_XMMdq_XMMq =3769,
-  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =3770, +  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 =3770,
-  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =3771, +  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 =3771,
-  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =3772, +  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 =3772,
-  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =3773, +  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 =3773,
-  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =3774, +  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC =3774,
-  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =3775, +  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq =3775,
-  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =3776, +  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq =3776,
-  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq =3777, +  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 =3777,
-  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq =3778, +  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 =3778,
-  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 =3779, +  XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb =3779,
-  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 =3780, +  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 =3780,
-  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 =3781, +  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 =3781,
-  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 =3782, +  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3782,
-  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq =3783, +  XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb =3783,
-  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq =3784, +  XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb =3784,
-  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 =3785, +  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 =3785,
-  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 =3786, +  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 =3786,
-  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 =3787, +  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC =3787,
-  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 =3788, +  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb =3788,
-  XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512 =3789, +  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3789,
-  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512 =3790, +  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 =3790,
-  XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512 =3791, +  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 =3791,
-  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512 =3792, +  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 =3792,
-  XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512 =3793, +  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 =3793,
-  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512 =3794, +  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC =3794,
-  XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512 =3795, +  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 =3795,
-  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512 =3796, +  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 =3796,
-  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd =3797, +  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =3797,
-  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd =3798, +  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =3798,
-  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 =3799, +  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =3799,
-  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 =3800, +  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =3800,
-  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 =3801, +  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC =3801,
-  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 =3802, +  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =3802,
-  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd =3803, +  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =3803,
-  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd =3804, +  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =3804,
-  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 =3805, +  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =3805,
-  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 =3806, +  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =3806,
-  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 =3807, +  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =3807,
-  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 =3808, +  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC =3808,
-  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 =3809, +  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =3809,
-  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 =3810, +  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =3810,
-  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 =3811, +  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =3811,
-  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 =3812, +  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =3812,
-  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 =3813, +  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =3813,
-  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 =3814, +  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =3814,
-  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 =3815, +  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC =3815,
-  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 =3816, +  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =3816,
-  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 =3817, +  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =3817,
-  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 =3818, +  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 =3818,
-  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 =3819, +  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 =3819,
-  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 =3820, +  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 =3820,
-  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 =3821, +  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 =3821,
-  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 =3822, +  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC =3822,
-  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 =3823, +  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 =3823,
-  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 =3824, +  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 =3824,
-  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 =3825, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =3825,
-  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 =3826, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =3826,
-  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 =3827, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =3827,
-  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 =3828, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =3828,
-  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 =3829, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =3829,
-  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 =3830, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC =3830,
-  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 =3831, +  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =3831,
-  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 =3832, +  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =3832,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =3833, +  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =3833,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =3834, +  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =3834,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =3835, +  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =3835,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =3836, +  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256 =3836,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =3837, +  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =3837,
-  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =3838, +  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =3838,
-  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =3839, +  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 =3839,
-  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =3840, +  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 =3840,
-  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =3841, +  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =3841,
-  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =3842, +  XED_IFORM_VCVTSD2SI_GPR32d_MEMq =3842,
-  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =3843, +  XED_IFORM_VCVTSD2SI_GPR32d_XMMq =3843,
-  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =3844, +  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 =3844,
-  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 =3845, +  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 =3845,
-  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 =3846, +  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC =3846,
-  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 =3847, +  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 =3847,
-  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 =3848, +  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 =3848,
-  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 =3849, +  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC =3849,
-  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 =3850, +  XED_IFORM_VCVTSD2SI_GPR64q_MEMq =3850,
-  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 =3851, +  XED_IFORM_VCVTSD2SI_GPR64q_XMMq =3851,
-  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 =3852, +  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq =3852,
-  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 =3853, +  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq =3853,
-  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 =3854, +  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 =3854,
-  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 =3855, +  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 =3855,
-  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 =3856, +  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =3856,
-  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 =3857, +  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 =3857,
-  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 =3858, +  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 =3858,
-  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 =3859, +  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC =3859,
-  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 =3860, +  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 =3860,
-  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 =3861, +  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 =3861,
-  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 =3862, +  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC =3862,
-  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 =3863, +  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 =3863,
-  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 =3864, +  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 =3864,
-  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 =3865, +  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC =3865,
-  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 =3866, +  XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512 =3866,
-  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 =3867, +  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512 =3867,
-  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 =3868, +  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC =3868,
-  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =3869, +  XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512 =3869,
-  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =3870, +  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512 =3870,
-  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =3871, +  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC =3871,
-  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =3872, +  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 =3872,
-  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =3873, +  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 =3873,
-  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =3874, +  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC =3874,
-  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq =3875, +  XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512 =3875,
-  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq =3876, +  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512 =3876,
-  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3877, +  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC =3877,
-  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3878, +  XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512 =3878,
-  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3879, +  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512 =3879,
-  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3880, +  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC =3880,
-  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq =3881, +  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d =3881,
-  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq =3882, +  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q =3882,
-  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3883, +  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd =3883,
-  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3884, +  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq =3884,
-  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3885, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 =3885,
-  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3886, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC =3886,
-  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =3887, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 =3887,
-  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =3888, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC =3888,
-  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =3889, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 =3889,
-  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =3890, +  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 =3890,
-  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq =3891, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 =3891,
-  XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq =3892, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC =3892,
-  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3893, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 =3893,
-  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3894, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC =3894,
-  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3895, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 =3895,
-  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3896, +  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 =3896,
-  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq =3897, +  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d =3897,
-  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq =3898, +  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q =3898,
-  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3899, +  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd =3899,
-  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3900, +  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq =3900,
-  XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq =3901, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 =3901,
-  XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq =3902, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC =3902,
-  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3903, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 =3903,
-  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3904, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC =3904,
-  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3905, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 =3905,
-  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3906, +  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 =3906,
-  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd =3907, +  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd =3907,
-  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd =3908, +  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd =3908,
-  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3909, +  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 =3909,
-  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3910, +  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 =3910,
-  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 =3911, +  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =3911,
-  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 =3912, +  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 =3912,
-  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 =3913, +  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 =3913,
-  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 =3914, +  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC =3914,
-  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 =3915, +  XED_IFORM_VCVTSS2SI_GPR32d_MEMd =3915,
-  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3916, +  XED_IFORM_VCVTSS2SI_GPR32d_XMMd =3916,
-  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb =3917, +  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 =3917,
-  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb =3918, +  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 =3918,
-  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb =3919, +  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC =3919,
-  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb =3920, +  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 =3920,
-  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb =3921, +  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 =3921,
-  XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb =3922, +  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC =3922,
-  XED_IFORM_VERR_GPR16 =3923, +  XED_IFORM_VCVTSS2SI_GPR64q_MEMd =3923,
-  XED_IFORM_VERR_MEMw =3924, +  XED_IFORM_VCVTSS2SI_GPR64q_XMMd =3924,
-  XED_IFORM_VERW_GPR16 =3925, +  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 =3925,
-  XED_IFORM_VERW_MEMw =3926, +  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 =3926,
-  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =3927, +  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC =3927,
-  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =3928, +  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 =3928,
-  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =3929, +  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 =3929,
-  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =3930, +  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC =3930,
-  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 =3931, +  XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 =3931,
-  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 =3932, +  XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 =3932,
-  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 =3933, +  XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 =3933,
-  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 =3934, +  XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 =3934,
-  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 =3935, +  XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 =3935,
-  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =3936, +  XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 =3936,
-  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 =3937, +  XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 =3937,
-  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 =3938, +  XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 =3938,
-  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 =3939, +  XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 =3939,
-  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 =3940, +  XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 =3940,
-  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 =3941, +  XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 =3941,
-  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =3942, +  XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 =3942,
-  XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb =3943, +  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq =3943,
-  XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb =3944, +  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq =3944,
-  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 =3945, +  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq =3945,
-  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =3946, +  XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq =3946,
-  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 =3947, +  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3947,
-  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =3948, +  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3948,
-  XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =3949, +  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3949,
-  XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =3950, +  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3950,
-  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 =3951, +  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256 =3951,
-  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =3952, +  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3952,
-  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 =3953, +  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3953,
-  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =3954, +  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3954,
-  XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =3955, +  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3955,
-  XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =3956, +  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512 =3956,
-  XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb =3957, +  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512 =3957,
-  XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb =3958, +  XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3958,
-  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 =3959, +  XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512 =3959,
-  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =3960, +  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3960,
-  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 =3961, +  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3961,
-  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =3962, +  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3962,
-  XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =3963, +  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3963,
-  XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =3964, +  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC =3964,
-  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 =3965, +  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3965,
-  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =3966, +  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3966,
-  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 =3967, +  XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512 =3967,
-  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =3968, +  XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512 =3968,
-  XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =3969, +  XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512 =3969,
-  XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =3970, +  XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512 =3970,
-  XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb =3971, +  XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512 =3971,
-  XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 =3972, +  XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512 =3972,
-  XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb =3973, +  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3973,
-  XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 =3974, +  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3974,
-  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =3975, +  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3975,
-  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =3976, +  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3976,
-  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =3977, +  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256 =3977,
-  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =3978, +  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3978,
-  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =3979, +  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3979,
-  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =3980, +  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3980,
-  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =3981, +  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3981,
-  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =3982, +  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512 =3982,
-  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =3983, +  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512 =3983,
-  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =3984, +  XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3984,
-  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =3985, +  XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512 =3985,
-  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =3986, +  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3986,
-  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =3987, +  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3987,
-  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =3988, +  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3988,
-  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =3989, +  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3989,
-  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =3990, +  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC =3990,
-  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3991, +  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3991,
-  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3992, +  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3992,
-  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =3993, +  XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512 =3993,
-  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =3994, +  XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512 =3994,
-  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =3995, +  XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512 =3995,
-  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =3996, +  XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512 =3996,
-  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3997, +  XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512 =3997,
-  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3998, +  XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512 =3998,
-  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =3999, +  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3999,
-  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =4000, +  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =4000,
-  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =4001, +  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =4001,
-  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =4002, +  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =4002,
-  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4003, +  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC =4003,
-  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4004, +  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =4004,
-  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4005, +  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =4005,
-  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4006, +  XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 =4006,
-  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq =4007, +  XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 =4007,
-  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq =4008, +  XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 =4008,
-  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4009, +  XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 =4009,
-  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4010, +  XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 =4010,
-  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4011, +  XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 =4011,
-  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4012, +  XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 =4012,
-  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq =4013, +  XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 =4013,
-  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq =4014, +  XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 =4014,
-  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4015, +  XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 =4015,
-  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4016, +  XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 =4016,
-  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4017, +  XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 =4017,
-  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4018, +  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =4018,
-  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4019, +  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =4019,
-  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4020, +  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =4020,
-  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4021, +  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =4021,
-  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4022, +  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC =4022,
-  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq =4023, +  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =4023,
-  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq =4024, +  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =4024,
-  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4025, +  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =4025,
-  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4026, +  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =4026,
-  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4027, +  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =4027,
-  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4028, +  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =4028,
-  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq =4029, +  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC =4029,
-  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq =4030, +  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =4030,
-  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4031, +  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =4031,
-  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4032, +  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =4032,
-  XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq =4033, +  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =4033,
-  XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq =4034, +  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =4034,
-  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4035, +  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =4035,
-  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4036, +  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC =4036,
-  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4037, +  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =4037,
-  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4038, +  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =4038,
-  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd =4039, +  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =4039,
-  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd =4040, +  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =4040,
-  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4041, +  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =4041,
-  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4042, +  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =4042,
-  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq =4043, +  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC =4043,
-  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq =4044, +  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =4044,
-  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4045, +  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =4045,
-  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4046, +  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =4046,
-  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4047, +  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =4047,
-  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4048, +  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =4048,
-  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq =4049, +  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =4049,
-  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq =4050, +  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC =4050,
-  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4051, +  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =4051,
-  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4052, +  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =4052,
-  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4053, +  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq =4053,
-  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4054, +  XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq =4054,
-  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4055, +  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =4055,
-  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4056, +  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =4056,
-  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4057, +  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =4057,
-  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4058, +  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =4058,
-  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq =4059, +  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC =4059,
-  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq =4060, +  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq =4060,
-  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4061, +  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq =4061,
-  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4062, +  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =4062,
-  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4063, +  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =4063,
-  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4064, +  XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512 =4064,
-  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq =4065, +  XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512 =4065,
-  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq =4066, +  XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512 =4066,
-  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4067, +  XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512 =4067,
-  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4068, +  XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512 =4068,
-  XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq =4069, +  XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512 =4069,
-  XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq =4070, +  XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 =4070,
-  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4071, +  XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 =4071,
-  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4072, +  XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 =4072,
-  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4073, +  XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 =4073,
-  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4074, +  XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 =4074,
-  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd =4075, +  XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 =4075,
-  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd =4076, +  XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 =4076,
-  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4077, +  XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 =4077,
-  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4078, +  XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 =4078,
-  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq =4079, +  XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 =4079,
-  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq =4080, +  XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 =4080,
-  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4081, +  XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 =4081,
-  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4082, +  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =4082,
-  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4083, +  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =4083,
-  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4084, +  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =4084,
-  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq =4085, +  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =4085,
-  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq =4086, +  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC =4086,
-  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4087, +  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =4087,
-  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4088, +  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =4088,
-  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4089, +  XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512 =4089,
-  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4090, +  XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512 =4090,
-  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4091, +  XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512 =4091,
-  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4092, +  XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512 =4092,
-  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4093, +  XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512 =4093,
-  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4094, +  XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512 =4094,
-  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq =4095, +  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =4095,
-  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq =4096, +  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =4096,
-  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4097, +  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =4097,
-  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4098, +  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =4098,
-  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4099, +  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC =4099,
-  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4100, +  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =4100,
-  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq =4101, +  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =4101,
-  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq =4102, +  XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512 =4102,
-  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4103, +  XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512 =4103,
-  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4104, +  XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512 =4104,
-  XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq =4105, +  XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512 =4105,
-  XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq =4106, +  XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512 =4106,
-  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4107, +  XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512 =4107,
-  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4108, +  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =4108,
-  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4109, +  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =4109,
-  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4110, +  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =4110,
-  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd =4111, +  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =4111,
-  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd =4112, +  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC =4112,
-  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4113, +  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =4113,
-  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4114, +  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =4114,
-  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4115, +  XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512 =4115,
-  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4116, +  XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512 =4116,
-  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4117, +  XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512 =4117,
-  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4118, +  XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512 =4118,
-  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4119, +  XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512 =4119,
-  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4120, +  XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512 =4120,
-  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4121, +  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq =4121,
-  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4122, +  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq =4122,
-  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4123, +  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 =4123,
-  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4124, +  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 =4124,
-  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4125, +  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC =4125,
-  XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4126, +  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 =4126,
-  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4127, +  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 =4127,
-  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4128, +  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC =4128,
-  XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4129, +  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq =4129,
-  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4130, +  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq =4130,
-  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4131, +  XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512 =4131,
-  XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4132, +  XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512 =4132,
-  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4133, +  XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512 =4133,
-  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4134, +  XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512 =4134,
-  XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq =4135, +  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 =4135,
-  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq =4136, +  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 =4136,
-  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq =4137, +  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC =4137,
-  XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd =4138, +  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 =4138,
-  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd =4139, +  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 =4139,
-  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd =4140, +  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC =4140,
-  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq =4141, +  XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512 =4141,
-  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq =4142, +  XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512 =4142,
-  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4143, +  XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512 =4143,
-  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4144, +  XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512 =4144,
-  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4145, +  XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512 =4145,
-  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4146, +  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512 =4146,
-  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq =4147, +  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC =4147,
-  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq =4148, +  XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512 =4148,
-  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4149, +  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512 =4149,
-  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4150, +  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC =4150,
-  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4151, +  XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512 =4151,
-  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4152, +  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512 =4152,
-  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4153, +  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC =4153,
-  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4154, +  XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512 =4154,
-  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4155, +  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512 =4155,
-  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4156, +  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC =4156,
-  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq =4157, +  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd =4157,
-  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq =4158, +  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd =4158,
-  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4159, +  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 =4159,
-  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4160, +  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 =4160,
-  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4161, +  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC =4161,
-  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4162, +  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 =4162,
-  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq =4163, +  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 =4163,
-  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq =4164, +  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC =4164,
-  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4165, +  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd =4165,
-  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4166, +  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd =4166,
-  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq =4167, +  XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512 =4167,
-  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq =4168, +  XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512 =4168,
-  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4169, +  XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512 =4169,
-  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4170, +  XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512 =4170,
-  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4171, +  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 =4171,
-  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4172, +  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 =4172,
-  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq =4173, +  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC =4173,
-  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq =4174, +  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 =4174,
-  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4175, +  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 =4175,
-  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4176, +  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC =4176,
-  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4177, +  XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512 =4177,
-  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4178, +  XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512 =4178,
-  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4179, +  XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512 =4179,
-  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4180, +  XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512 =4180,
-  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4181, +  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 =4181,
-  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4182, +  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 =4182,
-  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq =4183, +  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 =4183,
-  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq =4184, +  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 =4184,
-  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4185, +  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC =4185,
-  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4186, +  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 =4186,
-  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4187, +  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 =4187,
-  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4188, +  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 =4188,
-  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq =4189, +  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 =4189,
-  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq =4190, +  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 =4190,
-  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4191, +  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 =4191,
-  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4192, +  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC =4192,
-  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq =4193, +  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 =4193,
-  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq =4194, +  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 =4194,
-  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4195, +  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 =4195,
-  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4196, +  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 =4196,
-  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4197, +  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 =4197,
-  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4198, +  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 =4198,
-  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq =4199, +  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC =4199,
-  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq =4200, +  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 =4200,
-  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4201, +  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 =4201,
-  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4202, +  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 =4202,
-  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4203, +  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 =4203,
-  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4204, +  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 =4204,
-  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4205, +  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 =4205,
-  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4206, +  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC =4206,
-  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4207, +  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 =4207,
-  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4208, +  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 =4208,
-  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq =4209, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =4209,
-  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq =4210, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =4210,
-  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4211, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =4211,
-  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4212, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =4212,
-  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4213, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =4213,
-  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4214, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC =4214,
-  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq =4215, +  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =4215,
-  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq =4216, +  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =4216,
-  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4217, +  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =4217,
-  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4218, +  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =4218,
-  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4219, +  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =4219,
-  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4220, +  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256 =4220,
-  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4221, +  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =4221,
-  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4222, +  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =4222,
-  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4223, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 =4223,
-  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4224, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC =4224,
-  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4225, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 =4225,
-  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4226, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC =4226,
-  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4227, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 =4227,
-  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4228, +  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 =4228,
-  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4229, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 =4229,
-  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4230, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC =4230,
-  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq =4231, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 =4231,
-  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq =4232, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC =4232,
-  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4233, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 =4233,
-  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4234, +  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 =4234,
-  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4235, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 =4235,
-  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4236, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC =4236,
-  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq =4237, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 =4237,
-  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq =4238, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC =4238,
-  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4239, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 =4239,
-  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4240, +  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 =4240,
-  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4241, +  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 =4241,
-  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4242, +  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 =4242,
-  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4243, +  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 =4243,
-  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4244, +  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 =4244,
-  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4245, +  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC =4245,
-  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4246, +  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 =4246,
-  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq =4247, +  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 =4247,
-  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq =4248, +  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 =4248,
-  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4249, +  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 =4249,
-  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4250, +  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 =4250,
-  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4251, +  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 =4251,
-  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4252, +  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC =4252,
-  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq =4253, +  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 =4253,
-  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq =4254, +  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 =4254,
-  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4255, +  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =4255,
-  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4256, +  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =4256,
-  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq =4257, +  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =4257,
-  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq =4258, +  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =4258,
-  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4259, +  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =4259,
-  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4260, +  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =4260,
-  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4261, +  XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4261,
-  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4262, +  XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4262,
-  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd =4263, +  XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4263,
-  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd =4264, +  XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4264,
-  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4265, +  XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4265,
-  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4266, +  XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4266,
-  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq =4267, +  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq =4267,
-  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq =4268, +  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq =4268,
-  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4269, +  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4269,
-  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4270, +  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4270,
-  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4271, +  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4271,
-  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4272, +  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4272,
-  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq =4273, +  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4273,
-  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq =4274, +  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq =4274,
-  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4275, +  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq =4275,
-  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4276, +  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4276,
-  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4277, +  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4277,
-  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4278, +  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4278,
-  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4279, +  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4279,
-  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4280, +  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4280,
-  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4281, +  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4281,
-  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4282, +  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4282,
-  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq =4283, +  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4283,
-  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq =4284, +  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4284,
-  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4285, +  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq =4285,
-  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4286, +  XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq =4286,
-  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4287, +  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4287,
-  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4288, +  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4288,
-  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq =4289, +  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4289,
-  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq =4290, +  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4290,
-  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4291, +  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4291,
-  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4292, +  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq =4292,
-  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq =4293, +  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq =4293,
-  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq =4294, +  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4294,
-  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4295, +  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4295,
-  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4296, +  XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq =4296,
-  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4297, +  XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq =4297,
-  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4298, +  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4298,
-  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd =4299, +  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4299,
-  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd =4300, +  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4300,
-  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4301, +  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4301,
-  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4302, +  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4302,
-  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq =4303, +  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4303,
-  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq =4304, +  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd =4304,
-  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4305, +  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd =4305,
-  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4306, +  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4306,
-  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4307, +  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4307,
-  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4308, +  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4308,
-  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq =4309, +  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 =4309,
-  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq =4310, +  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 =4310,
-  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4311, +  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 =4311,
-  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4312, +  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 =4312,
-  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4313, +  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 =4313,
-  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4314, +  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 =4314,
-  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4315, +  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb =4315,
-  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4316, +  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb =4316,
-  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4317, +  XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512 =4317,
-  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4318, +  XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512 =4318,
-  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq =4319, +  XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512 =4319,
-  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq =4320, +  XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512 =4320,
-  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4321, +  XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4321,
-  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4322, +  XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4322,
-  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4323, +  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb =4323,
-  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4324, +  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb =4324,
-  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq =4325, +  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb =4325,
-  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq =4326, +  XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb =4326,
-  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4327, +  XED_IFORM_VERR_GPR16 =4327,
-  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4328, +  XED_IFORM_VERR_MEMw =4328,
-  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq =4329, +  XED_IFORM_VERW_GPR16 =4329,
-  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq =4330, +  XED_IFORM_VERW_MEMw =4330,
-  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4331, +  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =4331,
-  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4332, +  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =4332,
-  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4333, +  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =4333,
-  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4334, +  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =4334,
-  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd =4335, +  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 =4335,
-  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd =4336, +  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 =4336,
-  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4337, +  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 =4337,
-  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4338, +  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 =4338,
-  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq =4339, +  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 =4339,
-  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq =4340, +  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =4340,
-  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4341, +  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 =4341,
-  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4342, +  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 =4342,
-  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4343, +  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 =4343,
-  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4344, +  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 =4344,
-  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq =4345, +  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 =4345,
-  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq =4346, +  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =4346,
-  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4347, +  XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb =4347,
-  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4348, +  XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb =4348,
-  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4349, +  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 =4349,
-  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4350, +  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4350,
-  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4351, +  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 =4351,
-  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4352, +  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4352,
-  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4353, +  XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4353,
-  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4354, +  XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4354,
-  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq =4355, +  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 =4355,
-  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq =4356, +  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4356,
-  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4357, +  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 =4357,
-  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4358, +  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4358,
-  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4359, +  XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4359,
-  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4360, +  XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4360,
-  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq =4361, +  XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb =4361,
-  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq =4362, +  XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb =4362,
-  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4363, +  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 =4363,
-  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4364, +  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4364,
-  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq =4365, +  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 =4365,
-  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq =4366, +  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4366,
-  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4367, +  XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4367,
-  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4368, +  XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4368,
-  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4369, +  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 =4369,
-  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4370, +  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4370,
-  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq =4371, +  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 =4371,
-  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq =4372, +  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4372,
-  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4373, +  XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4373,
-  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4374, +  XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4374,
-  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4375, +  XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb =4375,
-  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4376, +  XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 =4376,
-  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4377, +  XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb =4377,
-  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4378, +  XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 =4378,
-  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4379, +  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4379,
-  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4380, +  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4380,
-  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq =4381, +  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4381,
-  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq =4382, +  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4382,
-  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4383, +  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC =4383,
-  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4384, +  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4384,
-  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4385, +  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4385,
-  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4386, +  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4386,
-  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq =4387, +  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4387,
-  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq =4388, +  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC =4388,
-  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4389, +  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4389,
-  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4390, +  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4390,
-  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq =4391, +  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4391,
-  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq =4392, +  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4392,
-  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4393, +  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC =4393,
-  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4394, +  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4394,
-  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4395, +  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4395,
-  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4396, +  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4396,
-  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq =4397, +  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4397,
-  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq =4398, +  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC =4398,
-  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4399, +  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4399,
-  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4400, +  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4400,
-  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4401, +  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =4401,
-  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4402, +  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =4402,
-  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4403, +  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC =4403,
-  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4404, +  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =4404,
-  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4405, +  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =4405,
-  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4406, +  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4406,
-  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq =4407, +  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4407,
-  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq =4408, +  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =4408,
-  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4409, +  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =4409,
-  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4410, +  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC =4410,
-  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4411, +  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =4411,
-  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4412, +  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =4412,
-  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq =4413, +  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4413,
-  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq =4414, +  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4414,
-  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4415, +  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =4415,
-  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4416, +  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4416,
-  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4417, +  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4417,
-  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4418, +  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =4418,
-  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4419, +  XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4419,
-  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4420, +  XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4420,
-  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4421, +  XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4421,
-  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4422, +  XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4422,
-  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4423, +  XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4423,
-  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4424, +  XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4424,
-  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4425, +  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq =4425,
-  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4426, +  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq =4426,
-  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4427, +  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4427,
-  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4428, +  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4428,
-  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4429, +  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4429,
-  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4430, +  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4430,
-  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4431, +  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4431,
-  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4432, +  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq =4432,
-  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4433, +  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq =4433,
-  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4434, +  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4434,
-  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4435, +  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4435,
-  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4436, +  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4436,
-  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4437, +  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4437,
-  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4438, +  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4438,
-  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4439, +  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4439,
-  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4440, +  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4440,
-  XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq =4441, +  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4441,
-  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq =4442, +  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4442,
-  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq =4443, +  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq =4443,
-  XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd =4444, +  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq =4444,
-  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd =4445, +  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4445,
-  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd =4446, +  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4446,
-  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4447, +  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4447,
-  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4448, +  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4448,
-  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4449, +  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4449,
-  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4450, +  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq =4450,
-  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4451, +  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq =4451,
-  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4452, +  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4452,
-  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4453, +  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4453,
-  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4454, +  XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq =4454,
-  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq =4455, +  XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq =4455,
-  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq =4456, +  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4456,
-  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4457, +  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4457,
-  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4458, +  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4458,
-  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4459, +  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4459,
-  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4460, +  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4460,
-  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq =4461, +  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4461,
-  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq =4462, +  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd =4462,
-  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4463, +  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd =4463,
-  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4464, +  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4464,
-  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4465, +  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4465,
-  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4466, +  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4466,
-  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4467, +  XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4467,
-  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4468, +  XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4468,
-  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4469, +  XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4469,
-  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4470, +  XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4470,
-  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq =4471, +  XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4471,
-  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq =4472, +  XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4472,
-  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4473, +  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq =4473,
-  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4474, +  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq =4474,
-  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4475, +  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4475,
-  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4476, +  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4476,
-  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq =4477, +  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4477,
-  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq =4478, +  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4478,
-  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4479, +  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4479,
-  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4480, +  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq =4480,
-  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq =4481, +  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq =4481,
-  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq =4482, +  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4482,
-  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4483, +  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4483,
-  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4484, +  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4484,
-  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4485, +  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4485,
-  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4486, +  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4486,
-  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd =4487, +  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4487,
-  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd =4488, +  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4488,
-  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4489, +  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4489,
-  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4490, +  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4490,
-  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq =4491, +  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq =4491,
-  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq =4492, +  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq =4492,
-  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4493, +  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4493,
-  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4494, +  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4494,
-  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4495, +  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4495,
-  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4496, +  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4496,
-  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq =4497, +  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4497,
-  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq =4498, +  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq =4498,
-  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4499, +  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq =4499,
-  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4500, +  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4500,
-  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4501, +  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4501,
-  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4502, +  XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq =4502,
-  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4503, +  XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq =4503,
-  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4504, +  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4504,
-  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4505, +  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4505,
-  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4506, +  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4506,
-  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq =4507, +  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4507,
-  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq =4508, +  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4508,
-  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4509, +  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4509,
-  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4510, +  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd =4510,
-  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4511, +  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd =4511,
-  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4512, +  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4512,
-  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq =4513, +  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4513,
-  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq =4514, +  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4514,
-  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4515, +  XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4515,
-  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4516, +  XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4516,
-  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq =4517, +  XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4517,
-  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq =4518, +  XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4518,
-  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4519, +  XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4519,
-  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4520, +  XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4520,
-  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4521, +  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq =4521,
-  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4522, +  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq =4522,
-  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd =4523, +  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4523,
-  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd =4524, +  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4524,
-  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4525, +  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4525,
-  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4526, +  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4526,
-  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq =4527, +  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4527,
-  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq =4528, +  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq =4528,
-  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4529, +  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq =4529,
-  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4530, +  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4530,
-  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4531, +  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4531,
-  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4532, +  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4532,
-  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq =4533, +  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4533,
-  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq =4534, +  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4534,
-  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4535, +  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4535,
-  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4536, +  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4536,
-  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4537, +  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4537,
-  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4538, +  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4538,
-  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4539, +  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq =4539,
-  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4540, +  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq =4540,
-  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4541, +  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4541,
-  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4542, +  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4542,
-  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq =4543, +  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4543,
-  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq =4544, +  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4544,
-  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4545, +  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4545,
-  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4546, +  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq =4546,
-  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4547, +  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq =4547,
-  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4548, +  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4548,
-  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq =4549, +  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4549,
-  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq =4550, +  XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq =4550,
-  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4551, +  XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq =4551,
-  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4552, +  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4552,
-  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq =4553, +  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4553,
-  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq =4554, +  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4554,
-  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4555, +  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4555,
-  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4556, +  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4556,
-  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4557, +  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4557,
-  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4558, +  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd =4558,
-  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd =4559, +  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd =4559,
-  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd =4560, +  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4560,
-  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4561, +  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4561,
-  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4562, +  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4562,
-  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4563, +  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4563,
-  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4564, +  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4564,
-  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4565, +  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4565,
-  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4566, +  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4566,
-  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4567, +  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC =4567,
-  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4568, +  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4568,
-  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4569, +  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4569,
-  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4570, +  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4570,
-  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4571, +  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4571,
-  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4572, +  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC =4572,
-  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4573, +  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4573,
-  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4574, +  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4574,
-  XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq =4575, +  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4575,
-  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq =4576, +  XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4576,
-  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq =4577, +  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4577,
-  XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd =4578, +  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4578,
-  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd =4579, +  XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4579,
-  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd =4580, +  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4580,
-  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq =4581, +  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4581,
-  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq =4582, +  XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4582,
-  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4583, +  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4583,
-  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4584, +  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4584,
-  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4585, +  XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq =4585,
-  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4586, +  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq =4586,
-  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq =4587, +  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq =4587,
-  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq =4588, +  XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd =4588,
-  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4589, +  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd =4589,
-  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4590, +  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd =4590,
-  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4591, +  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq =4591,
-  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4592, +  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq =4592,
-  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4593, +  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4593,
-  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4594, +  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4594,
-  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4595, +  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4595,
-  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4596, +  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4596,
-  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq =4597, +  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4597,
-  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq =4598, +  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq =4598,
-  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4599, +  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq =4599,
-  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4600, +  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4600,
-  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4601, +  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4601,
-  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4602, +  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4602,
-  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq =4603, +  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4603,
-  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq =4604, +  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4604,
-  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4605, +  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4605,
-  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4606, +  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4606,
-  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq =4607, +  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4607,
-  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq =4608, +  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4608,
-  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4609, +  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq =4609,
-  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4610, +  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq =4610,
-  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4611, +  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4611,
-  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4612, +  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4612,
-  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd =4613, +  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4613,
-  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd =4614, +  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4614,
-  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4615, +  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4615,
-  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4616, +  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq =4616,
-  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq =4617, +  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq =4617,
-  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq =4618, +  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4618,
-  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4619, +  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4619,
-  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4620, +  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq =4620,
-  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4621, +  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq =4621,
-  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4622, +  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4622,
-  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq =4623, +  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4623,
-  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq =4624, +  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4624,
-  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4625, +  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4625,
-  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4626, +  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4626,
-  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4627, +  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq =4627,
-  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4628, +  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq =4628,
-  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4629, +  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4629,
-  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4630, +  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4630,
-  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4631, +  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4631,
-  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4632, +  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4632,
-  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq =4633, +  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4633,
-  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq =4634, +  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4634,
-  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4635, +  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4635,
-  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4636, +  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4636,
-  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4637, +  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4637,
-  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4638, +  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq =4638,
-  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq =4639, +  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq =4639,
-  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq =4640, +  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4640,
-  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4641, +  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4641,
-  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4642, +  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4642,
-  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq =4643, +  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4643,
-  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq =4644, +  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4644,
-  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4645, +  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq =4645,
-  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4646, +  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq =4646,
-  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4647, +  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4647,
-  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4648, +  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4648,
-  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd =4649, +  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq =4649,
-  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd =4650, +  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq =4650,
-  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4651, +  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4651,
-  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4652, +  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4652,
-  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq =4653, +  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4653,
-  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq =4654, +  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4654,
-  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4655, +  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4655,
-  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4656, +  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq =4656,
-  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4657, +  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq =4657,
-  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4658, +  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4658,
-  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq =4659, +  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4659,
-  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq =4660, +  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4660,
-  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4661, +  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4661,
-  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4662, +  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4662,
-  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4663, +  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4663,
-  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4664, +  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4664,
-  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4665, +  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4665,
-  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4666, +  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4666,
-  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4667, +  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq =4667,
-  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4668, +  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq =4668,
-  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq =4669, +  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4669,
-  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq =4670, +  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4670,
-  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4671, +  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4671,
-  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4672, +  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4672,
-  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4673, +  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4673,
-  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4674, +  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq =4674,
-  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq =4675, +  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq =4675,
-  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq =4676, +  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4676,
-  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4677, +  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4677,
-  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4678, +  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4678,
-  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq =4679, +  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4679,
-  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq =4680, +  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4680,
-  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4681, +  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4681,
-  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4682, +  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4682,
-  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4683, +  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4683,
-  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4684, +  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4684,
-  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd =4685, +  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4685,
-  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd =4686, +  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4686,
-  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4687, +  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4687,
-  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4688, +  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4688,
-  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4689, +  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4689,
-  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4690, +  XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4690,
-  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4691, +  XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4691,
-  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4692, +  XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4692,
-  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4693, +  XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4693,
-  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4694, +  XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4694,
-  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4695, +  XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4695,
-  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4696, +  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq =4696,
-  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4697, +  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq =4697,
-  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4698, +  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4698,
-  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4699, +  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4699,
-  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4700, +  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4700,
-  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq =4701, +  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4701,
-  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq =4702, +  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4702,
-  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq =4703, +  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq =4703,
-  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd =4704, +  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq =4704,
-  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd =4705, +  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4705,
-  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd =4706, +  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4706,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 =4707, +  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4707,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 =4708, +  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4708,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 =4709, +  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4709,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =4710, +  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4710,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 =4711, +  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4711,
-  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 =4712, +  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4712,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 =4713, +  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4713,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 =4714, +  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq =4714,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 =4715, +  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq =4715,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =4716, +  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4716,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 =4717, +  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4717,
-  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 =4718, +  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4718,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 =4719, +  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4719,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 =4720, +  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4720,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 =4721, +  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq =4721,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =4722, +  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq =4722,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 =4723, +  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4723,
-  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 =4724, +  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4724,
-  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 =4725, +  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq =4725,
-  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =4726, +  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq =4726,
-  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 =4727, +  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4727,
-  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =4728, +  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4728,
-  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 =4729, +  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4729,
-  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =4730, +  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4730,
-  XED_IFORM_VFRCZPD_XMMdq_MEMdq =4731, +  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4731,
-  XED_IFORM_VFRCZPD_XMMdq_XMMdq =4732, +  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4732,
-  XED_IFORM_VFRCZPD_YMMqq_MEMqq =4733, +  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd =4733,
-  XED_IFORM_VFRCZPD_YMMqq_YMMqq =4734, +  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd =4734,
-  XED_IFORM_VFRCZPS_XMMdq_MEMdq =4735, +  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4735,
-  XED_IFORM_VFRCZPS_XMMdq_XMMdq =4736, +  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4736,
-  XED_IFORM_VFRCZPS_YMMqq_MEMqq =4737, +  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4737,
-  XED_IFORM_VFRCZPS_YMMqq_YMMqq =4738, +  XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4738,
-  XED_IFORM_VFRCZSD_XMMdq_MEMq =4739, +  XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4739,
-  XED_IFORM_VFRCZSD_XMMdq_XMMq =4740, +  XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4740,
-  XED_IFORM_VFRCZSS_XMMdq_MEMd =4741, +  XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4741,
-  XED_IFORM_VFRCZSS_XMMdq_XMMd =4742, +  XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4742,
-  XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =4743, +  XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4743,
-  XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 =4744, +  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq =4744,
-  XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =4745, +  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq =4745,
-  XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 =4746, +  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4746,
-  XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =4747, +  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4747,
-  XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =4748, +  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4748,
-  XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 =4749, +  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4749,
-  XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 =4750, +  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4750,
-  XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 =4751, +  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq =4751,
-  XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 =4752, +  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq =4752,
-  XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =4753, +  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4753,
-  XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =4754, +  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4754,
-  XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =4755, +  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4755,
-  XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =4756, +  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4756,
-  XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =4757, +  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4757,
-  XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =4758, +  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4758,
-  XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =4759, +  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4759,
-  XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =4760, +  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4760,
-  XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =4761, +  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4761,
-  XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 =4762, +  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq =4762,
-  XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =4763, +  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq =4763,
-  XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 =4764, +  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4764,
-  XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =4765, +  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4765,
-  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =4766, +  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4766,
-  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 =4767, +  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4767,
-  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 =4768, +  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4768,
-  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 =4769, +  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq =4769,
-  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 =4770, +  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq =4770,
-  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 =4771, +  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4771,
-  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 =4772, +  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4772,
-  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 =4773, +  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq =4773,
-  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 =4774, +  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq =4774,
-  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 =4775, +  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4775,
-  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =4776, +  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4776,
-  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 =4777, +  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4777,
-  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 =4778, +  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4778,
-  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 =4779, +  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4779,
-  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 =4780, +  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4780,
-  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =4781, +  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd =4781,
-  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =4782, +  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd =4782,
-  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 =4783, +  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4783,
-  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 =4784, +  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4784,
-  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 =4785, +  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4785,
-  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 =4786, +  XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4786,
-  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 =4787, +  XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4787,
-  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =4788, +  XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4788,
-  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4789, +  XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4789,
-  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4790, +  XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4790,
-  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4791, +  XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4791,
-  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4792, +  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq =4792,
-  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4793, +  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq =4793,
-  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4794, +  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4794,
-  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =4795, +  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4795,
-  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =4796, +  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4796,
-  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =4797, +  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4797,
-  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =4798, +  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4798,
-  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =4799, +  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq =4799,
-  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4800, +  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq =4800,
-  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =4801, +  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4801,
-  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =4802, +  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4802,
-  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =4803, +  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4803,
-  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =4804, +  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4804,
-  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =4805, +  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4805,
-  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =4806, +  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4806,
-  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =4807, +  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4807,
-  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =4808, +  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4808,
-  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =4809, +  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4809,
-  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =4810, +  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq =4810,
-  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =4811, +  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq =4811,
-  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4812, +  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4812,
-  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4813, +  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4813,
-  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4814, +  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4814,
-  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =4815, +  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4815,
-  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =4816, +  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4816,
-  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4817, +  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq =4817,
-  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4818, +  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq =4818,
-  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =4819, +  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4819,
-  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =4820, +  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4820,
-  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 =4821, +  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq =4821,
-  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 =4822, +  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq =4822,
-  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =4823, +  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4823,
-  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =4824, +  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4824,
-  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 =4825, +  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =4825,
-  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 =4826, +  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4826,
-  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =4827, +  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4827,
-  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =4828, +  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =4828,
-  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =4829, +  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd =4829,
-  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =4830, +  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd =4830,
-  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 =4831, +  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4831,
-  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 =4832, +  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4832,
-  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =4833, +  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =4833,
-  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =4834, +  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq =4834,
-  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 =4835, +  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq =4835,
-  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 =4836, +  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4836,
-  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =4837, +  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4837,
-  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =4838, +  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4838,
-  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =4839, +  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4839,
-  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =4840, +  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4840,
-  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 =4841, +  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq =4841,
-  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 =4842, +  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq =4842,
-  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =4843, +  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4843,
-  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =4844, +  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4844,
-  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 =4845, +  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4845,
-  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 =4846, +  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4846,
-  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =4847, +  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4847,
-  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =4848, +  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4848,
-  XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq =4849, +  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4849,
-  XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq =4850, +  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4850,
-  XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq =4851, +  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4851,
-  XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq =4852, +  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq =4852,
-  XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq =4853, +  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq =4853,
-  XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq =4854, +  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4854,
-  XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq =4855, +  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4855,
-  XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq =4856, +  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4856,
-  XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq =4857, +  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4857,
-  XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq =4858, +  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4858,
-  XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq =4859, +  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq =4859,
-  XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq =4860, +  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq =4860,
-  XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq =4861, +  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4861,
-  XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq =4862, +  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4862,
-  XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq =4863, +  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq =4863,
-  XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq =4864, +  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq =4864,
-  XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb =4865, +  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4865,
-  XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb =4866, +  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4866,
-  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =4867, +  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4867,
-  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 =4868, +  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4868,
-  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =4869, +  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4869,
-  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 =4870, +  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq =4870,
-  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =4871, +  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq =4871,
-  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 =4872, +  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4872,
-  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =4873, +  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4873,
-  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 =4874, +  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4874,
-  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =4875, +  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4875,
-  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 =4876, +  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4876,
-  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =4877, +  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4877,
-  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 =4878, +  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4878,
-  XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb =4879, +  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4879,
-  XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb =4880, +  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4880,
-  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =4881, +  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq =4881,
-  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 =4882, +  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq =4882,
-  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =4883, +  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4883,
-  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 =4884, +  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4884,
-  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =4885, +  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4885,
-  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 =4886, +  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4886,
-  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =4887, +  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4887,
-  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 =4888, +  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq =4888,
-  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =4889, +  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq =4889,
-  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 =4890, +  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4890,
-  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =4891, +  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4891,
-  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 =4892, +  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq =4892,
-  XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb =4893, +  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq =4893,
-  XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb =4894, +  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4894,
-  XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 =4895, +  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4895,
-  XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 =4896, +  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4896,
-  XED_IFORM_VLDDQU_XMMdq_MEMdq =4897, +  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4897,
-  XED_IFORM_VLDDQU_YMMqq_MEMqq =4898, +  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4898,
-  XED_IFORM_VLDMXCSR_MEMd =4899, +  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq =4899,
-  XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub =4900, +  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq =4900,
-  XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq =4901, +  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4901,
-  XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq =4902, +  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4902,
-  XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq =4903, +  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4903,
-  XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq =4904, +  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4904,
-  XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq =4905, +  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4905,
-  XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq =4906, +  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4906,
-  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq =4907, +  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4907,
-  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq =4908, +  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4908,
-  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq =4909, +  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4909,
-  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq =4910, +  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq =4910,
-  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4911, +  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq =4911,
-  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4912, +  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4912,
-  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4913, +  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4913,
-  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4914, +  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4914,
-  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq =4915, +  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4915,
-  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq =4916, +  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4916,
-  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4917, +  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq =4917,
-  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4918, +  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq =4918,
-  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4919, +  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4919,
-  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4920, +  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4920,
-  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4921, +  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4921,
-  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4922, +  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4922,
-  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4923, +  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4923,
-  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4924, +  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4924,
-  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq =4925, +  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4925,
-  XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq =4926, +  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4926,
-  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4927, +  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4927,
-  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4928, +  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4928,
-  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4929, +  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4929,
-  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4930, +  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4930,
-  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq =4931, +  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4931,
-  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq =4932, +  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4932,
-  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4933, +  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4933,
-  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4934, +  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4934,
-  XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq =4935, +  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4935,
-  XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq =4936, +  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4936,
-  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4937, +  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4937,
-  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4938, +  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4938,
-  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4939, +  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4939,
-  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4940, +  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4940,
-  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd =4941, +  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4941,
-  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd =4942, +  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4942,
-  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4943, +  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4943,
-  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4944, +  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4944,
-  XED_IFORM_VMCALL =4945, +  XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq =4945,
-  XED_IFORM_VMCLEAR_MEMq =4946, +  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq =4946,
-  XED_IFORM_VMFUNC =4947, +  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq =4947,
-  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq =4948, +  XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd =4948,
-  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq =4949, +  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd =4949,
-  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4950, +  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd =4950,
-  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4951, +  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4951,
-  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4952, +  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4952,
-  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4953, +  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4953,
-  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq =4954, +  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4954,
-  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq =4955, +  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC =4955,
-  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4956, +  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4956,
-  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4957, +  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4957,
-  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4958, +  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4958,
-  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4959, +  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4959,
-  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4960, +  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC =4960,
-  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4961, +  XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4961,
-  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4962, +  XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4962,
-  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4963, +  XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4963,
-  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq =4964, +  XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4964,
-  XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq =4965, +  XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4965,
-  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4966, +  XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4966,
-  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4967, +  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq =4967,
-  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4968, +  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq =4968,
-  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4969, +  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4969,
-  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq =4970, +  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4970,
-  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq =4971, +  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4971,
-  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4972, +  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4972,
-  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4973, +  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =4973,
-  XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq =4974, +  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq =4974,
-  XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq =4975, +  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq =4975,
-  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4976, +  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4976,
-  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4977, +  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4977,
-  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4978, +  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4978,
-  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4979, +  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4979,
-  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd =4980, +  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4980,
-  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd =4981, +  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4981,
-  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4982, +  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =4982,
-  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4983, +  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4983,
-  XED_IFORM_VMLAUNCH =4984, +  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4984,
-  XED_IFORM_VMLOAD_ArAX =4985, +  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq =4985,
-  XED_IFORM_VMMCALL =4986, +  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq =4986,
-  XED_IFORM_VMOVAPD_MEMdq_XMMdq =4987, +  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4987,
-  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 =4988, +  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4988,
-  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 =4989, +  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4989,
-  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 =4990, +  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4990,
-  XED_IFORM_VMOVAPD_MEMqq_YMMqq =4991, +  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =4991,
-  XED_IFORM_VMOVAPD_XMMdq_MEMdq =4992, +  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq =4992,
-  XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 =4993, +  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq =4993,
-  XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 =4994, +  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4994,
-  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 =4995, +  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4995,
-  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 =4996, +  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq =4996,
-  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 =4997, +  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq =4997,
-  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 =4998, +  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4998,
-  XED_IFORM_VMOVAPD_YMMqq_MEMqq =4999, +  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4999,
-  XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 =5000, +  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5000,
-  XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 =5001, +  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5001,
-  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5002, +  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5002,
-  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5003, +  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5003,
-  XED_IFORM_VMOVAPS_MEMdq_XMMdq =5004, +  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd =5004,
-  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 =5005, +  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd =5005,
-  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 =5006, +  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5006,
-  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5007, +  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5007,
-  XED_IFORM_VMOVAPS_MEMqq_YMMqq =5008, +  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5008,
-  XED_IFORM_VMOVAPS_XMMdq_MEMdq =5009, +  XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5009,
-  XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 =5010, +  XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5010,
-  XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 =5011, +  XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5011,
-  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 =5012, +  XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5012,
-  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 =5013, +  XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5013,
-  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 =5014, +  XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5014,
-  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 =5015, +  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq =5015,
-  XED_IFORM_VMOVAPS_YMMqq_MEMqq =5016, +  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq =5016,
-  XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 =5017, +  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5017,
-  XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 =5018, +  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5018,
-  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5019, +  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5019,
-  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5020, +  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5020,
-  XED_IFORM_VMOVD_GPR32d_XMMd =5021, +  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5021,
-  XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 =5022, +  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq =5022,
-  XED_IFORM_VMOVD_MEMd_XMMd =5023, +  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq =5023,
-  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 =5024, +  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5024,
-  XED_IFORM_VMOVD_XMMdq_GPR32d =5025, +  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5025,
-  XED_IFORM_VMOVD_XMMdq_MEMd =5026, +  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5026,
-  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 =5027, +  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5027,
-  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 =5028, +  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5028,
-  XED_IFORM_VMOVDDUP_XMMdq_MEMq =5029, +  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5029,
-  XED_IFORM_VMOVDDUP_XMMdq_XMMq =5030, +  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5030,
-  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 =5031, +  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5031,
-  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 =5032, +  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5032,
-  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 =5033, +  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq =5033,
-  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 =5034, +  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq =5034,
-  XED_IFORM_VMOVDDUP_YMMqq_MEMqq =5035, +  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5035,
-  XED_IFORM_VMOVDDUP_YMMqq_YMMqq =5036, +  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5036,
-  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 =5037, +  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5037,
-  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 =5038, +  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5038,
-  XED_IFORM_VMOVDQA_MEMdq_XMMdq =5039, +  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5039,
-  XED_IFORM_VMOVDQA_MEMqq_YMMqq =5040, +  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq =5040,
-  XED_IFORM_VMOVDQA_XMMdq_MEMdq =5041, +  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq =5041,
-  XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F =5042, +  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5042,
-  XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F =5043, +  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5043,
-  XED_IFORM_VMOVDQA_YMMqq_MEMqq =5044, +  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq =5044,
-  XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F =5045, +  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq =5045,
-  XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F =5046, +  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5046,
-  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 =5047, +  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5047,
-  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 =5048, +  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5048,
-  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 =5049, +  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5049,
-  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 =5050, +  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5050,
-  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 =5051, +  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5051,
-  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 =5052, +  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd =5052,
-  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 =5053, +  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd =5053,
-  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 =5054, +  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5054,
-  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5055, +  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5055,
-  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 =5056, +  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5056,
-  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 =5057, +  XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5057,
-  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 =5058, +  XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5058,
-  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 =5059, +  XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5059,
-  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 =5060, +  XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5060,
-  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 =5061, +  XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5061,
-  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 =5062, +  XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5062,
-  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 =5063, +  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq =5063,
-  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5064, +  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq =5064,
-  XED_IFORM_VMOVDQU_MEMdq_XMMdq =5065, +  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5065,
-  XED_IFORM_VMOVDQU_MEMqq_YMMqq =5066, +  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5066,
-  XED_IFORM_VMOVDQU_XMMdq_MEMdq =5067, +  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5067,
-  XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F =5068, +  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5068,
-  XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F =5069, +  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5069,
-  XED_IFORM_VMOVDQU_YMMqq_MEMqq =5070, +  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq =5070,
-  XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F =5071, +  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq =5071,
-  XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F =5072, +  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5072,
-  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 =5073, +  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5073,
-  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 =5074, +  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5074,
-  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 =5075, +  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5075,
-  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 =5076, +  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5076,
-  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 =5077, +  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5077,
-  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 =5078, +  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5078,
-  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 =5079, +  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5079,
-  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 =5080, +  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5080,
-  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 =5081, +  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq =5081,
-  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 =5082, +  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq =5082,
-  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 =5083, +  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5083,
-  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 =5084, +  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5084,
-  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 =5085, +  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5085,
-  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 =5086, +  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5086,
-  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 =5087, +  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5087,
-  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 =5088, +  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq =5088,
-  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 =5089, +  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq =5089,
-  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5090, +  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5090,
-  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 =5091, +  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5091,
-  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 =5092, +  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq =5092,
-  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 =5093, +  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq =5093,
-  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 =5094, +  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5094,
-  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 =5095, +  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5095,
-  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 =5096, +  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5096,
-  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 =5097, +  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5097,
-  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 =5098, +  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5098,
-  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5099, +  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5099,
-  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 =5100, +  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd =5100,
-  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 =5101, +  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd =5101,
-  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 =5102, +  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5102,
-  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 =5103, +  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5103,
-  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 =5104, +  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5104,
-  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 =5105, +  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =5105,
-  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 =5106, +  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =5106,
-  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 =5107, +  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =5107,
-  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 =5108, +  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =5108,
-  XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq =5109, +  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =5109,
-  XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 =5110, +  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =5110,
-  XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 =5111, +  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =5111,
-  XED_IFORM_VMOVHPD_MEMq_XMMdq =5112, +  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =5112,
-  XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq =5113, +  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =5113,
-  XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 =5114, +  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =5114,
-  XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 =5115, +  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =5115,
-  XED_IFORM_VMOVHPS_MEMq_XMMdq =5116, +  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =5116,
-  XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq =5117, +  XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq =5117,
-  XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 =5118, +  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq =5118,
-  XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq =5119, +  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq =5119,
-  XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 =5120, +  XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd =5120,
-  XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 =5121, +  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd =5121,
-  XED_IFORM_VMOVLPD_MEMq_XMMq =5122, +  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd =5122,
-  XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq =5123, +  XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5123,
-  XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 =5124, +  XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5124,
-  XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 =5125, +  XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5125,
-  XED_IFORM_VMOVLPS_MEMq_XMMq =5126, +  XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5126,
-  XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq =5127, +  XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5127,
-  XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 =5128, +  XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5128,
-  XED_IFORM_VMOVMSKPD_GPR32d_XMMdq =5129, +  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq =5129,
-  XED_IFORM_VMOVMSKPD_GPR32d_YMMqq =5130, +  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq =5130,
-  XED_IFORM_VMOVMSKPS_GPR32d_XMMdq =5131, +  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5131,
-  XED_IFORM_VMOVMSKPS_GPR32d_YMMqq =5132, +  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5132,
-  XED_IFORM_VMOVNTDQ_MEMdq_XMMdq =5133, +  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5133,
-  XED_IFORM_VMOVNTDQ_MEMqq_YMMqq =5134, +  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5134,
-  XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 =5135, +  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5135,
-  XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 =5136, +  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq =5136,
-  XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 =5137, +  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq =5137,
-  XED_IFORM_VMOVNTDQA_XMMdq_MEMdq =5138, +  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5138,
-  XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 =5139, +  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5139,
-  XED_IFORM_VMOVNTDQA_YMMqq_MEMqq =5140, +  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5140,
-  XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 =5141, +  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5141,
-  XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 =5142, +  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5142,
-  XED_IFORM_VMOVNTPD_MEMdq_XMMdq =5143, +  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5143,
-  XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 =5144, +  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5144,
-  XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 =5145, +  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5145,
-  XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 =5146, +  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5146,
-  XED_IFORM_VMOVNTPD_MEMqq_YMMqq =5147, +  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq =5147,
-  XED_IFORM_VMOVNTPS_MEMdq_XMMdq =5148, +  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq =5148,
-  XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 =5149, +  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5149,
-  XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 =5150, +  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5150,
-  XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 =5151, +  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5151,
-  XED_IFORM_VMOVNTPS_MEMqq_YMMqq =5152, +  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5152,
-  XED_IFORM_VMOVQ_GPR64q_XMMq =5153, +  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5153,
-  XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 =5154, +  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq =5154,
-  XED_IFORM_VMOVQ_MEMq_XMMq_7E =5155, +  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq =5155,
-  XED_IFORM_VMOVQ_MEMq_XMMq_D6 =5156, +  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5156,
-  XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 =5157, +  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5157,
-  XED_IFORM_VMOVQ_XMMdq_GPR64q =5158, +  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq =5158,
-  XED_IFORM_VMOVQ_XMMdq_MEMq_6E =5159, +  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq =5159,
-  XED_IFORM_VMOVQ_XMMdq_MEMq_7E =5160, +  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5160,
-  XED_IFORM_VMOVQ_XMMdq_XMMq_7E =5161, +  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5161,
-  XED_IFORM_VMOVQ_XMMdq_XMMq_D6 =5162, +  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5162,
-  XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 =5163, +  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5163,
-  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 =5164, +  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5164,
-  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 =5165, +  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5165,
-  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 =5166, +  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd =5166,
-  XED_IFORM_VMOVSD_MEMq_XMMq =5167, +  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd =5167,
-  XED_IFORM_VMOVSD_XMMdq_MEMq =5168, +  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5168,
-  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 =5169, +  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5169,
-  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 =5170, +  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5170,
-  XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 =5171, +  XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5171,
-  XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5172, +  XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5172,
-  XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 =5173, +  XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5173,
-  XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 =5174, +  XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5174,
-  XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5175, +  XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5175,
-  XED_IFORM_VMOVSHDUP_XMMdq_MEMdq =5176, +  XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5176,
-  XED_IFORM_VMOVSHDUP_XMMdq_XMMdq =5177, +  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq =5177,
-  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5178, +  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq =5178,
-  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5179, +  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5179,
-  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5180, +  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5180,
-  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5181, +  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5181,
-  XED_IFORM_VMOVSHDUP_YMMqq_MEMqq =5182, +  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5182,
-  XED_IFORM_VMOVSHDUP_YMMqq_YMMqq =5183, +  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5183,
-  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5184, +  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq =5184,
-  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5185, +  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq =5185,
-  XED_IFORM_VMOVSLDUP_XMMdq_MEMdq =5186, +  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5186,
-  XED_IFORM_VMOVSLDUP_XMMdq_XMMdq =5187, +  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5187,
-  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5188, +  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5188,
-  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5189, +  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5189,
-  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5190, +  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5190,
-  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5191, +  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5191,
-  XED_IFORM_VMOVSLDUP_YMMqq_MEMqq =5192, +  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5192,
-  XED_IFORM_VMOVSLDUP_YMMqq_YMMqq =5193, +  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5193,
-  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5194, +  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5194,
-  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5195, +  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq =5195,
-  XED_IFORM_VMOVSS_MEMd_XMMd =5196, +  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq =5196,
-  XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 =5197, +  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5197,
-  XED_IFORM_VMOVSS_XMMdq_MEMd =5198, +  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5198,
-  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 =5199, +  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5199,
-  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 =5200, +  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5200,
-  XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 =5201, +  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5201,
-  XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5202, +  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq =5202,
-  XED_IFORM_VMOVUPD_MEMdq_XMMdq =5203, +  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq =5203,
-  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 =5204, +  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5204,
-  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 =5205, +  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5205,
-  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 =5206, +  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq =5206,
-  XED_IFORM_VMOVUPD_MEMqq_YMMqq =5207, +  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq =5207,
-  XED_IFORM_VMOVUPD_XMMdq_MEMdq =5208, +  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5208,
-  XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 =5209, +  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5209,
-  XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 =5210, +  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5210,
-  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 =5211, +  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5211,
-  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 =5212, +  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5212,
-  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 =5213, +  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5213,
-  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 =5214, +  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd =5214,
-  XED_IFORM_VMOVUPD_YMMqq_MEMqq =5215, +  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd =5215,
-  XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 =5216, +  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5216,
-  XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 =5217, +  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5217,
-  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5218, +  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5218,
-  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5219, +  XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5219,
-  XED_IFORM_VMOVUPS_MEMdq_XMMdq =5220, +  XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5220,
-  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 =5221, +  XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5221,
-  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 =5222, +  XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5222,
-  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5223, +  XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5223,
-  XED_IFORM_VMOVUPS_MEMqq_YMMqq =5224, +  XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5224,
-  XED_IFORM_VMOVUPS_XMMdq_MEMdq =5225, +  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq =5225,
-  XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 =5226, +  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq =5226,
-  XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 =5227, +  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5227,
-  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 =5228, +  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5228,
-  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 =5229, +  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5229,
-  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 =5230, +  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5230,
-  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 =5231, +  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5231,
-  XED_IFORM_VMOVUPS_YMMqq_MEMqq =5232, +  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq =5232,
-  XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 =5233, +  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq =5233,
-  XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 =5234, +  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5234,
-  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5235, +  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5235,
-  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5236, +  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5236,
-  XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512 =5237, +  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5237,
-  XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512 =5238, +  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5238,
-  XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512 =5239, +  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5239,
-  XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512 =5240, +  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5240,
-  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb =5241, +  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5241,
-  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb =5242, +  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5242,
-  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb =5243, +  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq =5243,
-  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb =5244, +  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq =5244,
-  XED_IFORM_VMPTRLD_MEMq =5245, +  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5245,
-  XED_IFORM_VMPTRST_MEMq =5246, +  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5246,
-  XED_IFORM_VMREAD_GPR32_GPR32 =5247, +  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5247,
-  XED_IFORM_VMREAD_GPR64_GPR64 =5248, +  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5248,
-  XED_IFORM_VMREAD_MEMd_GPR32 =5249, +  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5249,
-  XED_IFORM_VMREAD_MEMq_GPR64 =5250, +  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq =5250,
-  XED_IFORM_VMRESUME =5251, +  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq =5251,
-  XED_IFORM_VMRUN_ArAX =5252, +  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5252,
-  XED_IFORM_VMSAVE =5253, +  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5253,
-  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq =5254, +  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq =5254,
-  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq =5255, +  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq =5255,
-  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5256, +  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5256,
-  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5257, +  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5257,
-  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5258, +  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5258,
-  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5259, +  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5259,
-  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq =5260, +  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5260,
-  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq =5261, +  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5261,
-  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5262, +  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd =5262,
-  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5263, +  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd =5263,
-  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5264, +  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5264,
-  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5265, +  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5265,
-  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5266, +  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5266,
-  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5267, +  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =5267,
-  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5268, +  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =5268,
-  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5269, +  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =5269,
-  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq =5270, +  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =5270,
-  XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq =5271, +  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =5271,
-  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5272, +  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =5272,
-  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5273, +  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =5273,
-  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5274, +  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =5274,
-  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5275, +  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =5275,
-  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq =5276, +  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =5276,
-  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq =5277, +  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =5277,
-  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5278, +  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =5278,
-  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5279, +  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq =5279,
-  XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq =5280, +  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq =5280,
-  XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq =5281, +  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq =5281,
-  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5282, +  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd =5282,
-  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5283, +  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd =5283,
-  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5284, +  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd =5284,
-  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5285, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128 =5285,
-  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd =5286, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256 =5286,
-  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd =5287, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512 =5287,
-  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5288, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512 =5288,
-  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5289, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512 =5289,
-  XED_IFORM_VMWRITE_GPR32_GPR32 =5290, +  XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512 =5290,
-  XED_IFORM_VMWRITE_GPR32_MEMd =5291, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 =5291,
-  XED_IFORM_VMWRITE_GPR64_GPR64 =5292, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 =5292,
-  XED_IFORM_VMWRITE_GPR64_MEMq =5293, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 =5293,
-  XED_IFORM_VMXOFF =5294, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =5294,
-  XED_IFORM_VMXON_MEMq =5295, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 =5295,
-  XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq =5296, +  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 =5296,
-  XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq =5297, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 =5297,
-  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5298, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 =5298,
-  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5299, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 =5299,
-  XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq =5300, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =5300,
-  XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq =5301, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 =5301,
-  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5302, +  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 =5302,
-  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5303, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 =5303,
-  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5304, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 =5304,
-  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5305, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 =5305,
-  XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq =5306, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =5306,
-  XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq =5307, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 =5307,
-  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5308, +  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 =5308,
-  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5309, +  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 =5309,
-  XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq =5310, +  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =5310,
-  XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq =5311, +  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 =5311,
-  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5312, +  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =5312,
-  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5313, +  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 =5313,
-  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5314, +  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =5314,
-  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5315, +  XED_IFORM_VFRCZPD_XMMdq_MEMdq =5315,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 =5316, +  XED_IFORM_VFRCZPD_XMMdq_XMMdq =5316,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 =5317, +  XED_IFORM_VFRCZPD_YMMqq_MEMqq =5317,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 =5318, +  XED_IFORM_VFRCZPD_YMMqq_YMMqq =5318,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 =5319, +  XED_IFORM_VFRCZPS_XMMdq_MEMdq =5319,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 =5320, +  XED_IFORM_VFRCZPS_XMMdq_XMMdq =5320,
-  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 =5321, +  XED_IFORM_VFRCZPS_YMMqq_MEMqq =5321,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 =5322, +  XED_IFORM_VFRCZPS_YMMqq_YMMqq =5322,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 =5323, +  XED_IFORM_VFRCZSD_XMMdq_MEMq =5323,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 =5324, +  XED_IFORM_VFRCZSD_XMMdq_XMMq =5324,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 =5325, +  XED_IFORM_VFRCZSS_XMMdq_MEMd =5325,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 =5326, +  XED_IFORM_VFRCZSS_XMMdq_XMMd =5326,
-  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 =5327, +  XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =5327,
-  XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5328, +  XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 =5328,
-  XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5329, +  XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =5329,
-  XED_IFORM_VPABSB_XMMdq_MEMdq =5330, +  XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 =5330,
-  XED_IFORM_VPABSB_XMMdq_XMMdq =5331, +  XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =5331,
-  XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 =5332, +  XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =5332,
-  XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 =5333, +  XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 =5333,
-  XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 =5334, +  XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 =5334,
-  XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 =5335, +  XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 =5335,
-  XED_IFORM_VPABSB_YMMqq_MEMqq =5336, +  XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 =5336,
-  XED_IFORM_VPABSB_YMMqq_YMMqq =5337, +  XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =5337,
-  XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 =5338, +  XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =5338,
-  XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 =5339, +  XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =5339,
-  XED_IFORM_VPABSD_XMMdq_MEMdq =5340, +  XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =5340,
-  XED_IFORM_VPABSD_XMMdq_XMMdq =5341, +  XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =5341,
-  XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 =5342, +  XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =5342,
-  XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 =5343, +  XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =5343,
-  XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 =5344, +  XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =5344,
-  XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 =5345, +  XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =5345,
-  XED_IFORM_VPABSD_YMMqq_MEMqq =5346, +  XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 =5346,
-  XED_IFORM_VPABSD_YMMqq_YMMqq =5347, +  XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =5347,
-  XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 =5348, +  XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 =5348,
-  XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 =5349, +  XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =5349,
-  XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 =5350, +  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =5350,
-  XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 =5351, +  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 =5351,
-  XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 =5352, +  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 =5352,
-  XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 =5353, +  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 =5353,
-  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 =5354, +  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 =5354,
-  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 =5355, +  XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512 =5355,
-  XED_IFORM_VPABSW_XMMdq_MEMdq =5356, +  XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512 =5356,
-  XED_IFORM_VPABSW_XMMdq_XMMdq =5357, +  XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512 =5357,
-  XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 =5358, +  XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512 =5358,
-  XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 =5359, +  XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512 =5359,
-  XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 =5360, +  XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512 =5360,
-  XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 =5361, +  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 =5361,
-  XED_IFORM_VPABSW_YMMqq_MEMqq =5362, +  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 =5362,
-  XED_IFORM_VPABSW_YMMqq_YMMqq =5363, +  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 =5363,
-  XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 =5364, +  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 =5364,
-  XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 =5365, +  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC =5365,
-  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq =5366, +  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5366,
-  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq =5367, +  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5367,
-  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 =5368, +  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 =5368,
-  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 =5369, +  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 =5369,
-  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 =5370, +  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 =5370,
-  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 =5371, +  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 =5371,
-  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq =5372, +  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC =5372,
-  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq =5373, +  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =5373,
-  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 =5374, +  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =5374,
-  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 =5375, +  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 =5375,
-  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq =5376, +  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 =5376,
-  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq =5377, +  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 =5377,
-  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 =5378, +  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 =5378,
-  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 =5379, +  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC =5379,
-  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 =5380, +  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5380,
-  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 =5381, +  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5381,
-  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq =5382, +  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5382,
-  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq =5383, +  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5383,
-  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 =5384, +  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5384,
-  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 =5385, +  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5385,
-  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq =5386, +  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5386,
-  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq =5387, +  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5387,
-  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 =5388, +  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5388,
-  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 =5389, +  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5389,
-  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq =5390, +  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5390,
-  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq =5391, +  XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512 =5391,
-  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 =5392, +  XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512 =5392,
-  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 =5393, +  XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512 =5393,
-  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 =5394, +  XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512 =5394,
-  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 =5395, +  XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512 =5395,
-  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq =5396, +  XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512 =5396,
-  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq =5397, +  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5397,
-  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 =5398, +  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =5398,
-  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 =5399, +  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5399,
-  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq =5400, +  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =5400,
-  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq =5401, +  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC =5401,
-  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 =5402, +  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5402,
-  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 =5403, +  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =5403,
-  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 =5404, +  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5404,
-  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 =5405, +  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =5405,
-  XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq =5406, +  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5406,
-  XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq =5407, +  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =5407,
-  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5408, +  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC =5408,
-  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5409, +  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5409,
-  XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq =5410, +  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =5410,
-  XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq =5411, +  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5411,
-  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5412, +  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =5412,
-  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5413, +  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5413,
-  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5414, +  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =5414,
-  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5415, +  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC =5415,
-  XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq =5416, +  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5416,
-  XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq =5417, +  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =5417,
-  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5418, +  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5418,
-  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5419, +  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5419,
-  XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq =5420, +  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =5420,
-  XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq =5421, +  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5421,
-  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5422, +  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5422,
-  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5423, +  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC =5423,
-  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5424, +  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5424,
-  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5425, +  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5425,
-  XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq =5426, +  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =5426,
-  XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq =5427, +  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =5427,
-  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5428, +  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =5428,
-  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5429, +  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 =5429,
-  XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq =5430, +  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 =5430,
-  XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq =5431, +  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =5431,
-  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5432, +  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =5432,
-  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5433, +  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 =5433,
-  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5434, +  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 =5434,
-  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5435, +  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =5435,
-  XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq =5436, +  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =5436,
-  XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq =5437, +  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =5437,
-  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =5438, +  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =5438,
-  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =5439, +  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 =5439,
-  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =5440, +  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 =5440,
-  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =5441, +  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =5441,
-  XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq =5442, +  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =5442,
-  XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq =5443, +  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 =5443,
-  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =5444, +  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 =5444,
-  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =5445, +  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =5445,
-  XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq =5446, +  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =5446,
-  XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq =5447, +  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5447,
-  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =5448, +  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5448,
-  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =5449, +  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 =5449,
-  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =5450, +  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 =5450,
-  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =5451, +  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5451,
-  XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq =5452, +  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5452,
-  XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq =5453, +  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 =5453,
-  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =5454, +  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 =5454,
-  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =5455, +  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5455,
-  XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq =5456, +  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5456,
-  XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq =5457, +  XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq =5457,
-  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5458, +  XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq =5458,
-  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5459, +  XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq =5459,
-  XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq =5460, +  XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq =5460,
-  XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq =5461, +  XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq =5461,
-  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5462, +  XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq =5462,
-  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5463, +  XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq =5463,
-  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5464, +  XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq =5464,
-  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5465, +  XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq =5465,
-  XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq =5466, +  XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq =5466,
-  XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq =5467, +  XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq =5467,
-  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5468, +  XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq =5468,
-  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5469, +  XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq =5469,
-  XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq =5470, +  XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq =5470,
-  XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq =5471, +  XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq =5471,
-  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5472, +  XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq =5472,
-  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5473, +  XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb =5473,
-  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5474, +  XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb =5474,
-  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5475, +  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =5475,
-  XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq =5476, +  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 =5476,
-  XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq =5477, +  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5477,
-  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5478, +  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 =5478,
-  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5479, +  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5479,
-  XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq =5480, +  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 =5480,
-  XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq =5481, +  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =5481,
-  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5482, +  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 =5482,
-  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5483, +  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5483,
-  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5484, +  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 =5484,
-  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5485, +  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5485,
-  XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb =5486, +  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 =5486,
-  XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb =5487, +  XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb =5487,
-  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =5488, +  XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb =5488,
-  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =5489, +  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =5489,
-  XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb =5490, +  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 =5490,
-  XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb =5491, +  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =5491,
-  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =5492, +  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 =5492,
-  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =5493, +  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =5493,
-  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =5494, +  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 =5494,
-  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =5495, +  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =5495,
-  XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq =5496, +  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 =5496,
-  XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq =5497, +  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =5497,
-  XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq =5498, +  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 =5498,
-  XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq =5499, +  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =5499,
-  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5500, +  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 =5500,
-  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5501, +  XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb =5501,
-  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5502, +  XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb =5502,
-  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5503, +  XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 =5503,
-  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5504, +  XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 =5504,
-  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5505, +  XED_IFORM_VLDDQU_XMMdq_MEMdq =5505,
-  XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq =5506, +  XED_IFORM_VLDDQU_YMMqq_MEMqq =5506,
-  XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq =5507, +  XED_IFORM_VLDMXCSR_MEMd =5507,
-  XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq =5508, +  XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub =5508,
-  XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq =5509, +  XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq =5509,
-  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5510, +  XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq =5510,
-  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5511, +  XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq =5511,
-  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5512, +  XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq =5512,
-  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5513, +  XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq =5513,
-  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5514, +  XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq =5514,
-  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5515, +  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq =5515,
-  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5516, +  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq =5516,
-  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5517, +  XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5517,
-  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5518, +  XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5518,
-  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5519, +  XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5519,
-  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5520, +  XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5520,
-  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5521, +  XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5521,
-  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5522, +  XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5522,
-  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5523, +  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq =5523,
-  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5524, +  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq =5524,
-  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5525, +  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5525,
-  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5526, +  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5526,
-  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5527, +  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5527,
-  XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq =5528, +  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5528,
-  XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq =5529, +  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5529,
-  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5530, +  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq =5530,
-  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5531, +  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq =5531,
-  XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq =5532, +  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5532,
-  XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq =5533, +  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5533,
-  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5534, +  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5534,
-  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5535, +  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5535,
-  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5536, +  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5536,
-  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5537, +  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5537,
-  XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq =5538, +  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5538,
-  XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq =5539, +  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5539,
-  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5540, +  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5540,
-  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5541, +  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq =5541,
-  XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq =5542, +  XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq =5542,
-  XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq =5543, +  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5543,
-  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5544, +  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5544,
-  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5545, +  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5545,
-  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5546, +  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5546,
-  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5547, +  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5547,
-  XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb =5548, +  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq =5548,
-  XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb =5549, +  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq =5549,
-  XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb =5550, +  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5550,
-  XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb =5551, +  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5551,
-  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5552, +  XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq =5552,
-  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5553, +  XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq =5553,
-  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5554, +  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5554,
-  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5555, +  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5555,
-  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5556, +  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5556,
-  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5557, +  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5557,
-  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5558, +  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5558,
-  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5559, +  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5559,
-  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5560, +  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd =5560,
-  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5561, +  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd =5561,
-  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5562, +  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5562,
-  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5563, +  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5563,
-  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5564, +  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5564,
-  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5565, +  XED_IFORM_VMCALL =5565,
-  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5566, +  XED_IFORM_VMCLEAR_MEMq =5566,
-  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5567, +  XED_IFORM_VMFUNC =5567,
-  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5568, +  XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 =5568,
-  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5569, +  XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 =5569,
-  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5570, +  XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 =5570,
-  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5571, +  XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 =5571,
-  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5572, +  XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 =5572,
-  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5573, +  XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 =5573,
-  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5574, +  XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5574,
-  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5575, +  XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5575,
-  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq =5576, +  XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =5576,
-  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq =5577, +  XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =5577,
-  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq =5578, +  XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5578,
-  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq =5579, +  XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =5579,
-  XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb =5580, +  XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5580,
-  XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb =5581, +  XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5581,
-  XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb =5582, +  XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 =5582,
-  XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb =5583, +  XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 =5583,
-  XED_IFORM_VPBROADCASTB_XMMdq_MEMb =5584, +  XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 =5584,
-  XED_IFORM_VPBROADCASTB_XMMdq_XMMb =5585, +  XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 =5585,
-  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 =5586, +  XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5586,
-  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 =5587, +  XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5587,
-  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 =5588, +  XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =5588,
-  XED_IFORM_VPBROADCASTB_YMMqq_MEMb =5589, +  XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =5589,
-  XED_IFORM_VPBROADCASTB_YMMqq_XMMb =5590, +  XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5590,
-  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 =5591, +  XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =5591,
-  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 =5592, +  XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5592,
-  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 =5593, +  XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5593,
-  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 =5594, +  XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5594,
-  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 =5595, +  XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5595,
-  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 =5596, +  XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5596,
-  XED_IFORM_VPBROADCASTD_XMMdq_MEMd =5597, +  XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5597,
-  XED_IFORM_VPBROADCASTD_XMMdq_XMMd =5598, +  XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5598,
-  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 =5599, +  XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5599,
-  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 =5600, +  XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5600,
-  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 =5601, +  XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5601,
-  XED_IFORM_VPBROADCASTD_YMMqq_MEMd =5602, +  XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5602,
-  XED_IFORM_VPBROADCASTD_YMMqq_XMMd =5603, +  XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5603,
-  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 =5604, +  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq =5604,
-  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 =5605, +  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq =5605,
-  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 =5606, +  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5606,
-  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 =5607, +  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5607,
-  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 =5608, +  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5608,
-  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 =5609, +  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5609,
-  XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 =5610, +  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5610,
-  XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 =5611, +  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq =5611,
-  XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD =5612, +  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq =5612,
-  XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 =5613, +  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5613,
-  XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 =5614, +  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5614,
-  XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD =5615, +  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5615,
-  XED_IFORM_VPBROADCASTQ_XMMdq_MEMq =5616, +  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5616,
-  XED_IFORM_VPBROADCASTQ_XMMdq_XMMq =5617, +  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5617,
-  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 =5618, +  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5618,
-  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 =5619, +  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5619,
-  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 =5620, +  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5620,
-  XED_IFORM_VPBROADCASTQ_YMMqq_MEMq =5621, +  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5621,
-  XED_IFORM_VPBROADCASTQ_YMMqq_XMMq =5622, +  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq =5622,
-  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 =5623, +  XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq =5623,
-  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 =5624, +  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5624,
-  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 =5625, +  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5625,
-  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 =5626, +  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5626,
-  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =5627, +  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5627,
-  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 =5628, +  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5628,
-  XED_IFORM_VPBROADCASTW_XMMdq_MEMw =5629, +  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq =5629,
-  XED_IFORM_VPBROADCASTW_XMMdq_XMMw =5630, +  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq =5630,
-  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 =5631, +  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5631,
-  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 =5632, +  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5632,
-  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 =5633, +  XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq =5633,
-  XED_IFORM_VPBROADCASTW_YMMqq_MEMw =5634, +  XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq =5634,
-  XED_IFORM_VPBROADCASTW_YMMqq_XMMw =5635, +  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5635,
-  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 =5636, +  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5636,
-  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 =5637, +  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5637,
-  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 =5638, +  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5638,
-  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 =5639, +  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5639,
-  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 =5640, +  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5640,
-  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 =5641, +  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd =5641,
-  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb =5642, +  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd =5642,
-  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb =5643, +  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5643,
-  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 =5644, +  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5644,
-  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 =5645, +  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5645,
-  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 =5646, +  XED_IFORM_VMLAUNCH =5646,
-  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 =5647, +  XED_IFORM_VMLOAD_ArAX =5647,
-  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 =5648, +  XED_IFORM_VMMCALL =5648,
-  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 =5649, +  XED_IFORM_VMOVAPD_MEMdq_XMMdq =5649,
-  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 =5650, +  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 =5650,
-  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 =5651, +  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 =5651,
-  XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq =5652, +  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 =5652,
-  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq =5653, +  XED_IFORM_VMOVAPD_MEMqq_YMMqq =5653,
-  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq =5654, +  XED_IFORM_VMOVAPD_XMMdq_MEMdq =5654,
-  XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq =5655, +  XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 =5655,
-  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq =5656, +  XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 =5656,
-  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq =5657, +  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 =5657,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 =5658, +  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 =5658,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 =5659, +  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 =5659,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 =5660, +  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 =5660,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 =5661, +  XED_IFORM_VMOVAPD_YMMqq_MEMqq =5661,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 =5662, +  XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 =5662,
-  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 =5663, +  XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 =5663,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 =5664, +  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5664,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 =5665, +  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5665,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 =5666, +  XED_IFORM_VMOVAPS_MEMdq_XMMdq =5666,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 =5667, +  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 =5667,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 =5668, +  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 =5668,
-  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 =5669, +  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5669,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =5670, +  XED_IFORM_VMOVAPS_MEMqq_YMMqq =5670,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =5671, +  XED_IFORM_VMOVAPS_XMMdq_MEMdq =5671,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =5672, +  XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 =5672,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =5673, +  XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 =5673,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =5674, +  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 =5674,
-  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =5675, +  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 =5675,
-  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq =5676, +  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 =5676,
-  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq =5677, +  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 =5677,
-  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq =5678, +  XED_IFORM_VMOVAPS_YMMqq_MEMqq =5678,
-  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq =5679, +  XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 =5679,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =5680, +  XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 =5680,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =5681, +  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5681,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =5682, +  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5682,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =5683, +  XED_IFORM_VMOVD_GPR32d_XMMd =5683,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =5684, +  XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 =5684,
-  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =5685, +  XED_IFORM_VMOVD_MEMd_XMMd =5685,
-  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq =5686, +  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 =5686,
-  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq =5687, +  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC =5687,
-  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq =5688, +  XED_IFORM_VMOVD_XMMdq_GPR32d =5688,
-  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq =5689, +  XED_IFORM_VMOVD_XMMdq_MEMd =5689,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =5690, +  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 =5690,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =5691, +  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 =5691,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =5692, +  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC =5692,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =5693, +  XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC =5693,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =5694, +  XED_IFORM_VMOVDDUP_XMMdq_MEMq =5694,
-  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =5695, +  XED_IFORM_VMOVDDUP_XMMdq_XMMq =5695,
-  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq =5696, +  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 =5696,
-  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq =5697, +  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 =5697,
-  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq =5698, +  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 =5698,
-  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq =5699, +  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 =5699,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =5700, +  XED_IFORM_VMOVDDUP_YMMqq_MEMqq =5700,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =5701, +  XED_IFORM_VMOVDDUP_YMMqq_YMMqq =5701,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =5702, +  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 =5702,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =5703, +  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 =5703,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =5704, +  XED_IFORM_VMOVDQA_MEMdq_XMMdq =5704,
-  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =5705, +  XED_IFORM_VMOVDQA_MEMqq_YMMqq =5705,
-  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq =5706, +  XED_IFORM_VMOVDQA_XMMdq_MEMdq =5706,
-  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq =5707, +  XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F =5707,
-  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq =5708, +  XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F =5708,
-  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq =5709, +  XED_IFORM_VMOVDQA_YMMqq_MEMqq =5709,
-  XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb =5710, +  XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F =5710,
-  XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb =5711, +  XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F =5711,
-  XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb =5712, +  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 =5712,
-  XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb =5713, +  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 =5713,
-  XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb =5714, +  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 =5714,
-  XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb =5715, +  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 =5715,
-  XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb =5716, +  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 =5716,
-  XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb =5717, +  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 =5717,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =5718, +  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 =5718,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =5719, +  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 =5719,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =5720, +  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5720,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =5721, +  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 =5721,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =5722, +  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 =5722,
-  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =5723, +  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 =5723,
-  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq =5724, +  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 =5724,
-  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq =5725, +  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 =5725,
-  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq =5726, +  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 =5726,
-  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq =5727, +  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 =5727,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 =5728, +  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 =5728,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 =5729, +  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5729,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 =5730, +  XED_IFORM_VMOVDQU_MEMdq_XMMdq =5730,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 =5731, +  XED_IFORM_VMOVDQU_MEMqq_YMMqq =5731,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 =5732, +  XED_IFORM_VMOVDQU_XMMdq_MEMdq =5732,
-  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 =5733, +  XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F =5733,
-  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq =5734, +  XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F =5734,
-  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq =5735, +  XED_IFORM_VMOVDQU_YMMqq_MEMqq =5735,
-  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq =5736, +  XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F =5736,
-  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq =5737, +  XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F =5737,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 =5738, +  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 =5738,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 =5739, +  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 =5739,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 =5740, +  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 =5740,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 =5741, +  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 =5741,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 =5742, +  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 =5742,
-  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 =5743, +  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 =5743,
-  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq =5744, +  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 =5744,
-  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq =5745, +  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 =5745,
-  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq =5746, +  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 =5746,
-  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq =5747, +  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 =5747,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =5748, +  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 =5748,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =5749, +  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 =5749,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =5750, +  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 =5750,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =5751, +  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 =5751,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =5752, +  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 =5752,
-  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =5753, +  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 =5753,
-  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq =5754, +  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 =5754,
-  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq =5755, +  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5755,
-  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq =5756, +  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 =5756,
-  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq =5757, +  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 =5757,
-  XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb =5758, +  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 =5758,
-  XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb =5759, +  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 =5759,
-  XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb =5760, +  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 =5760,
-  XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb =5761, +  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 =5761,
-  XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb =5762, +  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 =5762,
-  XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb =5763, +  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 =5763,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 =5764, +  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5764,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 =5765, +  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 =5765,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 =5766, +  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 =5766,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 =5767, +  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 =5767,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 =5768, +  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 =5768,
-  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 =5769, +  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 =5769,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =5770, +  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 =5770,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =5771, +  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 =5771,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =5772, +  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 =5772,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =5773, +  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 =5773,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =5774, +  XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq =5774,
-  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =5775, +  XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 =5775,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =5776, +  XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 =5776,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =5777, +  XED_IFORM_VMOVHPD_MEMq_XMMdq =5777,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =5778, +  XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq =5778,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =5779, +  XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 =5779,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =5780, +  XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 =5780,
-  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =5781, +  XED_IFORM_VMOVHPS_MEMq_XMMdq =5781,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =5782, +  XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq =5782,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =5783, +  XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 =5783,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =5784, +  XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq =5784,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =5785, +  XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 =5785,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =5786, +  XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 =5786,
-  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =5787, +  XED_IFORM_VMOVLPD_MEMq_XMMq =5787,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =5788, +  XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq =5788,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =5789, +  XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 =5789,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =5790, +  XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 =5790,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =5791, +  XED_IFORM_VMOVLPS_MEMq_XMMq =5791,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =5792, +  XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq =5792,
-  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =5793, +  XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 =5793,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 =5794, +  XED_IFORM_VMOVMSKPD_GPR32d_XMMdq =5794,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 =5795, +  XED_IFORM_VMOVMSKPD_GPR32d_YMMqq =5795,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 =5796, +  XED_IFORM_VMOVMSKPS_GPR32d_XMMdq =5796,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 =5797, +  XED_IFORM_VMOVMSKPS_GPR32d_YMMqq =5797,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 =5798, +  XED_IFORM_VMOVNTDQ_MEMdq_XMMdq =5798,
-  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 =5799, +  XED_IFORM_VMOVNTDQ_MEMqq_YMMqq =5799,
-  XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb =5800, +  XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 =5800,
-  XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb =5801, +  XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 =5801,
-  XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb =5802, +  XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 =5802,
-  XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb =5803, +  XED_IFORM_VMOVNTDQA_XMMdq_MEMdq =5803,
-  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 =5804, +  XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 =5804,
-  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 =5805, +  XED_IFORM_VMOVNTDQA_YMMqq_MEMqq =5805,
-  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 =5806, +  XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 =5806,
-  XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 =5807, +  XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 =5807,
-  XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 =5808, +  XED_IFORM_VMOVNTPD_MEMdq_XMMdq =5808,
-  XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 =5809, +  XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 =5809,
-  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 =5810, +  XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 =5810,
-  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 =5811, +  XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 =5811,
-  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 =5812, +  XED_IFORM_VMOVNTPD_MEMqq_YMMqq =5812,
-  XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 =5813, +  XED_IFORM_VMOVNTPS_MEMdq_XMMdq =5813,
-  XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 =5814, +  XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 =5814,
-  XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 =5815, +  XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 =5815,
-  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 =5816, +  XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 =5816,
-  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 =5817, +  XED_IFORM_VMOVNTPS_MEMqq_YMMqq =5817,
-  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 =5818, +  XED_IFORM_VMOVQ_GPR64q_XMMq =5818,
-  XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 =5819, +  XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 =5819,
-  XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 =5820, +  XED_IFORM_VMOVQ_MEMq_XMMq_7E =5820,
-  XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =5821, +  XED_IFORM_VMOVQ_MEMq_XMMq_D6 =5821,
-  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 =5822, +  XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 =5822,
-  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 =5823, +  XED_IFORM_VMOVQ_XMMdq_GPR64q =5823,
-  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 =5824, +  XED_IFORM_VMOVQ_XMMdq_MEMq_6E =5824,
-  XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 =5825, +  XED_IFORM_VMOVQ_XMMdq_MEMq_7E =5825,
-  XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 =5826, +  XED_IFORM_VMOVQ_XMMdq_XMMq_7E =5826,
-  XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 =5827, +  XED_IFORM_VMOVQ_XMMdq_XMMq_D6 =5827,
-  XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb =5828, +  XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 =5828,
-  XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb =5829, +  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 =5829,
-  XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb =5830, +  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 =5830,
-  XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb =5831, +  XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512 =5831,
-  XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb =5832, +  XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512 =5832,
-  XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb =5833, +  XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512 =5833,
-  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb =5834, +  XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512 =5834,
-  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb =5835, +  XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512 =5835,
-  XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb =5836, +  XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512 =5836,
-  XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb =5837, +  XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512 =5837,
-  XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb =5838, +  XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512 =5838,
-  XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb =5839, +  XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512 =5839,
-  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 =5840, +  XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512 =5840,
-  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 =5841, +  XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512 =5841,
-  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 =5842, +  XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512 =5842,
-  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 =5843, +  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 =5843,
-  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =5844, +  XED_IFORM_VMOVSD_MEMq_XMMq =5844,
-  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =5845, +  XED_IFORM_VMOVSD_XMMdq_MEMq =5845,
-  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 =5846, +  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 =5846,
-  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 =5847, +  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 =5847,
-  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 =5848, +  XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 =5848,
-  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 =5849, +  XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5849,
-  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =5850, +  XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 =5850,
-  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =5851, +  XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 =5851,
-  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8 =5852, +  XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5852,
-  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8 =5853, +  XED_IFORM_VMOVSHDUP_XMMdq_MEMdq =5853,
-  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8 =5854, +  XED_IFORM_VMOVSHDUP_XMMdq_XMMdq =5854,
-  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8 =5855, +  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5855,
-  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 =5856, +  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5856,
-  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 =5857, +  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5857,
-  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 =5858, +  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5858,
-  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 =5859, +  XED_IFORM_VMOVSHDUP_YMMqq_MEMqq =5859,
-  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8 =5860, +  XED_IFORM_VMOVSHDUP_YMMqq_YMMqq =5860,
-  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8 =5861, +  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5861,
-  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8 =5862, +  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5862,
-  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8 =5863, +  XED_IFORM_VMOVSLDUP_XMMdq_MEMdq =5863,
-  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 =5864, +  XED_IFORM_VMOVSLDUP_XMMdq_XMMdq =5864,
-  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 =5865, +  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5865,
-  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 =5866, +  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5866,
-  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 =5867, +  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5867,
-  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =5868, +  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5868,
-  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =5869, +  XED_IFORM_VMOVSLDUP_YMMqq_MEMqq =5869,
-  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32 =5870, +  XED_IFORM_VMOVSLDUP_YMMqq_YMMqq =5870,
-  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32 =5871, +  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5871,
-  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =5872, +  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5872,
-  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =5873, +  XED_IFORM_VMOVSS_MEMd_XMMd =5873,
-  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32 =5874, +  XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 =5874,
-  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32 =5875, +  XED_IFORM_VMOVSS_XMMdq_MEMd =5875,
-  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =5876, +  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 =5876,
-  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =5877, +  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 =5877,
-  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =5878, +  XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 =5878,
-  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =5879, +  XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5879,
-  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32 =5880, +  XED_IFORM_VMOVUPD_MEMdq_XMMdq =5880,
-  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32 =5881, +  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 =5881,
-  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =5882, +  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 =5882,
-  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =5883, +  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 =5883,
-  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32 =5884, +  XED_IFORM_VMOVUPD_MEMqq_YMMqq =5884,
-  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32 =5885, +  XED_IFORM_VMOVUPD_XMMdq_MEMdq =5885,
-  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =5886, +  XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 =5886,
-  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =5887, +  XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 =5887,
-  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8 =5888, +  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 =5888,
-  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8 =5889, +  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 =5889,
-  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8 =5890, +  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 =5890,
-  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8 =5891, +  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 =5891,
-  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 =5892, +  XED_IFORM_VMOVUPD_YMMqq_MEMqq =5892,
-  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 =5893, +  XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 =5893,
-  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 =5894, +  XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 =5894,
-  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 =5895, +  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5895,
-  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =5896, +  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5896,
-  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =5897, +  XED_IFORM_VMOVUPS_MEMdq_XMMdq =5897,
-  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32 =5898, +  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 =5898,
-  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32 =5899, +  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 =5899,
-  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =5900, +  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5900,
-  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =5901, +  XED_IFORM_VMOVUPS_MEMqq_YMMqq =5901,
-  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32 =5902, +  XED_IFORM_VMOVUPS_XMMdq_MEMdq =5902,
-  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32 =5903, +  XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 =5903,
-  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5904, +  XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 =5904,
-  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =5905, +  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 =5905,
-  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =5906, +  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 =5906,
-  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =5907, +  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 =5907,
-  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32 =5908, +  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 =5908,
-  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32 =5909, +  XED_IFORM_VMOVUPS_YMMqq_MEMqq =5909,
-  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =5910, +  XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 =5910,
-  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =5911, +  XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 =5911,
-  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32 =5912, +  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5912,
-  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32 =5913, +  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5913,
-  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5914, +  XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512 =5914,
-  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =5915, +  XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512 =5915,
-  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16 =5916, +  XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC =5916,
-  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16 =5917, +  XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512 =5917,
-  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16 =5918, +  XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512 =5918,
-  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16 =5919, +  XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC =5919,
-  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 =5920, +  XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC =5920,
-  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 =5921, +  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb =5921,
-  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 =5922, +  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb =5922,
-  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 =5923, +  XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =5923,
-  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16 =5924, +  XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =5924,
-  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16 =5925, +  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb =5925,
-  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16 =5926, +  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb =5926,
-  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16 =5927, +  XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =5927,
-  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 =5928, +  XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =5928,
-  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 =5929, +  XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =5929,
-  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 =5930, +  XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =5930,
-  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 =5931, +  XED_IFORM_VMPTRLD_MEMq =5931,
-  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16 =5932, +  XED_IFORM_VMPTRST_MEMq =5932,
-  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16 =5933, +  XED_IFORM_VMREAD_GPR32_GPR32 =5933,
-  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16 =5934, +  XED_IFORM_VMREAD_GPR64_GPR64 =5934,
-  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16 =5935, +  XED_IFORM_VMREAD_MEMd_GPR32 =5935,
-  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 =5936, +  XED_IFORM_VMREAD_MEMq_GPR64 =5936,
-  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 =5937, +  XED_IFORM_VMRESUME =5937,
-  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 =5938, +  XED_IFORM_VMRUN_ArAX =5938,
-  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 =5939, +  XED_IFORM_VMSAVE =5939,
-  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb =5940, +  XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5940,
-  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb =5941, +  XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5941,
-  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb =5942, +  XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5942,
-  XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb =5943, +  XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5943,
-  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5944, +  XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5944,
-  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5945, +  XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5945,
-  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5946, +  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq =5946,
-  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5947, +  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq =5947,
-  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5948, +  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5948,
-  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5949, +  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5949,
-  XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq =5950, +  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5950,
-  XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq =5951, +  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5951,
-  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5952, +  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =5952,
-  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5953, +  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq =5953,
-  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5954, +  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq =5954,
-  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5955, +  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5955,
-  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5956, +  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5956,
-  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5957, +  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5957,
-  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5958, +  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5958,
-  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5959, +  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5959,
-  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5960, +  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5960,
-  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5961, +  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =5961,
-  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5962, +  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5962,
-  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5963, +  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5963,
-  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5964, +  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq =5964,
-  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5965, +  XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq =5965,
-  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5966, +  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5966,
-  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5967, +  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5967,
-  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5968, +  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5968,
-  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5969, +  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5969,
-  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5970, +  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =5970,
-  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5971, +  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq =5971,
-  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5972, +  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq =5972,
-  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5973, +  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5973,
-  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5974, +  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5974,
-  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5975, +  XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq =5975,
-  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5976, +  XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq =5976,
-  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5977, +  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5977,
-  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5978, +  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5978,
-  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5979, +  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =5979,
-  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5980, +  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5980,
-  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5981, +  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5981,
-  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5982, +  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =5982,
-  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5983, +  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd =5983,
-  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5984, +  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd =5984,
-  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5985, +  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5985,
-  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5986, +  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5986,
-  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5987, +  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =5987,
-  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5988, +  XED_IFORM_VMWRITE_GPR32_GPR32 =5988,
-  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5989, +  XED_IFORM_VMWRITE_GPR32_MEMd =5989,
-  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5990, +  XED_IFORM_VMWRITE_GPR64_GPR64 =5990,
-  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5991, +  XED_IFORM_VMWRITE_GPR64_MEMq =5991,
-  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =5992, +  XED_IFORM_VMXOFF =5992,
-  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =5993, +  XED_IFORM_VMXON_MEMq =5993,
-  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =5994, +  XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq =5994,
-  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =5995, +  XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq =5995,
-  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =5996, +  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5996,
-  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =5997, +  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5997,
-  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =5998, +  XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq =5998,
-  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =5999, +  XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq =5999,
-  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =6000, +  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6000,
-  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =6001, +  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6001,
-  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =6002, +  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6002,
-  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =6003, +  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6003,
-  XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb =6004, +  XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq =6004,
-  XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb =6005, +  XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq =6005,
-  XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq =6006, +  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6006,
-  XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq =6007, +  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6007,
-  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6008, +  XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq =6008,
-  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =6009, +  XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq =6009,
-  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6010, +  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6010,
-  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6011, +  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6011,
-  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6012, +  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6012,
-  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6013, +  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6013,
-  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6014, +  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 =6014,
-  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6015, +  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 =6015,
-  XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb =6016, +  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 =6016,
-  XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb =6017, +  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 =6017,
-  XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq =6018, +  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 =6018,
-  XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq =6019, +  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 =6019,
-  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6020, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 =6020,
-  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6021, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 =6021,
-  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6022, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 =6022,
-  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6023, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 =6023,
-  XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb =6024, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 =6024,
-  XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb =6025, +  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 =6025,
-  XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq =6026, +  XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6026,
-  XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq =6027, +  XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6027,
-  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6028, +  XED_IFORM_VPABSB_XMMdq_MEMdq =6028,
-  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =6029, +  XED_IFORM_VPABSB_XMMdq_XMMdq =6029,
-  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6030, +  XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 =6030,
-  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6031, +  XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 =6031,
-  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6032, +  XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 =6032,
-  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =6033, +  XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 =6033,
-  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6034, +  XED_IFORM_VPABSB_YMMqq_MEMqq =6034,
-  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6035, +  XED_IFORM_VPABSB_YMMqq_YMMqq =6035,
-  XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb =6036, +  XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 =6036,
-  XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb =6037, +  XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 =6037,
-  XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq =6038, +  XED_IFORM_VPABSD_XMMdq_MEMdq =6038,
-  XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq =6039, +  XED_IFORM_VPABSD_XMMdq_XMMdq =6039,
-  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6040, +  XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 =6040,
-  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =6041, +  XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 =6041,
-  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6042, +  XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 =6042,
-  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6043, +  XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 =6043,
-  XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6044, +  XED_IFORM_VPABSD_YMMqq_MEMqq =6044,
-  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6045, +  XED_IFORM_VPABSD_YMMqq_YMMqq =6045,
-  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6046, +  XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 =6046,
-  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6047, +  XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 =6047,
-  XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb =6048, +  XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 =6048,
-  XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb =6049, +  XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 =6049,
-  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6050, +  XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 =6050,
-  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6051, +  XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 =6051,
-  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6052, +  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 =6052,
-  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6053, +  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 =6053,
-  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6054, +  XED_IFORM_VPABSW_XMMdq_MEMdq =6054,
-  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6055, +  XED_IFORM_VPABSW_XMMdq_XMMdq =6055,
-  XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq =6056, +  XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 =6056,
-  XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq =6057, +  XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 =6057,
-  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6058, +  XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 =6058,
-  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6059, +  XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 =6059,
-  XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb =6060, +  XED_IFORM_VPABSW_YMMqq_MEMqq =6060,
-  XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb =6061, +  XED_IFORM_VPABSW_YMMqq_YMMqq =6061,
-  XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6062, +  XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 =6062,
-  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =6063, +  XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 =6063,
-  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6064, +  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq =6064,
-  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6065, +  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq =6065,
-  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6066, +  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 =6066,
-  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =6067, +  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 =6067,
-  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6068, +  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 =6068,
-  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6069, +  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 =6069,
-  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6070, +  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq =6070,
-  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6071, +  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq =6071,
-  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6072, +  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 =6072,
-  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6073, +  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 =6073,
-  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6074, +  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq =6074,
-  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6075, +  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq =6075,
-  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6076, +  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 =6076,
-  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6077, +  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 =6077,
-  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6078, +  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 =6078,
-  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6079, +  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 =6079,
-  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6080, +  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq =6080,
-  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6081, +  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq =6081,
-  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6082, +  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 =6082,
-  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6083, +  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 =6083,
-  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6084, +  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq =6084,
-  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6085, +  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq =6085,
-  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6086, +  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 =6086,
-  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6087, +  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 =6087,
-  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6088, +  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq =6088,
-  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6089, +  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq =6089,
-  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6090, +  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 =6090,
-  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6091, +  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 =6091,
-  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6092, +  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 =6092,
-  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6093, +  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 =6093,
-  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6094, +  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq =6094,
-  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6095, +  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq =6095,
-  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6096, +  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 =6096,
-  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6097, +  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 =6097,
-  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6098, +  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq =6098,
-  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6099, +  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq =6099,
-  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6100, +  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 =6100,
-  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6101, +  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 =6101,
-  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6102, +  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 =6102,
-  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6103, +  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 =6103,
-  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6104, +  XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq =6104,
-  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6105, +  XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq =6105,
-  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6106, +  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6106,
-  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6107, +  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6107,
-  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6108, +  XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq =6108,
-  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6109, +  XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq =6109,
-  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6110, +  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6110,
-  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6111, +  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6111,
-  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 =6112, +  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6112,
-  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 =6113, +  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6113,
-  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 =6114, +  XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq =6114,
-  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 =6115, +  XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq =6115,
-  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 =6116, +  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6116,
-  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6117, +  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6117,
-  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 =6118, +  XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq =6118,
-  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 =6119, +  XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq =6119,
-  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 =6120, +  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6120,
-  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 =6121, +  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6121,
-  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 =6122, +  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6122,
-  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6123, +  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6123,
-  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 =6124, +  XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq =6124,
-  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 =6125, +  XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq =6125,
-  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 =6126, +  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6126,
-  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 =6127, +  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6127,
-  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6128, +  XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq =6128,
-  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6129, +  XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq =6129,
-  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 =6130, +  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6130,
-  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 =6131, +  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6131,
-  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 =6132, +  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6132,
-  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 =6133, +  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6133,
-  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 =6134, +  XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq =6134,
-  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6135, +  XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq =6135,
-  XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb =6136, +  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =6136,
-  XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 =6137, +  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =6137,
-  XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb =6138, +  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =6138,
-  XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 =6139, +  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =6139,
-  XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb =6140, +  XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq =6140,
-  XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 =6141, +  XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq =6141,
-  XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb =6142, +  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =6142,
-  XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 =6143, +  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =6143,
-  XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb =6144, +  XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq =6144,
-  XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 =6145, +  XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq =6145,
-  XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb =6146, +  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6146,
-  XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 =6147, +  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6147,
-  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 =6148, +  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6148,
-  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 =6149, +  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6149,
-  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 =6150, +  XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq =6150,
-  XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 =6151, +  XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq =6151,
-  XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb =6152, +  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6152,
-  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 =6153, +  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6153,
-  XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6154, +  XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq =6154,
-  XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 =6155, +  XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq =6155,
-  XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 =6156, +  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6156,
-  XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 =6157, +  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6157,
-  XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 =6158, +  XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq =6158,
-  XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6159, +  XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq =6159,
-  XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 =6160, +  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6160,
-  XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6161, +  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6161,
-  XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 =6162, +  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6162,
-  XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6163, +  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6163,
-  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6164, +  XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq =6164,
-  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 =6165, +  XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq =6165,
-  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 =6166, +  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6166,
-  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 =6167, +  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6167,
-  XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 =6168, +  XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq =6168,
-  XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6169, +  XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq =6169,
-  XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 =6170, +  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6170,
-  XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6171, +  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6171,
-  XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 =6172, +  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6172,
-  XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6173, +  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6173,
-  XED_IFORM_VPHADDBD_XMMdq_MEMdq =6174, +  XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq =6174,
-  XED_IFORM_VPHADDBD_XMMdq_XMMdq =6175, +  XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq =6175,
-  XED_IFORM_VPHADDBQ_XMMdq_MEMdq =6176, +  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6176,
-  XED_IFORM_VPHADDBQ_XMMdq_XMMdq =6177, +  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6177,
-  XED_IFORM_VPHADDBW_XMMdq_MEMdq =6178, +  XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq =6178,
-  XED_IFORM_VPHADDBW_XMMdq_XMMdq =6179, +  XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq =6179,
-  XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq =6180, +  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6180,
-  XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq =6181, +  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6181,
-  XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq =6182, +  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6182,
-  XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq =6183, +  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6183,
-  XED_IFORM_VPHADDDQ_XMMdq_MEMdq =6184, +  XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb =6184,
-  XED_IFORM_VPHADDDQ_XMMdq_XMMdq =6185, +  XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb =6185,
-  XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq =6186, +  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =6186,
-  XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq =6187, +  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =6187,
-  XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq =6188, +  XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb =6188,
-  XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq =6189, +  XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb =6189,
-  XED_IFORM_VPHADDUBD_XMMdq_MEMdq =6190, +  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =6190,
-  XED_IFORM_VPHADDUBD_XMMdq_XMMdq =6191, +  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =6191,
-  XED_IFORM_VPHADDUBQ_XMMdq_MEMdq =6192, +  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =6192,
-  XED_IFORM_VPHADDUBQ_XMMdq_XMMdq =6193, +  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =6193,
-  XED_IFORM_VPHADDUBW_XMMdq_MEMdq =6194, +  XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq =6194,
-  XED_IFORM_VPHADDUBW_XMMdq_XMMdq =6195, +  XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq =6195,
-  XED_IFORM_VPHADDUDQ_XMMdq_MEMdq =6196, +  XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq =6196,
-  XED_IFORM_VPHADDUDQ_XMMdq_XMMdq =6197, +  XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq =6197,
-  XED_IFORM_VPHADDUWD_XMMdq_MEMdq =6198, +  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6198,
-  XED_IFORM_VPHADDUWD_XMMdq_XMMdq =6199, +  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6199,
-  XED_IFORM_VPHADDUWQ_XMMdq_MEMdq =6200, +  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6200,
-  XED_IFORM_VPHADDUWQ_XMMdq_XMMdq =6201, +  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6201,
-  XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq =6202, +  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6202,
-  XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq =6203, +  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6203,
-  XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq =6204, +  XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq =6204,
-  XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq =6205, +  XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq =6205,
-  XED_IFORM_VPHADDWD_XMMdq_MEMdq =6206, +  XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq =6206,
-  XED_IFORM_VPHADDWD_XMMdq_XMMdq =6207, +  XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq =6207,
-  XED_IFORM_VPHADDWQ_XMMdq_MEMdq =6208, +  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6208,
-  XED_IFORM_VPHADDWQ_XMMdq_XMMdq =6209, +  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6209,
-  XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq =6210, +  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6210,
-  XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq =6211, +  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6211,
-  XED_IFORM_VPHSUBBW_XMMdq_MEMdq =6212, +  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6212,
-  XED_IFORM_VPHSUBBW_XMMdq_XMMdq =6213, +  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6213,
-  XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq =6214, +  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6214,
-  XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq =6215, +  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6215,
-  XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq =6216, +  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6216,
-  XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq =6217, +  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6217,
-  XED_IFORM_VPHSUBDQ_XMMdq_MEMdq =6218, +  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6218,
-  XED_IFORM_VPHSUBDQ_XMMdq_XMMdq =6219, +  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6219,
-  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq =6220, +  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6220,
-  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq =6221, +  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6221,
-  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq =6222, +  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6222,
-  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq =6223, +  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6223,
-  XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq =6224, +  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6224,
-  XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq =6225, +  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6225,
-  XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq =6226, +  XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq =6226,
-  XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq =6227, +  XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq =6227,
-  XED_IFORM_VPHSUBWD_XMMdq_MEMdq =6228, +  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6228,
-  XED_IFORM_VPHSUBWD_XMMdq_XMMdq =6229, +  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6229,
-  XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb =6230, +  XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq =6230,
-  XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb =6231, +  XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq =6231,
-  XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 =6232, +  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6232,
-  XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 =6233, +  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6233,
-  XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb =6234, +  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6234,
-  XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb =6235, +  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6235,
-  XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 =6236, +  XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq =6236,
-  XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 =6237, +  XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq =6237,
-  XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb =6238, +  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6238,
-  XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb =6239, +  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6239,
-  XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 =6240, +  XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq =6240,
-  XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 =6241, +  XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq =6241,
-  XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb =6242, +  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6242,
-  XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb =6243, +  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6243,
-  XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 =6244, +  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6244,
-  XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 =6245, +  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6245,
-  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =6246, +  XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb =6246,
-  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =6247, +  XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb =6247,
-  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =6248, +  XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb =6248,
-  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =6249, +  XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb =6249,
-  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =6250, +  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6250,
-  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =6251, +  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6251,
-  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6252, +  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6252,
-  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6253, +  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6253,
-  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6254, +  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6254,
-  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =6255, +  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6255,
-  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =6256, +  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6256,
-  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =6257, +  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6257,
-  XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq =6258, +  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6258,
-  XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq =6259, +  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6259,
-  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq =6260, +  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6260,
-  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq =6261, +  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6261,
-  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq =6262, +  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6262,
-  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq =6263, +  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6263,
-  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq =6264, +  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6264,
-  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq =6265, +  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6265,
-  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq =6266, +  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6266,
-  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq =6267, +  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6267,
-  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq =6268, +  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6268,
-  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq =6269, +  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6269,
-  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq =6270, +  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6270,
-  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq =6271, +  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6271,
-  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq =6272, +  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6272,
-  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq =6273, +  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6273,
-  XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq =6274, +  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq =6274,
-  XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq =6275, +  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq =6275,
-  XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq =6276, +  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq =6276,
-  XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq =6277, +  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq =6277,
-  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq =6278, +  XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb =6278,
-  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq =6279, +  XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb =6279,
-  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq =6280, +  XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb =6280,
-  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq =6281, +  XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb =6281,
-  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6282, +  XED_IFORM_VPBROADCASTB_XMMdq_MEMb =6282,
-  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6283, +  XED_IFORM_VPBROADCASTB_XMMdq_XMMb =6283,
-  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64 =6284, +  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 =6284,
-  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64 =6285, +  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 =6285,
-  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6286, +  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 =6286,
-  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6287, +  XED_IFORM_VPBROADCASTB_YMMqq_MEMb =6287,
-  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64 =6288, +  XED_IFORM_VPBROADCASTB_YMMqq_XMMb =6288,
-  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64 =6289, +  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 =6289,
-  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6290, +  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 =6290,
-  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6291, +  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 =6291,
-  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6292, +  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 =6292,
-  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6293, +  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 =6293,
-  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64 =6294, +  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 =6294,
-  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64 =6295, +  XED_IFORM_VPBROADCASTD_XMMdq_MEMd =6295,
-  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6296, +  XED_IFORM_VPBROADCASTD_XMMdq_XMMd =6296,
-  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6297, +  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 =6297,
-  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64 =6298, +  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 =6298,
-  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64 =6299, +  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 =6299,
-  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6300, +  XED_IFORM_VPBROADCASTD_YMMqq_MEMd =6300,
-  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6301, +  XED_IFORM_VPBROADCASTD_YMMqq_XMMd =6301,
-  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq =6302, +  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 =6302,
-  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq =6303, +  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 =6303,
-  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6304, +  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 =6304,
-  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6305, +  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 =6305,
-  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6306, +  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 =6306,
-  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6307, +  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 =6307,
-  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq =6308, +  XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 =6308,
-  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq =6309, +  XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 =6309,
-  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6310, +  XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD =6310,
-  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6311, +  XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 =6311,
-  XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq =6312, +  XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 =6312,
-  XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq =6313, +  XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD =6313,
-  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 =6314, +  XED_IFORM_VPBROADCASTQ_XMMdq_MEMq =6314,
-  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 =6315, +  XED_IFORM_VPBROADCASTQ_XMMdq_XMMq =6315,
-  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 =6316, +  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 =6316,
-  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 =6317, +  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6317,
-  XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq =6318, +  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6318,
-  XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq =6319, +  XED_IFORM_VPBROADCASTQ_YMMqq_MEMq =6319,
-  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 =6320, +  XED_IFORM_VPBROADCASTQ_YMMqq_XMMq =6320,
-  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 =6321, +  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 =6321,
-  XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq =6322, +  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6322,
-  XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq =6323, +  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 =6323,
-  XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq =6324, +  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 =6324,
-  XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq =6325, +  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6325,
-  XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq =6326, +  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 =6326,
-  XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq =6327, +  XED_IFORM_VPBROADCASTW_XMMdq_MEMw =6327,
-  XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq =6328, +  XED_IFORM_VPBROADCASTW_XMMdq_XMMw =6328,
-  XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq =6329, +  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 =6329,
-  XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq =6330, +  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 =6330,
-  XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq =6331, +  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 =6331,
-  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =6332, +  XED_IFORM_VPBROADCASTW_YMMqq_MEMw =6332,
-  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =6333, +  XED_IFORM_VPBROADCASTW_YMMqq_XMMw =6333,
-  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =6334, +  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 =6334,
-  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =6335, +  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 =6335,
-  XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq =6336, +  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 =6336,
-  XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq =6337, +  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 =6337,
-  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =6338, +  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 =6338,
-  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =6339, +  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 =6339,
-  XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq =6340, +  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb =6340,
-  XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq =6341, +  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb =6341,
-  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =6342, +  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 =6342,
-  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =6343, +  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 =6343,
-  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =6344, +  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 =6344,
-  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =6345, +  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 =6345,
-  XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq =6346, +  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 =6346,
-  XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq =6347, +  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 =6347,
-  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =6348, +  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 =6348,
-  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =6349, +  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 =6349,
-  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =6350, +  XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq =6350,
-  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =6351, +  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq =6351,
-  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =6352, +  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq =6352,
-  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =6353, +  XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq =6353,
-  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =6354, +  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq =6354,
-  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =6355, +  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq =6355,
-  XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq =6356, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 =6356,
-  XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq =6357, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 =6357,
-  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6358, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 =6358,
-  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6359, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 =6359,
-  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6360, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 =6360,
-  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6361, +  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 =6361,
-  XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq =6362, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 =6362,
-  XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq =6363, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 =6363,
-  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6364, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 =6364,
-  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6365, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 =6365,
-  XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq =6366, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 =6366,
-  XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq =6367, +  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 =6367,
-  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6368, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =6368,
-  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6369, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =6369,
-  XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq =6370, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =6370,
-  XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq =6371, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =6371,
-  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6372, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =6372,
-  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6373, +  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =6373,
-  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6374, +  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq =6374,
-  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6375, +  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq =6375,
-  XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq =6376, +  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq =6376,
-  XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq =6377, +  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq =6377,
-  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6378, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =6378,
-  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6379, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =6379,
-  XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq =6380, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =6380,
-  XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq =6381, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =6381,
-  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6382, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =6382,
-  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6383, +  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =6383,
-  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6384, +  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq =6384,
-  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6385, +  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq =6385,
-  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6386, +  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq =6386,
-  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6387, +  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq =6387,
-  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6388, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =6388,
-  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6389, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =6389,
-  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6390, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =6390,
-  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6391, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =6391,
-  XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq =6392, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =6392,
-  XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq =6393, +  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =6393,
-  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6394, +  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq =6394,
-  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6395, +  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq =6395,
-  XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq =6396, +  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq =6396,
-  XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq =6397, +  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq =6397,
-  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6398, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =6398,
-  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6399, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =6399,
-  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6400, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =6400,
-  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6401, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =6401,
-  XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq =6402, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =6402,
-  XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq =6403, +  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =6403,
-  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =6404, +  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq =6404,
-  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =6405, +  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq =6405,
-  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =6406, +  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq =6406,
-  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =6407, +  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq =6407,
-  XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq =6408, +  XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb =6408,
-  XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq =6409, +  XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb =6409,
-  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =6410, +  XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb =6410,
-  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =6411, +  XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb =6411,
-  XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq =6412, +  XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb =6412,
-  XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq =6413, +  XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb =6413,
-  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =6414, +  XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb =6414,
-  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =6415, +  XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb =6415,
-  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =6416, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =6416,
-  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =6417, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =6417,
-  XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq =6418, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =6418,
-  XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq =6419, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =6419,
-  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =6420, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =6420,
-  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =6421, +  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =6421,
-  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =6422, +  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq =6422,
-  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =6423, +  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq =6423,
-  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =6424, +  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq =6424,
-  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =6425, +  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq =6425,
-  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =6426, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 =6426,
-  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =6427, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 =6427,
-  XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq =6428, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 =6428,
-  XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq =6429, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 =6429,
-  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6430, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 =6430,
-  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6431, +  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 =6431,
-  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6432, +  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq =6432,
-  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6433, +  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq =6433,
-  XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq =6434, +  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq =6434,
-  XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq =6435, +  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq =6435,
-  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6436, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 =6436,
-  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6437, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 =6437,
-  XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq =6438, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 =6438,
-  XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq =6439, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 =6439,
-  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6440, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 =6440,
-  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6441, +  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 =6441,
-  XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq =6442, +  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq =6442,
-  XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq =6443, +  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq =6443,
-  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6444, +  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq =6444,
-  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6445, +  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq =6445,
-  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6446, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =6446,
-  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6447, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =6447,
-  XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq =6448, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =6448,
-  XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq =6449, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =6449,
-  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6450, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =6450,
-  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6451, +  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =6451,
-  XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq =6452, +  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq =6452,
-  XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq =6453, +  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq =6453,
-  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6454, +  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq =6454,
-  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6455, +  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq =6455,
-  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6456, +  XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb =6456,
-  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6457, +  XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb =6457,
-  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6458, +  XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb =6458,
-  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6459, +  XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb =6459,
-  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6460, +  XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb =6460,
-  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6461, +  XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb =6461,
-  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6462, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 =6462,
-  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6463, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 =6463,
-  XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq =6464, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 =6464,
-  XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq =6465, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 =6465,
-  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6466, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 =6466,
-  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6467, +  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 =6467,
-  XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq =6468, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =6468,
-  XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq =6469, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =6469,
-  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6470, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =6470,
-  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6471, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =6471,
-  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6472, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =6472,
-  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6473, +  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =6473,
-  XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 =6474, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =6474,
-  XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 =6475, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =6475,
-  XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 =6476, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =6476,
-  XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 =6477, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =6477,
-  XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 =6478, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =6478,
-  XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 =6479, +  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =6479,
-  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 =6480, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =6480,
-  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 =6481, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =6481,
-  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 =6482, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =6482,
-  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 =6483, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =6483,
-  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 =6484, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =6484,
-  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 =6485, +  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =6485,
-  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 =6486, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =6486,
-  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 =6487, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =6487,
-  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 =6488, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =6488,
-  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 =6489, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =6489,
-  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 =6490, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =6490,
-  XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 =6491, +  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =6491,
-  XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 =6492, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 =6492,
-  XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 =6493, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 =6493,
-  XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 =6494, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 =6494,
-  XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 =6495, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 =6495,
-  XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 =6496, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 =6496,
-  XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 =6497, +  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 =6497,
-  XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 =6498, +  XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb =6498,
-  XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 =6499, +  XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb =6499,
-  XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 =6500, +  XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb =6500,
-  XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 =6501, +  XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb =6501,
-  XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 =6502, +  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 =6502,
-  XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 =6503, +  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 =6503,
-  XED_IFORM_VPMOVMSKB_GPR32d_XMMdq =6504, +  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 =6504,
-  XED_IFORM_VPMOVMSKB_GPR32d_YMMqq =6505, +  XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 =6505,
-  XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 =6506, +  XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 =6506,
-  XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 =6507, +  XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6507,
-  XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 =6508, +  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 =6508,
-  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 =6509, +  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 =6509,
-  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 =6510, +  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 =6510,
-  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 =6511, +  XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 =6511,
-  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 =6512, +  XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 =6512,
-  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 =6513, +  XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6513,
-  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 =6514, +  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 =6514,
-  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 =6515, +  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 =6515,
-  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 =6516, +  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 =6516,
-  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 =6517, +  XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 =6517,
-  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 =6518, +  XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 =6518,
-  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 =6519, +  XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6519,
-  XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 =6520, +  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 =6520,
-  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 =6521, +  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 =6521,
-  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 =6522, +  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 =6522,
-  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 =6523, +  XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 =6523,
-  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 =6524, +  XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 =6524,
-  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 =6525, +  XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6525,
-  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 =6526, +  XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb =6526,
-  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 =6527, +  XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb =6527,
-  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 =6528, +  XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb =6528,
-  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 =6529, +  XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb =6529,
-  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 =6530, +  XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb =6530,
-  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 =6531, +  XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb =6531,
-  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 =6532, +  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb =6532,
-  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 =6533, +  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb =6533,
-  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 =6534, +  XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb =6534,
-  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 =6535, +  XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb =6535,
-  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 =6536, +  XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb =6536,
-  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 =6537, +  XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb =6537,
-  XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 =6538, +  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 =6538,
-  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 =6539, +  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 =6539,
-  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 =6540, +  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 =6540,
-  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 =6541, +  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 =6541,
-  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 =6542, +  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =6542,
-  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 =6543, +  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =6543,
-  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 =6544, +  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6544,
-  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 =6545, +  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6545,
-  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 =6546, +  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6546,
-  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 =6547, +  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 =6547,
-  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 =6548, +  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =6548,
-  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 =6549, +  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =6549,
-  XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 =6550, +  XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 =6550,
-  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 =6551, +  XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 =6551,
-  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 =6552, +  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8 =6552,
-  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 =6553, +  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8 =6553,
-  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 =6554, +  XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 =6554,
-  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 =6555, +  XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 =6555,
-  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 =6556, +  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8 =6556,
-  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 =6557, +  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8 =6557,
-  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 =6558, +  XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 =6558,
-  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 =6559, +  XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 =6559,
-  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 =6560, +  XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 =6560,
-  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 =6561, +  XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 =6561,
-  XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 =6562, +  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 =6562,
-  XED_IFORM_VPMOVSXBD_XMMdq_MEMd =6563, +  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 =6563,
-  XED_IFORM_VPMOVSXBD_XMMdq_XMMd =6564, +  XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 =6564,
-  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 =6565, +  XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 =6565,
-  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 =6566, +  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 =6566,
-  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 =6567, +  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 =6567,
-  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 =6568, +  XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 =6568,
-  XED_IFORM_VPMOVSXBD_YMMqq_MEMq =6569, +  XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 =6569,
-  XED_IFORM_VPMOVSXBD_YMMqq_XMMq =6570, +  XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 =6570,
-  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =6571, +  XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 =6571,
-  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =6572, +  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8 =6572,
-  XED_IFORM_VPMOVSXBQ_XMMdq_MEMw =6573, +  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8 =6573,
-  XED_IFORM_VPMOVSXBQ_XMMdq_XMMw =6574, +  XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 =6574,
-  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =6575, +  XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 =6575,
-  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =6576, +  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8 =6576,
-  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =6577, +  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8 =6577,
-  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =6578, +  XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 =6578,
-  XED_IFORM_VPMOVSXBQ_YMMqq_MEMd =6579, +  XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 =6579,
-  XED_IFORM_VPMOVSXBQ_YMMqq_XMMd =6580, +  XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 =6580,
-  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =6581, +  XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 =6581,
-  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =6582, +  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 =6582,
-  XED_IFORM_VPMOVSXBW_XMMdq_MEMq =6583, +  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 =6583,
-  XED_IFORM_VPMOVSXBW_XMMdq_XMMq =6584, +  XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 =6584,
-  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 =6585, +  XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 =6585,
-  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 =6586, +  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 =6586,
-  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 =6587, +  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 =6587,
-  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 =6588, +  XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 =6588,
-  XED_IFORM_VPMOVSXBW_YMMqq_MEMdq =6589, +  XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 =6589,
-  XED_IFORM_VPMOVSXBW_YMMqq_XMMdq =6590, +  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =6590,
-  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =6591, +  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =6591,
-  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =6592, +  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32 =6592,
-  XED_IFORM_VPMOVSXDQ_XMMdq_MEMq =6593, +  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32 =6593,
-  XED_IFORM_VPMOVSXDQ_XMMdq_XMMq =6594, +  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =6594,
-  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =6595, +  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =6595,
-  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =6596, +  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32 =6596,
-  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =6597, +  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32 =6597,
-  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =6598, +  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =6598,
-  XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq =6599, +  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =6599,
-  XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq =6600, +  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =6600,
-  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =6601, +  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =6601,
-  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =6602, +  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32 =6602,
-  XED_IFORM_VPMOVSXWD_XMMdq_MEMq =6603, +  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32 =6603,
-  XED_IFORM_VPMOVSXWD_XMMdq_XMMq =6604, +  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =6604,
-  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 =6605, +  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =6605,
-  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 =6606, +  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32 =6606,
-  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 =6607, +  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32 =6607,
-  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 =6608, +  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =6608,
-  XED_IFORM_VPMOVSXWD_YMMqq_MEMdq =6609, +  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =6609,
-  XED_IFORM_VPMOVSXWD_YMMqq_XMMdq =6610, +  XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 =6610,
-  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =6611, +  XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 =6611,
-  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =6612, +  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8 =6612,
-  XED_IFORM_VPMOVSXWQ_XMMdq_MEMd =6613, +  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8 =6613,
-  XED_IFORM_VPMOVSXWQ_XMMdq_XMMd =6614, +  XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 =6614,
-  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =6615, +  XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 =6615,
-  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =6616, +  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8 =6616,
-  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =6617, +  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8 =6617,
-  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =6618, +  XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 =6618,
-  XED_IFORM_VPMOVSXWQ_YMMqq_MEMq =6619, +  XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 =6619,
-  XED_IFORM_VPMOVSXWQ_YMMqq_XMMq =6620, +  XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 =6620,
-  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =6621, +  XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 =6621,
-  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =6622, +  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 =6622,
-  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 =6623, +  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 =6623,
-  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 =6624, +  XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 =6624,
-  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 =6625, +  XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 =6625,
-  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 =6626, +  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 =6626,
-  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 =6627, +  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 =6627,
-  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 =6628, +  XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 =6628,
-  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 =6629, +  XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 =6629,
-  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 =6630, +  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =6630,
-  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 =6631, +  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =6631,
-  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 =6632, +  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32 =6632,
-  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 =6633, +  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32 =6633,
-  XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 =6634, +  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =6634,
-  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 =6635, +  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =6635,
-  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 =6636, +  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32 =6636,
-  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 =6637, +  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32 =6637,
-  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 =6638, +  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6638,
-  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 =6639, +  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =6639,
-  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 =6640, +  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =6640,
-  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 =6641, +  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =6641,
-  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 =6642, +  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32 =6642,
-  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 =6643, +  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32 =6643,
-  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 =6644, +  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =6644,
-  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 =6645, +  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =6645,
-  XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 =6646, +  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32 =6646,
-  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 =6647, +  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32 =6647,
-  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 =6648, +  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6648,
-  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 =6649, +  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =6649,
-  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 =6650, +  XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 =6650,
-  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 =6651, +  XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 =6651,
-  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 =6652, +  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16 =6652,
-  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 =6653, +  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16 =6653,
-  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 =6654, +  XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 =6654,
-  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 =6655, +  XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 =6655,
-  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 =6656, +  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16 =6656,
-  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 =6657, +  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16 =6657,
-  XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 =6658, +  XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 =6658,
-  XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 =6659, +  XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 =6659,
-  XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 =6660, +  XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 =6660,
-  XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 =6661, +  XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 =6661,
-  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 =6662, +  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 =6662,
-  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 =6663, +  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 =6663,
-  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 =6664, +  XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 =6664,
-  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 =6665, +  XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 =6665,
-  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 =6666, +  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 =6666,
-  XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 =6667, +  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 =6667,
-  XED_IFORM_VPMOVZXBD_XMMdq_MEMd =6668, +  XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 =6668,
-  XED_IFORM_VPMOVZXBD_XMMdq_XMMd =6669, +  XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 =6669,
-  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 =6670, +  XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 =6670,
-  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 =6671, +  XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 =6671,
-  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 =6672, +  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16 =6672,
-  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 =6673, +  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16 =6673,
-  XED_IFORM_VPMOVZXBD_YMMqq_MEMq =6674, +  XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 =6674,
-  XED_IFORM_VPMOVZXBD_YMMqq_XMMq =6675, +  XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 =6675,
-  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =6676, +  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16 =6676,
-  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =6677, +  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16 =6677,
-  XED_IFORM_VPMOVZXBQ_XMMdq_MEMw =6678, +  XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 =6678,
-  XED_IFORM_VPMOVZXBQ_XMMdq_XMMw =6679, +  XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 =6679,
-  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =6680, +  XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 =6680,
-  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =6681, +  XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 =6681,
-  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =6682, +  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 =6682,
-  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =6683, +  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 =6683,
-  XED_IFORM_VPMOVZXBQ_YMMqq_MEMd =6684, +  XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 =6684,
-  XED_IFORM_VPMOVZXBQ_YMMqq_XMMd =6685, +  XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 =6685,
-  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =6686, +  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 =6686,
-  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =6687, +  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 =6687,
-  XED_IFORM_VPMOVZXBW_XMMdq_MEMq =6688, +  XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 =6688,
-  XED_IFORM_VPMOVZXBW_XMMdq_XMMq =6689, +  XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 =6689,
-  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 =6690, +  XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 =6690,
-  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 =6691, +  XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 =6691,
-  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 =6692, +  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16 =6692,
-  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 =6693, +  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16 =6693,
-  XED_IFORM_VPMOVZXBW_YMMqq_MEMdq =6694, +  XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 =6694,
-  XED_IFORM_VPMOVZXBW_YMMqq_XMMdq =6695, +  XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 =6695,
-  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =6696, +  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16 =6696,
-  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =6697, +  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16 =6697,
-  XED_IFORM_VPMOVZXDQ_XMMdq_MEMq =6698, +  XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 =6698,
-  XED_IFORM_VPMOVZXDQ_XMMdq_XMMq =6699, +  XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 =6699,
-  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =6700, +  XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 =6700,
-  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =6701, +  XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 =6701,
-  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =6702, +  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 =6702,
-  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =6703, +  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 =6703,
-  XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq =6704, +  XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 =6704,
-  XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq =6705, +  XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 =6705,
-  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =6706, +  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 =6706,
-  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =6707, +  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 =6707,
-  XED_IFORM_VPMOVZXWD_XMMdq_MEMq =6708, +  XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 =6708,
-  XED_IFORM_VPMOVZXWD_XMMdq_XMMq =6709, +  XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 =6709,
-  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 =6710, +  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb =6710,
-  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 =6711, +  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb =6711,
-  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 =6712, +  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb =6712,
-  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 =6713, +  XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb =6713,
-  XED_IFORM_VPMOVZXWD_YMMqq_MEMdq =6714, +  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6714,
-  XED_IFORM_VPMOVZXWD_YMMqq_XMMdq =6715, +  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6715,
-  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =6716, +  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6716,
-  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =6717, +  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6717,
-  XED_IFORM_VPMOVZXWQ_XMMdq_MEMd =6718, +  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6718,
-  XED_IFORM_VPMOVZXWQ_XMMdq_XMMd =6719, +  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6719,
-  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =6720, +  XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq =6720,
-  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =6721, +  XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq =6721,
-  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =6722, +  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6722,
-  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =6723, +  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6723,
-  XED_IFORM_VPMOVZXWQ_YMMqq_MEMq =6724, +  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6724,
-  XED_IFORM_VPMOVZXWQ_YMMqq_XMMq =6725, +  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6725,
-  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =6726, +  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6726,
-  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =6727, +  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6727,
-  XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq =6728, +  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6728,
-  XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq =6729, +  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6729,
-  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 =6730, +  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6730,
-  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 =6731, +  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6731,
-  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 =6732, +  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6732,
-  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 =6733, +  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6733,
-  XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq =6734, +  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6734,
-  XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq =6735, +  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6735,
-  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 =6736, +  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6736,
-  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 =6737, +  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6737,
-  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq =6738, +  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6738,
-  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq =6739, +  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6739,
-  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6740, +  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6740,
-  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6741, +  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6741,
-  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6742, +  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6742,
-  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6743, +  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6743,
-  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq =6744, +  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6744,
-  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq =6745, +  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6745,
-  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6746, +  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6746,
-  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6747, +  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6747,
-  XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq =6748, +  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6748,
-  XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq =6749, +  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6749,
-  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6750, +  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6750,
-  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6751, +  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6751,
-  XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq =6752, +  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6752,
-  XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq =6753, +  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6753,
-  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6754, +  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6754,
-  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6755, +  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6755,
-  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6756, +  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6756,
-  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6757, +  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6757,
-  XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq =6758, +  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6758,
-  XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq =6759, +  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6759,
-  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6760, +  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6760,
-  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6761, +  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6761,
-  XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq =6762, +  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =6762,
-  XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq =6763, +  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =6763,
-  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6764, +  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =6764,
-  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6765, +  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =6765,
-  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6766, +  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =6766,
-  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6767, +  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =6767,
-  XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq =6768, +  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =6768,
-  XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq =6769, +  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =6769,
-  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6770, +  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =6770,
-  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6771, +  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =6771,
-  XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq =6772, +  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =6772,
-  XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq =6773, +  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =6773,
-  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6774, +  XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb =6774,
-  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6775, +  XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb =6775,
-  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6776, +  XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq =6776,
-  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6777, +  XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq =6777,
-  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6778, +  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6778,
-  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6779, +  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =6779,
-  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6780, +  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6780,
-  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6781, +  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6781,
-  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6782, +  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6782,
-  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6783, +  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6783,
-  XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq =6784, +  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6784,
-  XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq =6785, +  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6785,
-  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6786, +  XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb =6786,
-  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6787, +  XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb =6787,
-  XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq =6788, +  XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq =6788,
-  XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq =6789, +  XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq =6789,
-  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6790, +  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6790,
-  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6791, +  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6791,
-  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6792, +  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6792,
-  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6793, +  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6793,
-  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 =6794, +  XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb =6794,
-  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 =6795, +  XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb =6795,
-  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 =6796, +  XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq =6796,
-  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 =6797, +  XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq =6797,
-  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 =6798, +  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6798,
-  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 =6799, +  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =6799,
-  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq =6800, +  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6800,
-  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq =6801, +  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6801,
-  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 =6802, +  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6802,
-  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 =6803, +  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =6803,
-  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq =6804, +  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6804,
-  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq =6805, +  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6805,
-  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 =6806, +  XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb =6806,
-  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 =6807, +  XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb =6807,
-  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 =6808, +  XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq =6808,
-  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 =6809, +  XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq =6809,
-  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 =6810, +  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6810,
-  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 =6811, +  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =6811,
-  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 =6812, +  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6812,
-  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 =6813, +  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6813,
-  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 =6814, +  XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6814,
-  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6815, +  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6815,
-  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =6816, +  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6816,
-  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =6817, +  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6817,
-  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =6818, +  XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb =6818,
-  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =6819, +  XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb =6819,
-  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 =6820, +  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6820,
-  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6821, +  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6821,
-  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6822, +  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6822,
-  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6823, +  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6823,
-  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6824, +  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6824,
-  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =6825, +  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6825,
-  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6826, +  XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq =6826,
-  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6827, +  XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq =6827,
-  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 =6828, +  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6828,
-  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 =6829, +  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6829,
-  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 =6830, +  XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb =6830,
-  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 =6831, +  XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb =6831,
-  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 =6832, +  XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6832,
-  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6833, +  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =6833,
-  XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq =6834, +  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6834,
-  XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq =6835, +  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6835,
-  XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq =6836, +  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6836,
-  XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq =6837, +  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =6837,
-  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6838, +  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6838,
-  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6839, +  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6839,
-  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6840, +  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6840,
-  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6841, +  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6841,
-  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6842, +  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6842,
-  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6843, +  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6843,
-  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6844, +  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6844,
-  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6845, +  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6845,
-  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6846, +  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6846,
-  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6847, +  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6847,
-  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6848, +  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6848,
-  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6849, +  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6849,
-  XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq =6850, +  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6850,
-  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq =6851, +  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6851,
-  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq =6852, +  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6852,
-  XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6853, +  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6853,
-  XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =6854, +  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6854,
-  XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6855, +  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6855,
-  XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =6856, +  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6856,
-  XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6857, +  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6857,
-  XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =6858, +  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6858,
-  XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6859, +  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6859,
-  XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =6860, +  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6860,
-  XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6861, +  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6861,
-  XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =6862, +  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6862,
-  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6863, +  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6863,
-  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =6864, +  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6864,
-  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6865, +  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6865,
-  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6866, +  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6866,
-  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6867, +  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6867,
-  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6868, +  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6868,
-  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6869, +  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6869,
-  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6870, +  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6870,
-  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6871, +  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6871,
-  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6872, +  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6872,
-  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6873, +  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6873,
-  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6874, +  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6874,
-  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6875, +  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6875,
-  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6876, +  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6876,
-  XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6877, +  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6877,
-  XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =6878, +  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6878,
-  XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6879, +  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6879,
-  XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =6880, +  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6880,
-  XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =6881, +  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6881,
-  XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =6882, +  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 =6882,
-  XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6883, +  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 =6883,
-  XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =6884, +  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 =6884,
-  XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6885, +  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 =6885,
-  XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =6886, +  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 =6886,
-  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6887, +  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6887,
-  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =6888, +  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 =6888,
-  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6889, +  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 =6889,
-  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6890, +  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 =6890,
-  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6891, +  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 =6891,
-  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6892, +  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 =6892,
-  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6893, +  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6893,
-  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6894, +  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 =6894,
-  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6895, +  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 =6895,
-  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6896, +  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 =6896,
-  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6897, +  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 =6897,
-  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6898, +  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6898,
-  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6899, +  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6899,
-  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6900, +  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 =6900,
-  XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb =6901, +  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 =6901,
-  XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq =6902, +  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 =6902,
-  XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb =6903, +  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 =6903,
-  XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq =6904, +  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 =6904,
-  XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq =6905, +  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6905,
-  XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb =6906, +  XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb =6906,
-  XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq =6907, +  XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 =6907,
-  XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb =6908, +  XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb =6908,
-  XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq =6909, +  XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 =6909,
-  XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq =6910, +  XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb =6910,
-  XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb =6911, +  XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 =6911,
-  XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq =6912, +  XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb =6912,
-  XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb =6913, +  XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 =6913,
-  XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq =6914, +  XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb =6914,
-  XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq =6915, +  XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 =6915,
-  XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb =6916, +  XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb =6916,
-  XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq =6917, +  XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 =6917,
-  XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb =6918, +  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 =6918,
-  XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq =6919, +  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 =6919,
-  XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq =6920, +  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 =6920,
-  XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq =6921, +  XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 =6921,
-  XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq =6922, +  XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb =6922,
-  XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 =6923, +  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 =6923,
-  XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 =6924, +  XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6924,
-  XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq =6925, +  XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 =6925,
-  XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq =6926, +  XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 =6926,
-  XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 =6927, +  XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 =6927,
-  XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 =6928, +  XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 =6928,
-  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 =6929, +  XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6929,
-  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 =6930, +  XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 =6930,
-  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =6931, +  XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6931,
-  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 =6932, +  XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 =6932,
-  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 =6933, +  XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6933,
-  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =6934, +  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6934,
-  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =6935, +  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 =6935,
-  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =6936, +  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 =6936,
-  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =6937, +  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 =6937,
-  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 =6938, +  XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 =6938,
-  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 =6939, +  XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6939,
-  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =6940, +  XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 =6940,
-  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =6941, +  XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6941,
-  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =6942, +  XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 =6942,
-  XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq =6943, +  XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6943,
-  XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq =6944, +  XED_IFORM_VPHADDBD_XMMdq_MEMdq =6944,
-  XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq =6945, +  XED_IFORM_VPHADDBD_XMMdq_XMMdq =6945,
-  XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq =6946, +  XED_IFORM_VPHADDBQ_XMMdq_MEMdq =6946,
-  XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq =6947, +  XED_IFORM_VPHADDBQ_XMMdq_XMMdq =6947,
-  XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq =6948, +  XED_IFORM_VPHADDBW_XMMdq_MEMdq =6948,
-  XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq =6949, +  XED_IFORM_VPHADDBW_XMMdq_XMMdq =6949,
-  XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq =6950, +  XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq =6950,
-  XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq =6951, +  XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq =6951,
-  XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq =6952, +  XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq =6952,
-  XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq =6953, +  XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq =6953,
-  XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq =6954, +  XED_IFORM_VPHADDDQ_XMMdq_MEMdq =6954,
-  XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq =6955, +  XED_IFORM_VPHADDDQ_XMMdq_XMMdq =6955,
-  XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq =6956, +  XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq =6956,
-  XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq =6957, +  XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq =6957,
-  XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq =6958, +  XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq =6958,
-  XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq =6959, +  XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq =6959,
-  XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq =6960, +  XED_IFORM_VPHADDUBD_XMMdq_MEMdq =6960,
-  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =6961, +  XED_IFORM_VPHADDUBD_XMMdq_XMMdq =6961,
-  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =6962, +  XED_IFORM_VPHADDUBQ_XMMdq_MEMdq =6962,
-  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =6963, +  XED_IFORM_VPHADDUBQ_XMMdq_XMMdq =6963,
-  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =6964, +  XED_IFORM_VPHADDUBW_XMMdq_MEMdq =6964,
-  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =6965, +  XED_IFORM_VPHADDUBW_XMMdq_XMMdq =6965,
-  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =6966, +  XED_IFORM_VPHADDUDQ_XMMdq_MEMdq =6966,
-  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =6967, +  XED_IFORM_VPHADDUDQ_XMMdq_XMMdq =6967,
-  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =6968, +  XED_IFORM_VPHADDUWD_XMMdq_MEMdq =6968,
-  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =6969, +  XED_IFORM_VPHADDUWD_XMMdq_XMMdq =6969,
-  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =6970, +  XED_IFORM_VPHADDUWQ_XMMdq_MEMdq =6970,
-  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =6971, +  XED_IFORM_VPHADDUWQ_XMMdq_XMMdq =6971,
-  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =6972, +  XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq =6972,
-  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6973, +  XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq =6973,
-  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6974, +  XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq =6974,
-  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6975, +  XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq =6975,
-  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6976, +  XED_IFORM_VPHADDWD_XMMdq_MEMdq =6976,
-  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6977, +  XED_IFORM_VPHADDWD_XMMdq_XMMdq =6977,
-  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6978, +  XED_IFORM_VPHADDWQ_XMMdq_MEMdq =6978,
-  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6979, +  XED_IFORM_VPHADDWQ_XMMdq_XMMdq =6979,
-  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6980, +  XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq =6980,
-  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6981, +  XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq =6981,
-  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6982, +  XED_IFORM_VPHSUBBW_XMMdq_MEMdq =6982,
-  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6983, +  XED_IFORM_VPHSUBBW_XMMdq_XMMdq =6983,
-  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6984, +  XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq =6984,
-  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6985, +  XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq =6985,
-  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6986, +  XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq =6986,
-  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6987, +  XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq =6987,
-  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6988, +  XED_IFORM_VPHSUBDQ_XMMdq_MEMdq =6988,
-  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6989, +  XED_IFORM_VPHSUBDQ_XMMdq_XMMdq =6989,
-  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6990, +  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq =6990,
-  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =6991, +  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq =6991,
-  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =6992, +  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq =6992,
-  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =6993, +  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq =6993,
-  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =6994, +  XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq =6994,
-  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =6995, +  XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq =6995,
-  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =6996, +  XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq =6996,
-  XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq =6997, +  XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq =6997,
-  XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq =6998, +  XED_IFORM_VPHSUBWD_XMMdq_MEMdq =6998,
-  XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq =6999, +  XED_IFORM_VPHSUBWD_XMMdq_XMMdq =6999,
-  XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq =7000, +  XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb =7000,
-  XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq =7001, +  XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb =7001,
-  XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq =7002, +  XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 =7002,
-  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7003, +  XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 =7003,
-  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7004, +  XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb =7004,
-  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7005, +  XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb =7005,
-  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7006, +  XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 =7006,
-  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7007, +  XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 =7007,
-  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7008, +  XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb =7008,
-  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7009, +  XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb =7009,
-  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7010, +  XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 =7010,
-  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7011, +  XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 =7011,
-  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7012, +  XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb =7012,
-  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7013, +  XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb =7013,
-  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7014, +  XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 =7014,
-  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7015, +  XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 =7015,
-  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7016, +  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =7016,
-  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7017, +  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =7017,
-  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7018, +  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =7018,
-  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7019, +  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =7019,
-  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7020, +  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =7020,
-  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7021, +  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =7021,
-  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7022, +  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =7022,
-  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7023, +  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =7023,
-  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7024, +  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =7024,
-  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7025, +  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =7025,
-  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7026, +  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =7026,
-  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7027, +  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =7027,
-  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7028, +  XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq =7028,
-  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7029, +  XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq =7029,
-  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7030, +  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq =7030,
-  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7031, +  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq =7031,
-  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7032, +  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq =7032,
-  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =7033, +  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq =7033,
-  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =7034, +  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq =7034,
-  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =7035, +  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq =7035,
-  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =7036, +  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq =7036,
-  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =7037, +  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq =7037,
-  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =7038, +  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq =7038,
-  XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq =7039, +  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq =7039,
-  XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq =7040, +  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq =7040,
-  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7041, +  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq =7041,
-  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7042, +  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq =7042,
-  XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq =7043, +  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq =7043,
-  XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq =7044, +  XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq =7044,
-  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7045, +  XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq =7045,
-  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7046, +  XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq =7046,
-  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7047, +  XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq =7047,
-  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7048, +  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq =7048,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 =7049, +  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq =7049,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 =7050, +  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq =7050,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 =7051, +  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq =7051,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 =7052, +  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7052,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 =7053, +  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7053,
-  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 =7054, +  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64 =7054,
-  XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb =7055, +  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64 =7055,
-  XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb =7056, +  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7056,
-  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7057, +  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7057,
-  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7058, +  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64 =7058,
-  XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb =7059, +  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64 =7059,
-  XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb =7060, +  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7060,
-  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7061, +  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7061,
-  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7062, +  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7062,
-  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7063, +  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7063,
-  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7064, +  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64 =7064,
-  XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb =7065, +  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64 =7065,
-  XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb =7066, +  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7066,
-  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7067, +  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7067,
-  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7068, +  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64 =7068,
-  XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb =7069, +  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64 =7069,
-  XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb =7070, +  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7070,
-  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7071, +  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7071,
-  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7072, +  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq =7072,
-  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7073, +  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq =7073,
-  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7074, +  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7074,
-  XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb =7075, +  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7075,
-  XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb =7076, +  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7076,
-  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7077, +  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7077,
-  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7078, +  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq =7078,
-  XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb =7079, +  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq =7079,
-  XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb =7080, +  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7080,
-  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7081, +  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7081,
-  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7082, +  XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq =7082,
-  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7083, +  XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq =7083,
-  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7084, +  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 =7084,
-  XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq =7085, +  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 =7085,
-  XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq =7086, +  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 =7086,
-  XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq =7087, +  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 =7087,
-  XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq =7088, +  XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq =7088,
-  XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq =7089, +  XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq =7089,
-  XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq =7090, +  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 =7090,
-  XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq =7091, +  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 =7091,
-  XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq =7092, +  XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq =7092,
-  XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq =7093, +  XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq =7093,
-  XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq =7094, +  XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq =7094,
-  XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq =7095, +  XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq =7095,
-  XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq =7096, +  XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq =7096,
-  XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb =7097, +  XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq =7097,
-  XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq =7098, +  XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq =7098,
-  XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq =7099, +  XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq =7099,
-  XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7100, +  XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq =7100,
-  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7101, +  XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq =7101,
-  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7102, +  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =7102,
-  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7103, +  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =7103,
-  XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb =7104, +  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =7104,
-  XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq =7105, +  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =7105,
-  XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq =7106, +  XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq =7106,
-  XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7107, +  XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq =7107,
-  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7108, +  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =7108,
-  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7109, +  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =7109,
-  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7110, +  XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq =7110,
-  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7111, +  XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq =7111,
-  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7112, +  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =7112,
-  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7113, +  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =7113,
-  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7114, +  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =7114,
-  XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb =7115, +  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =7115,
-  XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 =7116, +  XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq =7116,
-  XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 =7117, +  XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq =7117,
-  XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb =7118, +  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =7118,
-  XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 =7119, +  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =7119,
-  XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 =7120, +  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =7120,
-  XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 =7121, +  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =7121,
-  XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =7122, +  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =7122,
-  XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb =7123, +  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =7123,
-  XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq =7124, +  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =7124,
-  XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq =7125, +  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =7125,
-  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7126, +  XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq =7126,
-  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7127, +  XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq =7127,
-  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7128, +  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7128,
-  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7129, +  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7129,
-  XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb =7130, +  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7130,
-  XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq =7131, +  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7131,
-  XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq =7132, +  XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq =7132,
-  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7133, +  XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq =7133,
-  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7134, +  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7134,
-  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7135, +  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7135,
-  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7136, +  XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq =7136,
-  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7137, +  XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq =7137,
-  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7138, +  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7138,
-  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7139, +  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7139,
-  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7140, +  XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq =7140,
-  XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq =7141, +  XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq =7141,
-  XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq =7142, +  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7142,
-  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7143, +  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7143,
-  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7144, +  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7144,
-  XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq =7145, +  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7145,
-  XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq =7146, +  XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq =7146,
-  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7147, +  XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq =7147,
-  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7148, +  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7148,
-  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7149, +  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7149,
-  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7150, +  XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq =7150,
-  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq =7151, +  XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq =7151,
-  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq =7152, +  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7152,
-  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7153, +  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7153,
-  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7154, +  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7154,
-  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq =7155, +  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7155,
-  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq =7156, +  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7156,
-  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7157, +  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7157,
-  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7158, +  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7158,
-  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7159, +  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7159,
-  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7160, +  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7160,
-  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7161, +  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7161,
-  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7162, +  XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq =7162,
-  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7163, +  XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq =7163,
-  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7164, +  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7164,
-  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7165, +  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7165,
-  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7166, +  XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq =7166,
-  XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb =7167, +  XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq =7167,
-  XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq =7168, +  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7168,
-  XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq =7169, +  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7169,
-  XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7170, +  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7170,
-  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7171, +  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7171,
-  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7172, +  XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq =7172,
-  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7173, +  XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq =7173,
-  XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb =7174, +  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =7174,
-  XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq =7175, +  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =7175,
-  XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq =7176, +  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =7176,
-  XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7177, +  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =7177,
-  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7178, +  XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq =7178,
-  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7179, +  XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq =7179,
-  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7180, +  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =7180,
-  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7181, +  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =7181,
-  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7182, +  XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq =7182,
-  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7183, +  XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq =7183,
-  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7184, +  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =7184,
-  XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb =7185, +  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =7185,
-  XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq =7186, +  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =7186,
-  XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq =7187, +  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =7187,
-  XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7188, +  XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq =7188,
-  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7189, +  XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq =7189,
-  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7190, +  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =7190,
-  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7191, +  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =7191,
-  XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb =7192, +  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =7192,
-  XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq =7193, +  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =7193,
-  XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq =7194, +  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =7194,
-  XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7195, +  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =7195,
-  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7196, +  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =7196,
-  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7197, +  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =7197,
-  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7198, +  XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq =7198,
-  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7199, +  XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq =7199,
-  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7200, +  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7200,
-  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7201, +  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7201,
-  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7202, +  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7202,
-  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7203, +  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7203,
-  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7204, +  XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq =7204,
-  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7205, +  XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq =7205,
-  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7206, +  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7206,
-  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7207, +  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7207,
-  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7208, +  XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq =7208,
-  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7209, +  XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq =7209,
-  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7210, +  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7210,
-  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7211, +  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7211,
-  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7212, +  XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq =7212,
-  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7213, +  XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq =7213,
-  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7214, +  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7214,
-  XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq =7215, +  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7215,
-  XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq =7216, +  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7216,
-  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7217, +  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7217,
-  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7218, +  XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq =7218,
-  XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq =7219, +  XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq =7219,
-  XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq =7220, +  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7220,
-  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7221, +  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7221,
-  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7222, +  XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq =7222,
-  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7223, +  XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq =7223,
-  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7224, +  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7224,
-  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7225, +  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7225,
-  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7226, +  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7226,
-  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7227, +  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7227,
-  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7228, +  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7228,
-  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7229, +  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7229,
-  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7230, +  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7230,
-  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7231, +  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7231,
-  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7232, +  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7232,
-  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7233, +  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7233,
-  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7234, +  XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq =7234,
-  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7235, +  XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq =7235,
-  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7236, +  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7236,
-  XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb =7237, +  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7237,
-  XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq =7238, +  XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq =7238,
-  XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq =7239, +  XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq =7239,
-  XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7240, +  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7240,
-  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7241, +  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7241,
-  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7242, +  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7242,
-  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7243, +  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7243,
-  XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb =7244, +  XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 =7244,
-  XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq =7245, +  XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 =7245,
-  XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq =7246, +  XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 =7246,
-  XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7247, +  XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 =7247,
-  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7248, +  XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 =7248,
-  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7249, +  XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 =7249,
-  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7250, +  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 =7250,
-  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7251, +  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 =7251,
-  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7252, +  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 =7252,
-  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7253, +  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 =7253,
-  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7254, +  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 =7254,
-  XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb =7255, +  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 =7255,
-  XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq =7256, +  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 =7256,
-  XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq =7257, +  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 =7257,
-  XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7258, +  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 =7258,
-  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7259, +  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 =7259,
-  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7260, +  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 =7260,
-  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7261, +  XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 =7261,
-  XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb =7262, +  XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 =7262,
-  XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq =7263, +  XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 =7263,
-  XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq =7264, +  XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 =7264,
-  XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7265, +  XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 =7265,
-  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7266, +  XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 =7266,
-  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7267, +  XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 =7267,
-  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7268, +  XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 =7268,
-  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7269, +  XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 =7269,
-  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7270, +  XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 =7270,
-  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7271, +  XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 =7271,
-  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7272, +  XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 =7272,
-  XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb =7273, +  XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 =7273,
-  XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 =7274, +  XED_IFORM_VPMOVMSKB_GPR32d_XMMdq =7274,
-  XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 =7275, +  XED_IFORM_VPMOVMSKB_GPR32d_YMMqq =7275,
-  XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb =7276, +  XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 =7276,
-  XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 =7277, +  XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 =7277,
-  XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 =7278, +  XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 =7278,
-  XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 =7279, +  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 =7279,
-  XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =7280, +  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 =7280,
-  XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb =7281, +  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 =7281,
-  XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq =7282, +  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 =7282,
-  XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq =7283, +  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 =7283,
-  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7284, +  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 =7284,
-  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7285, +  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 =7285,
-  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7286, +  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 =7286,
-  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7287, +  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 =7287,
-  XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb =7288, +  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 =7288,
-  XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq =7289, +  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 =7289,
-  XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq =7290, +  XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 =7290,
-  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7291, +  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 =7291,
-  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7292, +  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 =7292,
-  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7293, +  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 =7293,
-  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7294, +  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 =7294,
-  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7295, +  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 =7295,
-  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7296, +  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 =7296,
-  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7297, +  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 =7297,
-  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7298, +  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 =7298,
-  XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq =7299, +  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 =7299,
-  XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq =7300, +  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 =7300,
-  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7301, +  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 =7301,
-  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7302, +  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 =7302,
-  XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq =7303, +  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 =7303,
-  XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq =7304, +  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 =7304,
-  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7305, +  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 =7305,
-  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7306, +  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 =7306,
-  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7307, +  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 =7307,
-  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7308, +  XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 =7308,
-  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq =7309, +  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 =7309,
-  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq =7310, +  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 =7310,
-  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7311, +  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 =7311,
-  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7312, +  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 =7312,
-  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq =7313, +  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 =7313,
-  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq =7314, +  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 =7314,
-  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7315, +  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 =7315,
-  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7316, +  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 =7316,
-  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7317, +  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 =7317,
-  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7318, +  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 =7318,
-  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7319, +  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 =7319,
-  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7320, +  XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 =7320,
-  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7321, +  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 =7321,
-  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7322, +  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 =7322,
-  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7323, +  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 =7323,
-  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7324, +  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 =7324,
-  XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb =7325, +  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 =7325,
-  XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq =7326, +  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 =7326,
-  XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq =7327, +  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 =7327,
-  XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7328, +  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 =7328,
-  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7329, +  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 =7329,
-  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7330, +  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 =7330,
-  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7331, +  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 =7331,
-  XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb =7332, +  XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 =7332,
-  XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq =7333, +  XED_IFORM_VPMOVSXBD_XMMdq_MEMd =7333,
-  XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq =7334, +  XED_IFORM_VPMOVSXBD_XMMdq_XMMd =7334,
-  XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7335, +  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 =7335,
-  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7336, +  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 =7336,
-  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7337, +  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 =7337,
-  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7338, +  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 =7338,
-  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7339, +  XED_IFORM_VPMOVSXBD_YMMqq_MEMq =7339,
-  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7340, +  XED_IFORM_VPMOVSXBD_YMMqq_XMMq =7340,
-  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7341, +  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =7341,
-  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7342, +  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =7342,
-  XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq =7343, +  XED_IFORM_VPMOVSXBQ_XMMdq_MEMw =7343,
-  XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq =7344, +  XED_IFORM_VPMOVSXBQ_XMMdq_XMMw =7344,
-  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7345, +  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =7345,
-  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7346, +  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =7346,
-  XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq =7347, +  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =7347,
-  XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq =7348, +  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =7348,
-  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7349, +  XED_IFORM_VPMOVSXBQ_YMMqq_MEMd =7349,
-  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7350, +  XED_IFORM_VPMOVSXBQ_YMMqq_XMMd =7350,
-  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7351, +  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =7351,
-  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7352, +  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =7352,
-  XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq =7353, +  XED_IFORM_VPMOVSXBW_XMMdq_MEMq =7353,
-  XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq =7354, +  XED_IFORM_VPMOVSXBW_XMMdq_XMMq =7354,
-  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7355, +  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 =7355,
-  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7356, +  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 =7356,
-  XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq =7357, +  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 =7357,
-  XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq =7358, +  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 =7358,
-  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7359, +  XED_IFORM_VPMOVSXBW_YMMqq_MEMdq =7359,
-  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7360, +  XED_IFORM_VPMOVSXBW_YMMqq_XMMdq =7360,
-  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7361, +  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =7361,
-  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7362, +  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =7362,
-  XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq =7363, +  XED_IFORM_VPMOVSXDQ_XMMdq_MEMq =7363,
-  XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq =7364, +  XED_IFORM_VPMOVSXDQ_XMMdq_XMMq =7364,
-  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7365, +  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =7365,
-  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7366, +  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =7366,
-  XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq =7367, +  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =7367,
-  XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq =7368, +  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =7368,
-  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7369, +  XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq =7369,
-  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7370, +  XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq =7370,
-  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7371, +  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =7371,
-  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7372, +  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =7372,
-  XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq =7373, +  XED_IFORM_VPMOVSXWD_XMMdq_MEMq =7373,
-  XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq =7374, +  XED_IFORM_VPMOVSXWD_XMMdq_XMMq =7374,
-  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =7375, +  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 =7375,
-  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =7376, +  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 =7376,
-  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =7377, +  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 =7377,
-  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =7378, +  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 =7378,
-  XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq =7379, +  XED_IFORM_VPMOVSXWD_YMMqq_MEMdq =7379,
-  XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq =7380, +  XED_IFORM_VPMOVSXWD_YMMqq_XMMdq =7380,
-  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =7381, +  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =7381,
-  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =7382, +  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =7382,
-  XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq =7383, +  XED_IFORM_VPMOVSXWQ_XMMdq_MEMd =7383,
-  XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq =7384, +  XED_IFORM_VPMOVSXWQ_XMMdq_XMMd =7384,
-  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7385, +  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =7385,
-  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7386, +  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =7386,
-  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7387, +  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =7387,
-  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7388, +  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =7388,
-  XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq =7389, +  XED_IFORM_VPMOVSXWQ_YMMqq_MEMq =7389,
-  XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq =7390, +  XED_IFORM_VPMOVSXWQ_YMMqq_XMMq =7390,
-  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7391, +  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =7391,
-  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7392, +  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =7392,
-  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq =7393, +  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 =7393,
-  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq =7394, +  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 =7394,
-  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7395, +  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 =7395,
-  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7396, +  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 =7396,
-  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq =7397, +  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 =7397,
-  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq =7398, +  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 =7398,
-  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7399, +  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 =7399,
-  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7400, +  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 =7400,
-  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7401, +  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 =7401,
-  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7402, +  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 =7402,
-  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq =7403, +  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 =7403,
-  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq =7404, +  XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 =7404,
-  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7405, +  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 =7405,
-  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7406, +  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 =7406,
-  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq =7407, +  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 =7407,
-  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq =7408, +  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 =7408,
-  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7409, +  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 =7409,
-  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7410, +  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 =7410,
-  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7411, +  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 =7411,
-  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7412, +  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 =7412,
-  XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq =7413, +  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 =7413,
-  XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq =7414, +  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 =7414,
-  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7415, +  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 =7415,
-  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7416, +  XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 =7416,
-  XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq =7417, +  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 =7417,
-  XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq =7418, +  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 =7418,
-  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7419, +  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 =7419,
-  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7420, +  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 =7420,
-  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7421, +  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 =7421,
-  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7422, +  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 =7422,
-  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7423, +  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 =7423,
-  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7424, +  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 =7424,
-  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7425, +  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 =7425,
-  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7426, +  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 =7426,
-  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7427, +  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 =7427,
-  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7428, +  XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 =7428,
-  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7429, +  XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 =7429,
-  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7430, +  XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 =7430,
-  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7431, +  XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 =7431,
-  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7432, +  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 =7432,
-  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7433, +  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 =7433,
-  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7434, +  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 =7434,
-  XED_IFORM_VPTEST_XMMdq_MEMdq =7435, +  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 =7435,
-  XED_IFORM_VPTEST_XMMdq_XMMdq =7436, +  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 =7436,
-  XED_IFORM_VPTEST_YMMqq_MEMqq =7437, +  XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 =7437,
-  XED_IFORM_VPTEST_YMMqq_YMMqq =7438, +  XED_IFORM_VPMOVZXBD_XMMdq_MEMd =7438,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =7439, +  XED_IFORM_VPMOVZXBD_XMMdq_XMMd =7439,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =7440, +  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 =7440,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =7441, +  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 =7441,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =7442, +  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 =7442,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =7443, +  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 =7443,
-  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =7444, +  XED_IFORM_VPMOVZXBD_YMMqq_MEMq =7444,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =7445, +  XED_IFORM_VPMOVZXBD_YMMqq_XMMq =7445,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =7446, +  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =7446,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =7447, +  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =7447,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =7448, +  XED_IFORM_VPMOVZXBQ_XMMdq_MEMw =7448,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =7449, +  XED_IFORM_VPMOVZXBQ_XMMdq_XMMw =7449,
-  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =7450, +  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =7450,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =7451, +  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =7451,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =7452, +  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =7452,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =7453, +  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =7453,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =7454, +  XED_IFORM_VPMOVZXBQ_YMMqq_MEMd =7454,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =7455, +  XED_IFORM_VPMOVZXBQ_YMMqq_XMMd =7455,
-  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =7456, +  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =7456,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =7457, +  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =7457,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =7458, +  XED_IFORM_VPMOVZXBW_XMMdq_MEMq =7458,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =7459, +  XED_IFORM_VPMOVZXBW_XMMdq_XMMq =7459,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =7460, +  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 =7460,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =7461, +  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 =7461,
-  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =7462, +  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 =7462,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =7463, +  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 =7463,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =7464, +  XED_IFORM_VPMOVZXBW_YMMqq_MEMdq =7464,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =7465, +  XED_IFORM_VPMOVZXBW_YMMqq_XMMdq =7465,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =7466, +  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =7466,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =7467, +  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =7467,
-  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =7468, +  XED_IFORM_VPMOVZXDQ_XMMdq_MEMq =7468,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =7469, +  XED_IFORM_VPMOVZXDQ_XMMdq_XMMq =7469,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =7470, +  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =7470,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =7471, +  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =7471,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =7472, +  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =7472,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =7473, +  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =7473,
-  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =7474, +  XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq =7474,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =7475, +  XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq =7475,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =7476, +  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =7476,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =7477, +  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =7477,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =7478, +  XED_IFORM_VPMOVZXWD_XMMdq_MEMq =7478,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =7479, +  XED_IFORM_VPMOVZXWD_XMMdq_XMMq =7479,
-  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =7480, +  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 =7480,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =7481, +  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 =7481,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =7482, +  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 =7482,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =7483, +  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 =7483,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =7484, +  XED_IFORM_VPMOVZXWD_YMMqq_MEMdq =7484,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =7485, +  XED_IFORM_VPMOVZXWD_YMMqq_XMMdq =7485,
-  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =7486, +  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =7486,
-  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq =7487, +  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =7487,
-  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq =7488, +  XED_IFORM_VPMOVZXWQ_XMMdq_MEMd =7488,
-  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7489, +  XED_IFORM_VPMOVZXWQ_XMMdq_XMMd =7489,
-  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7490, +  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =7490,
-  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq =7491, +  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =7491,
-  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq =7492, +  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =7492,
-  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7493, +  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =7493,
-  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7494, +  XED_IFORM_VPMOVZXWQ_YMMqq_MEMq =7494,
-  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7495, +  XED_IFORM_VPMOVZXWQ_YMMqq_XMMq =7495,
-  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7496, +  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =7496,
-  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq =7497, +  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =7497,
-  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq =7498, +  XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq =7498,
-  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7499, +  XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq =7499,
-  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7500, +  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 =7500,
-  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq =7501, +  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 =7501,
-  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq =7502, +  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 =7502,
-  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7503, +  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 =7503,
-  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7504, +  XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq =7504,
-  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7505, +  XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq =7505,
-  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7506, +  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 =7506,
-  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq =7507, +  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 =7507,
-  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq =7508, +  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq =7508,
-  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7509, +  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq =7509,
-  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7510, +  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7510,
-  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq =7511, +  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7511,
-  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq =7512, +  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7512,
-  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7513, +  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7513,
-  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7514, +  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq =7514,
-  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7515, +  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq =7515,
-  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7516, +  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7516,
-  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq =7517, +  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7517,
-  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq =7518, +  XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq =7518,
-  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7519, +  XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq =7519,
-  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7520, +  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7520,
-  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq =7521, +  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7521,
-  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq =7522, +  XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq =7522,
-  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7523, +  XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq =7523,
-  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7524, +  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7524,
-  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7525, +  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7525,
-  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7526, +  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7526,
-  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq =7527, +  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7527,
-  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq =7528, +  XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq =7528,
-  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7529, +  XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq =7529,
-  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7530, +  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7530,
-  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq =7531, +  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7531,
-  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq =7532, +  XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq =7532,
-  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7533, +  XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq =7533,
-  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7534, +  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7534,
-  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7535, +  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7535,
-  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7536, +  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7536,
-  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq =7537, +  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7537,
-  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq =7538, +  XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq =7538,
-  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7539, +  XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq =7539,
-  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7540, +  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7540,
-  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq =7541, +  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7541,
-  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq =7542, +  XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq =7542,
-  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7543, +  XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq =7543,
-  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7544, +  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7544,
-  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7545, +  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7545,
-  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7546, +  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7546,
-  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq =7547, +  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7547,
-  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq =7548, +  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7548,
-  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7549, +  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7549,
-  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7550, +  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7550,
-  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq =7551, +  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7551,
-  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq =7552, +  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7552,
-  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7553, +  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7553,
-  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7554, +  XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq =7554,
-  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7555, +  XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq =7555,
-  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7556, +  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7556,
-  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq =7557, +  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7557,
-  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq =7558, +  XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq =7558,
-  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7559, +  XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq =7559,
-  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7560, +  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7560,
-  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq =7561, +  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7561,
-  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq =7562, +  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7562,
-  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7563, +  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7563,
-  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7564, +  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 =7564,
-  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7565, +  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 =7565,
-  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7566, +  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 =7566,
-  XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq =7567, +  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 =7567,
-  XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq =7568, +  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 =7568,
-  XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq =7569, +  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 =7569,
-  XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq =7570, +  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq =7570,
-  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7571, +  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq =7571,
-  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7572, +  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 =7572,
-  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7573, +  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 =7573,
-  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7574, +  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq =7574,
-  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7575, +  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq =7575,
-  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7576, +  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 =7576,
-  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7577, +  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 =7577,
-  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7578, +  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 =7578,
-  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7579, +  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 =7579,
-  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7580, +  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 =7580,
-  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7581, +  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 =7581,
-  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7582, +  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 =7582,
-  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =7583, +  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 =7583,
-  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =7584, +  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 =7584,
-  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =7585, +  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 =7585,
-  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =7586, +  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =7586,
-  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =7587, +  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =7587,
-  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =7588, +  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =7588,
-  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =7589, +  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =7589,
-  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =7590, +  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 =7590,
-  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =7591, +  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 =7591,
-  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =7592, +  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =7592,
-  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =7593, +  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =7593,
-  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =7594, +  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =7594,
-  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =7595, +  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =7595,
-  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =7596, +  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =7596,
-  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =7597, +  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =7597,
-  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =7598, +  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 =7598,
-  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 =7599, +  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 =7599,
-  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 =7600, +  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 =7600,
-  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 =7601, +  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 =7601,
-  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 =7602, +  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 =7602,
-  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =7603, +  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 =7603,
-  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =7604, +  XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq =7604,
-  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 =7605, +  XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq =7605,
-  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 =7606, +  XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq =7606,
-  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 =7607, +  XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq =7607,
-  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 =7608, +  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7608,
-  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =7609, +  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7609,
-  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =7610, +  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7610,
-  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7611, +  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7611,
-  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7612, +  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7612,
-  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7613, +  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7613,
-  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7614, +  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7614,
-  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =7615, +  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7615,
-  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =7616, +  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7616,
-  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =7617, +  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7617,
-  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =7618, +  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7618,
-  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =7619, +  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7619,
-  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =7620, +  XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq =7620,
-  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =7621, +  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq =7621,
-  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =7622, +  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq =7622,
-  XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 =7623, +  XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7623,
-  XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 =7624, +  XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7624,
-  XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 =7625, +  XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7625,
-  XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 =7626, +  XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7626,
-  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =7627, +  XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7627,
-  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =7628, +  XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7628,
-  XED_IFORM_VRCPPS_XMMdq_MEMdq =7629, +  XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7629,
-  XED_IFORM_VRCPPS_XMMdq_XMMdq =7630, +  XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7630,
-  XED_IFORM_VRCPPS_YMMqq_MEMqq =7631, +  XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7631,
-  XED_IFORM_VRCPPS_YMMqq_YMMqq =7632, +  XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7632,
-  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7633, +  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7633,
-  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7634, +  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7634,
-  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd =7635, +  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7635,
-  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd =7636, +  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7636,
-  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7637, +  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7637,
-  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =7638, +  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7638,
-  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7639, +  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7639,
-  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =7640, +  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7640,
-  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7641, +  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7641,
-  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =7642, +  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7642,
-  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7643, +  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7643,
-  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =7644, +  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7644,
-  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7645, +  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7645,
-  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =7646, +  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7646,
-  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7647, +  XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7647,
-  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =7648, +  XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7648,
-  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7649, +  XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7649,
-  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =7650, +  XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7650,
-  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7651, +  XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7651,
-  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =7652, +  XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7652,
-  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7653, +  XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7653,
-  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =7654, +  XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7654,
-  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =7655, +  XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7655,
-  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =7656, +  XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7656,
-  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =7657, +  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7657,
-  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =7658, +  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7658,
-  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =7659, +  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7659,
-  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =7660, +  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7660,
-  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7661, +  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7661,
-  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =7662, +  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7662,
-  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7663, +  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7663,
-  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =7664, +  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7664,
-  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =7665, +  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7665,
-  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =7666, +  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7666,
-  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7667, +  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7667,
-  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =7668, +  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7668,
-  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7669, +  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7669,
-  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =7670, +  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7670,
-  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =7671, +  XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb =7671,
-  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =7672, +  XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq =7672,
-  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7673, +  XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb =7673,
-  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =7674, +  XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq =7674,
-  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7675, +  XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq =7675,
-  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =7676, +  XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb =7676,
-  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =7677, +  XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq =7677,
-  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =7678, +  XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb =7678,
-  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =7679, +  XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq =7679,
-  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =7680, +  XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq =7680,
-  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =7681, +  XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb =7681,
-  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =7682, +  XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq =7682,
-  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =7683, +  XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb =7683,
-  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =7684, +  XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq =7684,
-  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb =7685, +  XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq =7685,
-  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb =7686, +  XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb =7686,
-  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb =7687, +  XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq =7687,
-  XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb =7688, +  XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb =7688,
-  XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb =7689, +  XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq =7689,
-  XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb =7690, +  XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq =7690,
-  XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb =7691, +  XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq =7691,
-  XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb =7692, +  XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq =7692,
-  XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb =7693, +  XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 =7693,
-  XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb =7694, +  XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 =7694,
-  XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb =7695, +  XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq =7695,
-  XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb =7696, +  XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq =7696,
-  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 =7697, +  XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 =7697,
-  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 =7698, +  XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 =7698,
-  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 =7699, +  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 =7699,
-  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 =7700, +  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 =7700,
-  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =7701, +  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =7701,
-  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =7702, +  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 =7702,
-  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 =7703, +  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 =7703,
-  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 =7704, +  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =7704,
-  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 =7705, +  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =7705,
-  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 =7706, +  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =7706,
-  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =7707, +  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =7707,
-  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =7708, +  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 =7708,
-  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7709, +  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 =7709,
-  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7710, +  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =7710,
-  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7711, +  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =7711,
-  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7712, +  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =7712,
-  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =7713, +  XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq =7713,
-  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =7714, +  XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq =7714,
-  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =7715, +  XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq =7715,
-  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =7716, +  XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq =7716,
-  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =7717, +  XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq =7717,
-  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =7718, +  XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq =7718,
-  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =7719, +  XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq =7719,
-  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =7720, +  XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq =7720,
-  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =7721, +  XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq =7721,
-  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =7722, +  XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq =7722,
-  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =7723, +  XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq =7723,
-  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =7724, +  XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq =7724,
-  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =7725, +  XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq =7725,
-  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =7726, +  XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq =7726,
-  XED_IFORM_VRSQRTPS_XMMdq_MEMdq =7727, +  XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq =7727,
-  XED_IFORM_VRSQRTPS_XMMdq_XMMdq =7728, +  XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq =7728,
-  XED_IFORM_VRSQRTPS_YMMqq_MEMqq =7729, +  XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq =7729,
-  XED_IFORM_VRSQRTPS_YMMqq_YMMqq =7730, +  XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq =7730,
-  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7731, +  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7731,
-  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7732, +  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7732,
-  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd =7733, +  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7733,
-  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd =7734, +  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7734,
-  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7735, +  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7735,
-  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7736, +  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7736,
-  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =7737, +  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7737,
-  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =7738, +  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7738,
-  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =7739, +  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7739,
-  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =7740, +  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7740,
-  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7741, +  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7741,
-  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7742, +  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7742,
-  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =7743, +  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7743,
-  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =7744, +  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7744,
-  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =7745, +  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7745,
-  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =7746, +  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7746,
-  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7747, +  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7747,
-  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7748, +  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7748,
-  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =7749, +  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7749,
-  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =7750, +  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7750,
-  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =7751, +  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7751,
-  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =7752, +  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7752,
-  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7753, +  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7753,
-  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7754, +  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7754,
-  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7755, +  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7755,
-  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7756, +  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7756,
-  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7757, +  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7757,
-  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7758, +  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7758,
-  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =7759, +  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7759,
-  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =7760, +  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7760,
-  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =7761, +  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =7761,
-  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =7762, +  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =7762,
-  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 =7763, +  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =7763,
-  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 =7764, +  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =7764,
-  XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =7765, +  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =7765,
-  XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =7766, +  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =7766,
-  XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =7767, +  XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq =7767,
-  XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =7768, +  XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq =7768,
-  XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =7769, +  XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq =7769,
-  XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =7770, +  XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq =7770,
-  XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =7771, +  XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq =7771,
-  XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =7772, +  XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq =7772,
-  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =7773, +  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7773,
-  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =7774, +  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7774,
-  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =7775, +  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7775,
-  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =7776, +  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7776,
-  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 =7777, +  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7777,
-  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 =7778, +  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7778,
-  XED_IFORM_VSHA512MSG1_YMMu64_XMMu64 =7779, +  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7779,
-  XED_IFORM_VSHA512MSG2_YMMu64_YMMu64 =7780, +  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7780,
-  XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64 =7781, +  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7781,
-  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =7782, +  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7782,
-  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =7783, +  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7783,
-  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =7784, +  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7784,
-  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =7785, +  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7785,
-  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =7786, +  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7786,
-  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =7787, +  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7787,
-  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =7788, +  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7788,
-  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =7789, +  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7789,
-  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7790, +  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7790,
-  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7791, +  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7791,
-  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7792, +  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7792,
-  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7793, +  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7793,
-  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7794, +  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7794,
-  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7795, +  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7795,
-  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7796, +  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7796,
-  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7797, +  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7797,
-  XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb =7798, +  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7798,
-  XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb =7799, +  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7799,
-  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =7800, +  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7800,
-  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =7801, +  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7801,
-  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =7802, +  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7802,
-  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =7803, +  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =7803,
-  XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb =7804, +  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =7804,
-  XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb =7805, +  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =7805,
-  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =7806, +  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =7806,
-  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =7807, +  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =7807,
-  XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb =7808, +  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =7808,
-  XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb =7809, +  XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq =7809,
-  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =7810, +  XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq =7810,
-  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =7811, +  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7811,
-  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =7812, +  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7812,
-  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =7813, +  XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq =7813,
-  XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb =7814, +  XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq =7814,
-  XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb =7815, +  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7815,
-  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =7816, +  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7816,
-  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =7817, +  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7817,
-  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32 =7818, +  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7818,
-  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32 =7819, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 =7819,
-  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32 =7820, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 =7820,
-  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32 =7821, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 =7821,
-  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 =7822, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 =7822,
-  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 =7823, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 =7823,
-  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32 =7824, +  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 =7824,
-  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32 =7825, +  XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb =7825,
-  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32 =7826, +  XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb =7826,
-  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32 =7827, +  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7827,
-  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32 =7828, +  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7828,
-  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32 =7829, +  XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb =7829,
-  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32 =7830, +  XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb =7830,
-  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32 =7831, +  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7831,
-  XED_IFORM_VSQRTPD_XMMdq_MEMdq =7832, +  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7832,
-  XED_IFORM_VSQRTPD_XMMdq_XMMdq =7833, +  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7833,
-  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 =7834, +  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7834,
-  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 =7835, +  XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb =7835,
-  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 =7836, +  XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb =7836,
-  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 =7837, +  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7837,
-  XED_IFORM_VSQRTPD_YMMqq_MEMqq =7838, +  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7838,
-  XED_IFORM_VSQRTPD_YMMqq_YMMqq =7839, +  XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb =7839,
-  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 =7840, +  XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb =7840,
-  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =7841, +  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7841,
-  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =7842, +  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7842,
-  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =7843, +  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7843,
-  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =7844, +  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7844,
-  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =7845, +  XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb =7845,
-  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =7846, +  XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb =7846,
-  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =7847, +  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7847,
-  XED_IFORM_VSQRTPS_XMMdq_MEMdq =7848, +  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7848,
-  XED_IFORM_VSQRTPS_XMMdq_XMMdq =7849, +  XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb =7849,
-  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 =7850, +  XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb =7850,
-  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 =7851, +  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7851,
-  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 =7852, +  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7852,
-  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 =7853, +  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7853,
-  XED_IFORM_VSQRTPS_YMMqq_MEMqq =7854, +  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7854,
-  XED_IFORM_VSQRTPS_YMMqq_YMMqq =7855, +  XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq =7855,
-  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 =7856, +  XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq =7856,
-  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =7857, +  XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq =7857,
-  XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq =7858, +  XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq =7858,
-  XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq =7859, +  XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq =7859,
-  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7860, +  XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq =7860,
-  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7861, +  XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq =7861,
-  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7862, +  XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq =7862,
-  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7863, +  XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq =7863,
-  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd =7864, +  XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq =7864,
-  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd =7865, +  XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq =7865,
-  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7866, +  XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq =7866,
-  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7867, +  XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb =7867,
-  XED_IFORM_VSTMXCSR_MEMd =7868, +  XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq =7868,
-  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq =7869, +  XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq =7869,
-  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq =7870, +  XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7870,
-  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7871, +  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7871,
-  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7872, +  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7872,
-  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =7873, +  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7873,
-  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =7874, +  XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb =7874,
-  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq =7875, +  XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq =7875,
-  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq =7876, +  XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq =7876,
-  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =7877, +  XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7877,
-  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =7878, +  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7878,
-  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7879, +  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7879,
-  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7880, +  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7880,
-  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =7881, +  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7881,
-  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =7882, +  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7882,
-  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =7883, +  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7883,
-  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =7884, +  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7884,
-  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq =7885, +  XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb =7885,
-  XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq =7886, +  XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 =7886,
-  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7887, +  XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 =7887,
-  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7888, +  XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb =7888,
-  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =7889, +  XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 =7889,
-  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =7890, +  XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 =7890,
-  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq =7891, +  XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 =7891,
-  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq =7892, +  XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =7892,
-  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =7893, +  XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb =7893,
-  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =7894, +  XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq =7894,
-  XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq =7895, +  XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq =7895,
-  XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq =7896, +  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7896,
-  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7897, +  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7897,
-  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7898, +  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7898,
-  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =7899, +  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7899,
-  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =7900, +  XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb =7900,
-  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd =7901, +  XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq =7901,
-  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd =7902, +  XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq =7902,
-  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7903, +  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7903,
-  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7904, +  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7904,
-  XED_IFORM_VTESTPD_XMMdq_MEMdq =7905, +  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7905,
-  XED_IFORM_VTESTPD_XMMdq_XMMdq =7906, +  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7906,
-  XED_IFORM_VTESTPD_YMMqq_MEMqq =7907, +  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7907,
-  XED_IFORM_VTESTPD_YMMqq_YMMqq =7908, +  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7908,
-  XED_IFORM_VTESTPS_XMMdq_MEMdq =7909, +  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7909,
-  XED_IFORM_VTESTPS_XMMdq_XMMdq =7910, +  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7910,
-  XED_IFORM_VTESTPS_YMMqq_MEMqq =7911, +  XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq =7911,
-  XED_IFORM_VTESTPS_YMMqq_YMMqq =7912, +  XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq =7912,
-  XED_IFORM_VUCOMISD_XMMdq_MEMq =7913, +  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7913,
-  XED_IFORM_VUCOMISD_XMMdq_XMMq =7914, +  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7914,
-  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 =7915, +  XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq =7915,
-  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 =7916, +  XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq =7916,
-  XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512 =7917, +  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7917,
-  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512 =7918, +  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7918,
-  XED_IFORM_VUCOMISS_XMMdq_MEMd =7919, +  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7919,
-  XED_IFORM_VUCOMISS_XMMdq_XMMd =7920, +  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7920,
-  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 =7921, +  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq =7921,
-  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 =7922, +  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq =7922,
-  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq =7923, +  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7923,
-  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq =7924, +  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7924,
-  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7925, +  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq =7925,
-  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7926, +  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq =7926,
-  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =7927, +  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7927,
-  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =7928, +  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7928,
-  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq =7929, +  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7929,
-  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq =7930, +  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7930,
-  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =7931, +  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7931,
-  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =7932, +  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7932,
-  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq =7933, +  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7933,
-  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq =7934, +  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7934,
-  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7935, +  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7935,
-  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7936, +  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7936,
-  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =7937, +  XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb =7937,
-  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =7938, +  XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq =7938,
-  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq =7939, +  XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq =7939,
-  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq =7940, +  XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7940,
-  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =7941, +  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7941,
-  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =7942, +  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7942,
-  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq =7943, +  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7943,
-  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq =7944, +  XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb =7944,
-  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =7945, +  XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq =7945,
-  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =7946, +  XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq =7946,
-  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =7947, +  XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7947,
-  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =7948, +  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7948,
-  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq =7949, +  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7949,
-  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq =7950, +  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7950,
-  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =7951, +  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7951,
-  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =7952, +  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7952,
-  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq =7953, +  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7953,
-  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq =7954, +  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7954,
-  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =7955, +  XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb =7955,
-  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =7956, +  XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq =7956,
-  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =7957, +  XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq =7957,
-  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =7958, +  XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7958,
-  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq =7959, +  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7959,
-  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq =7960, +  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7960,
-  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =7961, +  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7961,
-  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =7962, +  XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb =7962,
-  XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq =7963, +  XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq =7963,
-  XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq =7964, +  XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq =7964,
-  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7965, +  XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7965,
-  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7966, +  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7966,
-  XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq =7967, +  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7967,
-  XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq =7968, +  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7968,
-  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7969, +  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7969,
-  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7970, +  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7970,
-  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7971, +  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7971,
-  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7972, +  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7972,
-  XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq =7973, +  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7973,
-  XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq =7974, +  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7974,
-  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7975, +  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7975,
-  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7976, +  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7976,
-  XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq =7977, +  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7977,
-  XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq =7978, +  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7978,
-  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7979, +  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7979,
-  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7980, +  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7980,
-  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7981, +  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7981,
-  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7982, +  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7982,
-  XED_IFORM_VZEROALL =7983, +  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7983,
-  XED_IFORM_VZEROUPPER =7984, +  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7984,
-  XED_IFORM_WBINVD =7985, +  XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq =7985,
-  XED_IFORM_WBNOINVD =7986, +  XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq =7986,
-  XED_IFORM_WRFSBASE_GPRy =7987, +  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7987,
-  XED_IFORM_WRGSBASE_GPRy =7988, +  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7988,
-  XED_IFORM_WRMSR =7989, +  XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq =7989,
-  XED_IFORM_WRMSRLIST =7990, +  XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq =7990,
-  XED_IFORM_WRMSRNS =7991, +  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7991,
-  XED_IFORM_WRPKRU =7992, +  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7992,
-  XED_IFORM_WRSSD_MEMu32_GPR32u32 =7993, +  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7993,
-  XED_IFORM_WRSSD_MEMu32_GPR32u32_APX =7994, +  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7994,
-  XED_IFORM_WRSSQ_MEMu64_GPR64u64 =7995, +  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7995,
-  XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX =7996, +  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7996,
-  XED_IFORM_WRUSSD_MEMu32_GPR32u32 =7997, +  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7997,
-  XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX =7998, +  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7998,
-  XED_IFORM_WRUSSQ_MEMu64_GPR64u64 =7999, +  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7999,
-  XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX =8000, +  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8000,
-  XED_IFORM_XABORT_IMMb =8001, +  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8001,
-  XED_IFORM_XADD_GPR8_GPR8 =8002, +  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8002,
-  XED_IFORM_XADD_GPRv_GPRv =8003, +  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8003,
-  XED_IFORM_XADD_MEMb_GPR8 =8004, +  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8004,
-  XED_IFORM_XADD_MEMv_GPRv =8005, +  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8005,
-  XED_IFORM_XADD_LOCK_MEMb_GPR8 =8006, +  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8006,
-  XED_IFORM_XADD_LOCK_MEMv_GPRv =8007, +  XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb =8007,
-  XED_IFORM_XBEGIN_RELBRz =8008, +  XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq =8008,
-  XED_IFORM_XCHG_GPR8_GPR8 =8009, +  XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq =8009,
-  XED_IFORM_XCHG_GPRv_GPRv =8010, +  XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8010,
-  XED_IFORM_XCHG_GPRv_OrAX =8011, +  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =8011,
-  XED_IFORM_XCHG_MEMb_GPR8 =8012, +  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8012,
-  XED_IFORM_XCHG_MEMv_GPRv =8013, +  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8013,
-  XED_IFORM_XEND =8014, +  XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb =8014,
-  XED_IFORM_XGETBV =8015, +  XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq =8015,
-  XED_IFORM_XLAT =8016, +  XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq =8016,
-  XED_IFORM_XOR_AL_IMMb =8017, +  XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8017,
-  XED_IFORM_XOR_GPR8_GPR8_30 =8018, +  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =8018,
-  XED_IFORM_XOR_GPR8_GPR8_32 =8019, +  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8019,
-  XED_IFORM_XOR_GPR8_IMMb_80r6 =8020, +  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =8020,
-  XED_IFORM_XOR_GPR8_IMMb_82r6 =8021, +  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8021,
-  XED_IFORM_XOR_GPR8_MEMb =8022, +  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =8022,
-  XED_IFORM_XOR_GPR8i8_GPR8i8_APX =8023, +  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8023,
-  XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX =8024, +  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =8024,
-  XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX =8025, +  XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb =8025,
-  XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX =8026, +  XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq =8026,
-  XED_IFORM_XOR_GPR8i8_IMM8_APX =8027, +  XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq =8027,
-  XED_IFORM_XOR_GPR8i8_MEMi8_APX =8028, +  XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =8028,
-  XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX =8029, +  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =8029,
-  XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX =8030, +  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8030,
-  XED_IFORM_XOR_GPRv_GPRv_31 =8031, +  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8031,
-  XED_IFORM_XOR_GPRv_GPRv_33 =8032, +  XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb =8032,
-  XED_IFORM_XOR_GPRv_GPRv_APX =8033, +  XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq =8033,
-  XED_IFORM_XOR_GPRv_GPRv_GPRv_APX =8034, +  XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq =8034,
-  XED_IFORM_XOR_GPRv_GPRv_IMM8_APX =8035, +  XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =8035,
-  XED_IFORM_XOR_GPRv_GPRv_IMMz_APX =8036, +  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =8036,
-  XED_IFORM_XOR_GPRv_GPRv_MEMv_APX =8037, +  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8037,
-  XED_IFORM_XOR_GPRv_IMM8_APX =8038, +  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =8038,
-  XED_IFORM_XOR_GPRv_IMMb =8039, +  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =8039,
-  XED_IFORM_XOR_GPRv_IMMz =8040, +  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =8040,
-  XED_IFORM_XOR_GPRv_IMMz_APX =8041, +  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8041,
-  XED_IFORM_XOR_GPRv_MEMv =8042, +  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =8042,
-  XED_IFORM_XOR_GPRv_MEMv_APX =8043, +  XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb =8043,
-  XED_IFORM_XOR_GPRv_MEMv_GPRv_APX =8044, +  XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 =8044,
-  XED_IFORM_XOR_GPRv_MEMv_IMM8_APX =8045, +  XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 =8045,
-  XED_IFORM_XOR_GPRv_MEMv_IMMz_APX =8046, +  XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb =8046,
-  XED_IFORM_XOR_MEMb_GPR8 =8047, +  XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 =8047,
-  XED_IFORM_XOR_MEMb_IMMb_80r6 =8048, +  XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 =8048,
-  XED_IFORM_XOR_MEMb_IMMb_82r6 =8049, +  XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 =8049,
-  XED_IFORM_XOR_MEMi8_GPR8i8_APX =8050, +  XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =8050,
-  XED_IFORM_XOR_MEMi8_IMM8_APX =8051, +  XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb =8051,
-  XED_IFORM_XOR_MEMv_GPRv =8052, +  XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq =8052,
-  XED_IFORM_XOR_MEMv_GPRv_APX =8053, +  XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq =8053,
-  XED_IFORM_XOR_MEMv_IMM8_APX =8054, +  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =8054,
-  XED_IFORM_XOR_MEMv_IMMb =8055, +  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =8055,
-  XED_IFORM_XOR_MEMv_IMMz =8056, +  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8056,
-  XED_IFORM_XOR_MEMv_IMMz_APX =8057, +  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8057,
-  XED_IFORM_XOR_OrAX_IMMz =8058, +  XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb =8058,
-  XED_IFORM_XORPD_XMMxuq_MEMxuq =8059, +  XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq =8059,
-  XED_IFORM_XORPD_XMMxuq_XMMxuq =8060, +  XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq =8060,
-  XED_IFORM_XORPS_XMMxud_MEMxud =8061, +  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =8061,
-  XED_IFORM_XORPS_XMMxud_XMMxud =8062, +  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =8062,
-  XED_IFORM_XOR_LOCK_MEMb_GPR8 =8063, +  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8063,
-  XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 =8064, +  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =8064,
-  XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 =8065, +  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =8065,
-  XED_IFORM_XOR_LOCK_MEMv_GPRv =8066, +  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =8066,
-  XED_IFORM_XOR_LOCK_MEMv_IMMb =8067, +  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8067,
-  XED_IFORM_XOR_LOCK_MEMv_IMMz =8068, +  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =8068,
-  XED_IFORM_XRESLDTRK =8069, +  XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq =8069,
-  XED_IFORM_XRSTOR_MEMmxsave =8070, +  XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq =8070,
-  XED_IFORM_XRSTOR64_MEMmxsave =8071, +  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8071,
-  XED_IFORM_XRSTORS_MEMmxsave =8072, +  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8072,
-  XED_IFORM_XRSTORS64_MEMmxsave =8073, +  XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq =8073,
-  XED_IFORM_XSAVE_MEMmxsave =8074, +  XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq =8074,
-  XED_IFORM_XSAVE64_MEMmxsave =8075, +  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8075,
-  XED_IFORM_XSAVEC_MEMmxsave =8076, +  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8076,
-  XED_IFORM_XSAVEC64_MEMmxsave =8077, +  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8077,
-  XED_IFORM_XSAVEOPT_MEMmxsave =8078, +  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8078,
-  XED_IFORM_XSAVEOPT64_MEMmxsave =8079, +  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq =8079,
-  XED_IFORM_XSAVES_MEMmxsave =8080, +  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq =8080,
-  XED_IFORM_XSAVES64_MEMmxsave =8081, +  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8081,
-  XED_IFORM_XSETBV =8082, +  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8082,
-  XED_IFORM_XSTORE =8083, +  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq =8083,
-  XED_IFORM_XSUSLDTRK =8084, +  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq =8084,
-  XED_IFORM_XTEST =8085, +  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8085, +
+  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8086, +
+  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8087, +
+  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8088, +
+  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8089, +
+  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8090, +
+  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8091, +
+  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8092, +
+  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8093, +
+  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8094, +
+  XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb =8095, +
+  XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq =8096, +
+  XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq =8097, +
+  XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8098, +
+  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =8099, +
+  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8100, +
+  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8101, +
+  XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb =8102, +
+  XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq =8103, +
+  XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq =8104, +
+  XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8105, +
+  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =8106, +
+  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8107, +
+  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =8108, +
+  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =8109, +
+  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =8110, +
+  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8111, +
+  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =8112, +
+  XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq =8113, +
+  XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq =8114, +
+  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8115, +
+  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8116, +
+  XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq =8117, +
+  XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq =8118, +
+  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8119, +
+  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8120, +
+  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8121, +
+  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8122, +
+  XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq =8123, +
+  XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq =8124, +
+  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8125, +
+  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8126, +
+  XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq =8127, +
+  XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq =8128, +
+  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8129, +
+  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8130, +
+  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8131, +
+  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8132, +
+  XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq =8133, +
+  XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq =8134, +
+  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8135, +
+  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8136, +
+  XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq =8137, +
+  XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq =8138, +
+  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8139, +
+  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8140, +
+  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8141, +
+  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8142, +
+  XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq =8143, +
+  XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq =8144, +
+  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =8145, +
+  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =8146, +
+  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =8147, +
+  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =8148, +
+  XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq =8149, +
+  XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq =8150, +
+  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =8151, +
+  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =8152, +
+  XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq =8153, +
+  XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq =8154, +
+  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =8155, +
+  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =8156, +
+  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =8157, +
+  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =8158, +
+  XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq =8159, +
+  XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq =8160, +
+  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =8161, +
+  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =8162, +
+  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq =8163, +
+  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq =8164, +
+  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8165, +
+  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8166, +
+  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq =8167, +
+  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq =8168, +
+  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8169, +
+  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8170, +
+  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8171, +
+  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8172, +
+  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq =8173, +
+  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq =8174, +
+  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8175, +
+  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8176, +
+  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq =8177, +
+  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq =8178, +
+  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8179, +
+  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8180, +
+  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8181, +
+  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8182, +
+  XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq =8183, +
+  XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq =8184, +
+  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8185, +
+  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8186, +
+  XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq =8187, +
+  XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq =8188, +
+  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8189, +
+  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8190, +
+  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8191, +
+  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8192, +
+  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =8193, +
+  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =8194, +
+  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =8195, +
+  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =8196, +
+  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =8197, +
+  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =8198, +
+  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =8199, +
+  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =8200, +
+  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =8201, +
+  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =8202, +
+  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =8203, +
+  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =8204, +
+  XED_IFORM_VPTEST_XMMdq_MEMdq =8205, +
+  XED_IFORM_VPTEST_XMMdq_XMMdq =8206, +
+  XED_IFORM_VPTEST_YMMqq_MEMqq =8207, +
+  XED_IFORM_VPTEST_YMMqq_YMMqq =8208, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =8209, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =8210, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =8211, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =8212, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =8213, +
+  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =8214, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =8215, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =8216, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =8217, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =8218, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =8219, +
+  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =8220, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =8221, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =8222, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =8223, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =8224, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =8225, +
+  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =8226, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =8227, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =8228, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =8229, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =8230, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =8231, +
+  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =8232, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =8233, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =8234, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =8235, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =8236, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =8237, +
+  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =8238, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =8239, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =8240, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =8241, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =8242, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =8243, +
+  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =8244, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =8245, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =8246, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =8247, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =8248, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =8249, +
+  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =8250, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =8251, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =8252, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =8253, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =8254, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =8255, +
+  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =8256, +
+  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq =8257, +
+  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq =8258, +
+  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8259, +
+  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8260, +
+  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq =8261, +
+  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq =8262, +
+  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8263, +
+  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8264, +
+  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8265, +
+  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8266, +
+  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq =8267, +
+  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq =8268, +
+  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8269, +
+  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8270, +
+  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq =8271, +
+  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq =8272, +
+  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8273, +
+  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8274, +
+  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8275, +
+  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8276, +
+  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq =8277, +
+  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq =8278, +
+  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8279, +
+  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8280, +
+  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq =8281, +
+  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq =8282, +
+  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8283, +
+  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8284, +
+  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8285, +
+  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8286, +
+  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq =8287, +
+  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq =8288, +
+  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8289, +
+  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8290, +
+  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq =8291, +
+  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq =8292, +
+  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8293, +
+  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8294, +
+  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8295, +
+  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8296, +
+  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq =8297, +
+  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq =8298, +
+  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8299, +
+  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8300, +
+  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq =8301, +
+  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq =8302, +
+  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8303, +
+  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8304, +
+  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8305, +
+  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8306, +
+  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq =8307, +
+  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq =8308, +
+  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8309, +
+  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8310, +
+  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq =8311, +
+  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq =8312, +
+  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8313, +
+  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8314, +
+  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8315, +
+  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8316, +
+  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq =8317, +
+  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq =8318, +
+  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8319, +
+  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8320, +
+  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq =8321, +
+  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq =8322, +
+  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8323, +
+  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8324, +
+  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8325, +
+  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8326, +
+  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq =8327, +
+  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq =8328, +
+  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8329, +
+  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8330, +
+  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq =8331, +
+  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq =8332, +
+  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8333, +
+  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8334, +
+  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8335, +
+  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8336, +
+  XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq =8337, +
+  XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq =8338, +
+  XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq =8339, +
+  XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq =8340, +
+  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8341, +
+  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8342, +
+  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8343, +
+  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8344, +
+  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8345, +
+  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8346, +
+  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8347, +
+  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8348, +
+  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8349, +
+  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8350, +
+  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8351, +
+  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8352, +
+  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8353, +
+  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8354, +
+  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8355, +
+  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8356, +
+  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC =8357, +
+  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8358, +
+  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8359, +
+  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8360, +
+  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8361, +
+  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8362, +
+  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8363, +
+  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC =8364, +
+  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8365, +
+  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8366, +
+  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8367, +
+  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8368, +
+  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =8369, +
+  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8370, +
+  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8371, +
+  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =8372, +
+  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 =8373, +
+  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 =8374, +
+  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 =8375, +
+  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 =8376, +
+  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =8377, +
+  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8378, +
+  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 =8379, +
+  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 =8380, +
+  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 =8381, +
+  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 =8382, +
+  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =8383, +
+  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8384, +
+  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8385, +
+  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8386, +
+  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8387, +
+  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8388, +
+  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =8389, +
+  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =8390, +
+  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =8391, +
+  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =8392, +
+  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =8393, +
+  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =8394, +
+  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =8395, +
+  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =8396, +
+  XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8397, +
+  XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8398, +
+  XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8399, +
+  XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8400, +
+  XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8401, +
+  XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8402, +
+  XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 =8403, +
+  XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 =8404, +
+  XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 =8405, +
+  XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 =8406, +
+  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8407, +
+  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8408, +
+  XED_IFORM_VRCPPS_XMMdq_MEMdq =8409, +
+  XED_IFORM_VRCPPS_XMMdq_XMMdq =8410, +
+  XED_IFORM_VRCPPS_YMMqq_MEMqq =8411, +
+  XED_IFORM_VRCPPS_YMMqq_YMMqq =8412, +
+  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8413, +
+  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8414, +
+  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd =8415, +
+  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd =8416, +
+  XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8417, +
+  XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 =8418, +
+  XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8419, +
+  XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 =8420, +
+  XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8421, +
+  XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 =8422, +
+  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8423, +
+  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =8424, +
+  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8425, +
+  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =8426, +
+  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC =8427, +
+  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8428, +
+  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =8429, +
+  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8430, +
+  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =8431, +
+  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8432, +
+  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =8433, +
+  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC =8434, +
+  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8435, +
+  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =8436, +
+  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8437, +
+  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =8438, +
+  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8439, +
+  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =8440, +
+  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC =8441, +
+  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8442, +
+  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =8443, +
+  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8444, +
+  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8445, +
+  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =8446, +
+  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =8447, +
+  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =8448, +
+  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC =8449, +
+  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8450, +
+  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8451, +
+  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =8452, +
+  XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8453, +
+  XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 =8454, +
+  XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8455, +
+  XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 =8456, +
+  XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8457, +
+  XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 =8458, +
+  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8459, +
+  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =8460, +
+  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8461, +
+  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =8462, +
+  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC =8463, +
+  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8464, +
+  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =8465, +
+  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8466, +
+  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =8467, +
+  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8468, +
+  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =8469, +
+  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC =8470, +
+  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8471, +
+  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =8472, +
+  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8473, +
+  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =8474, +
+  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8475, +
+  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =8476, +
+  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC =8477, +
+  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8478, +
+  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =8479, +
+  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8480, +
+  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8481, +
+  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC =8482, +
+  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =8483, +
+  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =8484, +
+  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC =8485, +
+  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8486, +
+  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8487, +
+  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC =8488, +
+  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb =8489, +
+  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb =8490, +
+  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb =8491, +
+  XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb =8492, +
+  XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb =8493, +
+  XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb =8494, +
+  XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb =8495, +
+  XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb =8496, +
+  XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb =8497, +
+  XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb =8498, +
+  XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb =8499, +
+  XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb =8500, +
+  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 =8501, +
+  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 =8502, +
+  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 =8503, +
+  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 =8504, +
+  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =8505, +
+  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8506, +
+  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 =8507, +
+  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 =8508, +
+  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 =8509, +
+  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 =8510, +
+  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =8511, +
+  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8512, +
+  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8513, +
+  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8514, +
+  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8515, +
+  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8516, +
+  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =8517, +
+  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =8518, +
+  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =8519, +
+  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =8520, +
+  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =8521, +
+  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =8522, +
+  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =8523, +
+  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =8524, +
+  XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8525, +
+  XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8526, +
+  XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8527, +
+  XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8528, +
+  XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8529, +
+  XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8530, +
+  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =8531, +
+  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =8532, +
+  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =8533, +
+  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =8534, +
+  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8535, +
+  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8536, +
+  XED_IFORM_VRSQRTPS_XMMdq_MEMdq =8537, +
+  XED_IFORM_VRSQRTPS_XMMdq_XMMdq =8538, +
+  XED_IFORM_VRSQRTPS_YMMqq_MEMqq =8539, +
+  XED_IFORM_VRSQRTPS_YMMqq_YMMqq =8540, +
+  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8541, +
+  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8542, +
+  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd =8543, +
+  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd =8544, +
+  XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =8545, +
+  XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =8546, +
+  XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =8547, +
+  XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =8548, +
+  XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =8549, +
+  XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =8550, +
+  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8551, +
+  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8552, +
+  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8553, +
+  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8554, +
+  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =8555, +
+  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8556, +
+  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8557, +
+  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8558, +
+  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8559, +
+  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =8560, +
+  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =8561, +
+  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =8562, +
+  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =8563, +
+  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =8564, +
+  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8565, +
+  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8566, +
+  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8567, +
+  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8568, +
+  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =8569, +
+  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8570, +
+  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8571, +
+  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8572, +
+  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8573, +
+  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =8574, +
+  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8575, +
+  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8576, +
+  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =8577, +
+  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8578, +
+  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8579, +
+  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =8580, +
+  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =8581, +
+  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =8582, +
+  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =8583, +
+  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =8584, +
+  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 =8585, +
+  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 =8586, +
+  XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =8587, +
+  XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =8588, +
+  XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =8589, +
+  XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =8590, +
+  XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =8591, +
+  XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =8592, +
+  XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =8593, +
+  XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =8594, +
+  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =8595, +
+  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =8596, +
+  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =8597, +
+  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =8598, +
+  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 =8599, +
+  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 =8600, +
+  XED_IFORM_VSHA512MSG1_YMMu64_XMMu64 =8601, +
+  XED_IFORM_VSHA512MSG2_YMMu64_YMMu64 =8602, +
+  XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64 =8603, +
+  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8604, +
+  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8605, +
+  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8606, +
+  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8607, +
+  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8608, +
+  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8609, +
+  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8610, +
+  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8611, +
+  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =8612, +
+  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =8613, +
+  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =8614, +
+  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =8615, +
+  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =8616, +
+  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =8617, +
+  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =8618, +
+  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =8619, +
+  XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb =8620, +
+  XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb =8621, +
+  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8622, +
+  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8623, +
+  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8624, +
+  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8625, +
+  XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb =8626, +
+  XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb =8627, +
+  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8628, +
+  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8629, +
+  XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb =8630, +
+  XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb =8631, +
+  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8632, +
+  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8633, +
+  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8634, +
+  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8635, +
+  XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb =8636, +
+  XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb =8637, +
+  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8638, +
+  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8639, +
+  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32 =8640, +
+  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32 =8641, +
+  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32 =8642, +
+  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32 =8643, +
+  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 =8644, +
+  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 =8645, +
+  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32 =8646, +
+  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512 =8647, +
+  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32 =8648, +
+  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512 =8649, +
+  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32 =8650, +
+  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512 =8651, +
+  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32 =8652, +
+  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512 =8653, +
+  XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512 =8654, +
+  XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512 =8655, +
+  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32 =8656, +
+  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512 =8657, +
+  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32 =8658, +
+  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512 =8659, +
+  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32 =8660, +
+  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512 =8661, +
+  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32 =8662, +
+  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512 =8663, +
+  XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512 =8664, +
+  XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512 =8665, +
+  XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8666, +
+  XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8667, +
+  XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8668, +
+  XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8669, +
+  XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8670, +
+  XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8671, +
+  XED_IFORM_VSQRTPD_XMMdq_MEMdq =8672, +
+  XED_IFORM_VSQRTPD_XMMdq_XMMdq =8673, +
+  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 =8674, +
+  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 =8675, +
+  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 =8676, +
+  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 =8677, +
+  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC =8678, +
+  XED_IFORM_VSQRTPD_YMMqq_MEMqq =8679, +
+  XED_IFORM_VSQRTPD_YMMqq_YMMqq =8680, +
+  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 =8681, +
+  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8682, +
+  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =8683, +
+  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =8684, +
+  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =8685, +
+  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =8686, +
+  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC =8687, +
+  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8688, +
+  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8689, +
+  XED_IFORM_VSQRTPS_XMMdq_MEMdq =8690, +
+  XED_IFORM_VSQRTPS_XMMdq_XMMdq =8691, +
+  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 =8692, +
+  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 =8693, +
+  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 =8694, +
+  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 =8695, +
+  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC =8696, +
+  XED_IFORM_VSQRTPS_YMMqq_MEMqq =8697, +
+  XED_IFORM_VSQRTPS_YMMqq_YMMqq =8698, +
+  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 =8699, +
+  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8700, +
+  XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq =8701, +
+  XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq =8702, +
+  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8703, +
+  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8704, +
+  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =8705, +
+  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8706, +
+  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8707, +
+  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =8708, +
+  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd =8709, +
+  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd =8710, +
+  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8711, +
+  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8712, +
+  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =8713, +
+  XED_IFORM_VSTMXCSR_MEMd =8714, +
+  XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =8715, +
+  XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =8716, +
+  XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =8717, +
+  XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =8718, +
+  XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =8719, +
+  XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =8720, +
+  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq =8721, +
+  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq =8722, +
+  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8723, +
+  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8724, +
+  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8725, +
+  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8726, +
+  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC =8727, +
+  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq =8728, +
+  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq =8729, +
+  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8730, +
+  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8731, +
+  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8732, +
+  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8733, +
+  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =8734, +
+  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =8735, +
+  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC =8736, +
+  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =8737, +
+  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =8738, +
+  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq =8739, +
+  XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq =8740, +
+  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8741, +
+  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8742, +
+  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8743, +
+  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8744, +
+  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC =8745, +
+  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq =8746, +
+  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq =8747, +
+  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8748, +
+  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8749, +
+  XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq =8750, +
+  XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq =8751, +
+  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8752, +
+  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8753, +
+  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC =8754, +
+  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8755, +
+  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8756, +
+  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC =8757, +
+  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd =8758, +
+  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd =8759, +
+  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8760, +
+  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8761, +
+  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC =8762, +
+  XED_IFORM_VTESTPD_XMMdq_MEMdq =8763, +
+  XED_IFORM_VTESTPD_XMMdq_XMMdq =8764, +
+  XED_IFORM_VTESTPD_YMMqq_MEMqq =8765, +
+  XED_IFORM_VTESTPD_YMMqq_YMMqq =8766, +
+  XED_IFORM_VTESTPS_XMMdq_MEMdq =8767, +
+  XED_IFORM_VTESTPS_XMMdq_XMMdq =8768, +
+  XED_IFORM_VTESTPS_YMMqq_MEMqq =8769, +
+  XED_IFORM_VTESTPS_YMMqq_YMMqq =8770, +
+  XED_IFORM_VUCOMISD_XMMdq_MEMq =8771, +
+  XED_IFORM_VUCOMISD_XMMdq_XMMq =8772, +
+  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 =8773, +
+  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 =8774, +
+  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC =8775, +
+  XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512 =8776, +
+  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512 =8777, +
+  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC =8778, +
+  XED_IFORM_VUCOMISS_XMMdq_MEMd =8779, +
+  XED_IFORM_VUCOMISS_XMMdq_XMMd =8780, +
+  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 =8781, +
+  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 =8782, +
+  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC =8783, +
+  XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512 =8784, +
+  XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512 =8785, +
+  XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512 =8786, +
+  XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512 =8787, +
+  XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512 =8788, +
+  XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512 =8789, +
+  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq =8790, +
+  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq =8791, +
+  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8792, +
+  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8793, +
+  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8794, +
+  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8795, +
+  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq =8796, +
+  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq =8797, +
+  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8798, +
+  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8799, +
+  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq =8800, +
+  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq =8801, +
+  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8802, +
+  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8803, +
+  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8804, +
+  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8805, +
+  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq =8806, +
+  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq =8807, +
+  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8808, +
+  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8809, +
+  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq =8810, +
+  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq =8811, +
+  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8812, +
+  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8813, +
+  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8814, +
+  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8815, +
+  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq =8816, +
+  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq =8817, +
+  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8818, +
+  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8819, +
+  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq =8820, +
+  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq =8821, +
+  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8822, +
+  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8823, +
+  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8824, +
+  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8825, +
+  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq =8826, +
+  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq =8827, +
+  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8828, +
+  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8829, +
+  XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq =8830, +
+  XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq =8831, +
+  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8832, +
+  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8833, +
+  XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq =8834, +
+  XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq =8835, +
+  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8836, +
+  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8837, +
+  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8838, +
+  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8839, +
+  XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq =8840, +
+  XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq =8841, +
+  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8842, +
+  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8843, +
+  XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq =8844, +
+  XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq =8845, +
+  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8846, +
+  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8847, +
+  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8848, +
+  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8849, +
+  XED_IFORM_VZEROALL =8850, +
+  XED_IFORM_VZEROUPPER =8851, +
+  XED_IFORM_WBINVD =8852, +
+  XED_IFORM_WBNOINVD =8853, +
+  XED_IFORM_WRFSBASE_GPRy =8854, +
+  XED_IFORM_WRGSBASE_GPRy =8855, +
+  XED_IFORM_WRMSR =8856, +
+  XED_IFORM_WRMSRLIST =8857, +
+  XED_IFORM_WRMSRNS =8858, +
+  XED_IFORM_WRMSRNS_IMM32_GPR64u64 =8859, +
+  XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX =8860, +
+  XED_IFORM_WRPKRU =8861, +
+  XED_IFORM_WRSSD_MEMu32_GPR32u32 =8862, +
+  XED_IFORM_WRSSD_MEMu32_GPR32u32_APX =8863, +
+  XED_IFORM_WRSSQ_MEMu64_GPR64u64 =8864, +
+  XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX =8865, +
+  XED_IFORM_WRUSSD_MEMu32_GPR32u32 =8866, +
+  XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX =8867, +
+  XED_IFORM_WRUSSQ_MEMu64_GPR64u64 =8868, +
+  XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX =8869, +
+  XED_IFORM_XABORT_IMMb =8870, +
+  XED_IFORM_XADD_GPR8_GPR8 =8871, +
+  XED_IFORM_XADD_GPRv_GPRv =8872, +
+  XED_IFORM_XADD_MEMb_GPR8 =8873, +
+  XED_IFORM_XADD_MEMv_GPRv =8874, +
+  XED_IFORM_XADD_LOCK_MEMb_GPR8 =8875, +
+  XED_IFORM_XADD_LOCK_MEMv_GPRv =8876, +
+  XED_IFORM_XBEGIN_RELBRz =8877, +
+  XED_IFORM_XCHG_GPR8_GPR8 =8878, +
+  XED_IFORM_XCHG_GPRv_GPRv =8879, +
+  XED_IFORM_XCHG_GPRv_OrAX =8880, +
+  XED_IFORM_XCHG_MEMb_GPR8 =8881, +
+  XED_IFORM_XCHG_MEMv_GPRv =8882, +
+  XED_IFORM_XEND =8883, +
+  XED_IFORM_XGETBV =8884, +
+  XED_IFORM_XLAT =8885, +
+  XED_IFORM_XOR_AL_IMMb =8886, +
+  XED_IFORM_XOR_GPR8_GPR8_30 =8887, +
+  XED_IFORM_XOR_GPR8_GPR8_32 =8888, +
+  XED_IFORM_XOR_GPR8_IMMb_80r6 =8889, +
+  XED_IFORM_XOR_GPR8_IMMb_82r6 =8890, +
+  XED_IFORM_XOR_GPR8_MEMb =8891, +
+  XED_IFORM_XOR_GPR8i8_GPR8i8_APX =8892, +
+  XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX =8893, +
+  XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX =8894, +
+  XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX =8895, +
+  XED_IFORM_XOR_GPR8i8_IMM8_APX =8896, +
+  XED_IFORM_XOR_GPR8i8_MEMi8_APX =8897, +
+  XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX =8898, +
+  XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX =8899, +
+  XED_IFORM_XOR_GPRv_GPRv_31 =8900, +
+  XED_IFORM_XOR_GPRv_GPRv_33 =8901, +
+  XED_IFORM_XOR_GPRv_GPRv_APX =8902, +
+  XED_IFORM_XOR_GPRv_GPRv_GPRv_APX =8903, +
+  XED_IFORM_XOR_GPRv_GPRv_IMM8_APX =8904, +
+  XED_IFORM_XOR_GPRv_GPRv_IMMz_APX =8905, +
+  XED_IFORM_XOR_GPRv_GPRv_MEMv_APX =8906, +
+  XED_IFORM_XOR_GPRv_IMM8_APX =8907, +
+  XED_IFORM_XOR_GPRv_IMMb =8908, +
+  XED_IFORM_XOR_GPRv_IMMz =8909, +
+  XED_IFORM_XOR_GPRv_IMMz_APX =8910, +
+  XED_IFORM_XOR_GPRv_MEMv =8911, +
+  XED_IFORM_XOR_GPRv_MEMv_APX =8912, +
+  XED_IFORM_XOR_GPRv_MEMv_GPRv_APX =8913, +
+  XED_IFORM_XOR_GPRv_MEMv_IMM8_APX =8914, +
+  XED_IFORM_XOR_GPRv_MEMv_IMMz_APX =8915, +
+  XED_IFORM_XOR_MEMb_GPR8 =8916, +
+  XED_IFORM_XOR_MEMb_IMMb_80r6 =8917, +
+  XED_IFORM_XOR_MEMb_IMMb_82r6 =8918, +
+  XED_IFORM_XOR_MEMi8_GPR8i8_APX =8919, +
+  XED_IFORM_XOR_MEMi8_IMM8_APX =8920, +
+  XED_IFORM_XOR_MEMv_GPRv =8921, +
+  XED_IFORM_XOR_MEMv_GPRv_APX =8922, +
+  XED_IFORM_XOR_MEMv_IMM8_APX =8923, +
+  XED_IFORM_XOR_MEMv_IMMb =8924, +
+  XED_IFORM_XOR_MEMv_IMMz =8925, +
+  XED_IFORM_XOR_MEMv_IMMz_APX =8926, +
+  XED_IFORM_XOR_OrAX_IMMz =8927, +
+  XED_IFORM_XORPD_XMMxuq_MEMxuq =8928, +
+  XED_IFORM_XORPD_XMMxuq_XMMxuq =8929, +
+  XED_IFORM_XORPS_XMMxud_MEMxud =8930, +
+  XED_IFORM_XORPS_XMMxud_XMMxud =8931, +
+  XED_IFORM_XOR_LOCK_MEMb_GPR8 =8932, +
+  XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 =8933, +
+  XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 =8934, +
+  XED_IFORM_XOR_LOCK_MEMv_GPRv =8935, +
+  XED_IFORM_XOR_LOCK_MEMv_IMMb =8936, +
+  XED_IFORM_XOR_LOCK_MEMv_IMMz =8937, +
+  XED_IFORM_XRESLDTRK =8938, +
+  XED_IFORM_XRSTOR_MEMmxsave =8939, +
+  XED_IFORM_XRSTOR64_MEMmxsave =8940, +
+  XED_IFORM_XRSTORS_MEMmxsave =8941, +
+  XED_IFORM_XRSTORS64_MEMmxsave =8942, +
+  XED_IFORM_XSAVE_MEMmxsave =8943, +
+  XED_IFORM_XSAVE64_MEMmxsave =8944, +
+  XED_IFORM_XSAVEC_MEMmxsave =8945, +
+  XED_IFORM_XSAVEC64_MEMmxsave =8946, +
+  XED_IFORM_XSAVEOPT_MEMmxsave =8947, +
+  XED_IFORM_XSAVEOPT64_MEMmxsave =8948, +
+  XED_IFORM_XSAVES_MEMmxsave =8949, +
+  XED_IFORM_XSAVES64_MEMmxsave =8950, +
+  XED_IFORM_XSETBV =8951, +
+  XED_IFORM_XSTORE =8952, +
+  XED_IFORM_XSUSLDTRK =8953, +
+  XED_IFORM_XTEST =8954,
  XED_IFORM_LAST
@@ -55700,6 +59176,34 @@

+ + + +

◆ XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_MOVRS_GPRv_MEMv_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_MOVRS_GPRv_MEMv_DEFINED   1
+
+
@@ -57030,20 +60534,6 @@

- - - -

◆ XED_IFORM_NOP_MEMv_0F18r4_DEFINED

- -
-
- - - - -
#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED   1
-
-
@@ -63190,6 +66680,20 @@

+ + + +

◆ XED_IFORM_PREFETCHRST2_MEMu8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_PREFETCHRST2_MEMu8_DEFINED   1
+
+
@@ -66746,6 +70250,34 @@

+ + + +

◆ XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED   1
+
+
@@ -75146,6 +78678,118 @@

+ + + +

◆ XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED   1
+
+
@@ -75174,6 +78818,174 @@

+ + + +

◆ XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED   1
+
+
@@ -75202,6 +79014,34 @@

+ + + +

◆ XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED   1
+
+
@@ -75272,6 +79112,34 @@

+ + + +

◆ XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED   1
+
+
@@ -75510,6 +79378,34 @@

+ + + +

◆ XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED   1
+
+
@@ -75538,6 +79434,34 @@

+ + + +

◆ XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED   1
+
+
@@ -75608,6 +79532,20 @@

+ + + +

◆ XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1
+
+
@@ -75622,6 +79560,90 @@

+ + + +

◆ XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED   1
+
+
@@ -76196,6 +80218,90 @@

+ + + +

◆ XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -76280,6 +80386,20 @@

+ + + +

◆ XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -76392,6 +80512,20 @@

+ + + +

◆ XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -76504,6 +80638,20 @@

+ + + +

◆ XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -76616,6 +80764,20 @@

+ + + +

◆ XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -76644,6 +80806,20 @@

+ + + +

◆ XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -76700,6 +80876,20 @@

+ + + +

◆ XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79164,6 +83354,90 @@

+ + + +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+
@@ -79220,6 +83494,20 @@

+ + + +

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -79360,6 +83648,20 @@

+ + + +

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -79444,6 +83746,20 @@

+ + + +

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -79556,6 +83872,20 @@

+ + + +

◆ XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79612,6 +83942,20 @@

+ + + +

◆ XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79640,6 +83984,20 @@

+ + + +

◆ XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79696,6 +84054,20 @@

+ + + +

◆ XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79752,6 +84124,20 @@

+ + + +

◆ XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79808,6 +84194,20 @@

+ + + +

◆ XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -79976,6 +84376,538 @@

+ + + +

◆ XED_IFORM_VCOMSBF16_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMSBF16_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMSBF16_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMSBF16_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
+
+
@@ -80060,6 +84992,20 @@

+ + + +

◆ XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC_DEFINED   1
+
+
@@ -80172,6 +85118,20 @@

+ + + +

◆ XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED   1
+
+
@@ -80284,6 +85244,20 @@

+ + + +

◆ XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC_DEFINED   1
+
+
@@ -80342,4928 +85316,8148 @@

-

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED   1#define XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED

- +
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED

- +
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED

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#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED

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#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED

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#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED

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#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED

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#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED

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#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED

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#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED

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#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED

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#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED

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#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED

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◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED   1#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED

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◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED   1#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED   1#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED

+ +

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED   1#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED   1#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED   1#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED

- +
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED

- +
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED

- +
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED   1
- -

◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED   1
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◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED

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◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED   1#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED

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◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED   1#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED

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◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED   1#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED

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◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED   1#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED

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#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED

+ +
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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED

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#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
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◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

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#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1
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+ +
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◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
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+
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◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
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+
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◆ XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED

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#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED   1
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◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
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+
+

◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

- + + +
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
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+
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◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
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+
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◆ XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED   1
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◆ XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
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◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED   1
+
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◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED   1
+
+ +
+
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◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC_DEFINED

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+ + + + +
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1
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+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1
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+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1
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+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED   1
+
+ +
+
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◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC_DEFINED

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#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED

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+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED

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#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED

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+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC_DEFINED

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+
+ + +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC_DEFINED   1
- -

◆ XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED

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+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED

- +
#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

- +
#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

- +
#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED   1#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED   1#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED   1#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED   1#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED   1#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED   1#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

+ +

◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

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◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED   1
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◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED   1
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◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED

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#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

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◆ XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1
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◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED

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#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

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#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
- -

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

+ +

◆ XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

- +
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
@@ -85324,6 +93518,20 @@

+

+
+ +

◆ XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -85352,6 +93560,90 @@

+ + + +

◆ XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1
+
+
@@ -85408,6 +93700,20 @@

+ + + +

◆ XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85436,6 +93742,20 @@

+ + + +

◆ XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85464,6 +93784,62 @@

+ + + +

◆ XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED   1
+
+
@@ -85492,6 +93868,20 @@

+ + + +

◆ XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85520,6 +93910,76 @@

+ + + +

◆ XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED   1
+
+
@@ -85548,6 +94008,20 @@

+ + + +

◆ XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85576,6 +94050,20 @@

+ + + +

◆ XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85604,6 +94092,20 @@

+ + + +

◆ XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85632,6 +94134,20 @@

+ + + +

◆ XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85688,6 +94204,20 @@

+ + + +

◆ XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85716,6 +94246,20 @@

+ + + +

◆ XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85744,6 +94288,62 @@

+ + + +

◆ XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED   1
+
+
@@ -85772,6 +94372,20 @@

+ + + +

◆ XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -85800,6 +94414,76 @@

+ + + +

◆ XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED   1
+
+
@@ -85856,6 +94540,20 @@

+ + + +

◆ XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC_DEFINED   1
+
+
@@ -85940,6 +94638,20 @@

+ + + +

◆ XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED   1
+
+
@@ -86024,6 +94736,20 @@

+ + + +

◆ XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC_DEFINED   1
+
+
@@ -86108,6 +94834,20 @@

+ + + +

◆ XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1
+
+
@@ -86206,6 +94946,20 @@

+ + + +

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC_DEFINED   1
+
+
@@ -86276,6 +95030,20 @@

+ + + +

◆ XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256_DEFINED   1
+
+
@@ -86318,6 +95086,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86332,6 +95114,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86374,6 +95170,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86388,6 +95198,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86430,6 +95254,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86444,6 +95282,20 @@

+ + + +

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -86528,6 +95380,20 @@

+ + + +

◆ XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC_DEFINED   1
+
+
@@ -86612,6 +95478,20 @@

+ + + +

◆ XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC_DEFINED   1
+
+
@@ -86724,6 +95604,90 @@

+ + + +

◆ XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -86808,6 +95772,20 @@

+ + + +

◆ XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -86920,6 +95898,20 @@

+ + + +

◆ XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -87032,6 +96024,20 @@

+ + + +

◆ XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -87144,6 +96150,20 @@

+ + + +

◆ XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -87172,6 +96192,20 @@

+ + + +

◆ XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -87228,6 +96262,20 @@

+ + + +

◆ XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -87340,6 +96388,90 @@

+ + + +

◆ XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
+
+
@@ -88180,6 +97312,20 @@

+ + + +

◆ XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1
+
+
@@ -88236,6 +97382,20 @@

+ + + +

◆ XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -88292,6 +97452,20 @@

+ + + +

◆ XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1
+
+
@@ -88348,6 +97522,20 @@

+ + + +

◆ XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -88404,6 +97592,20 @@

+ + + +

◆ XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -88488,6 +97690,20 @@

+ + + +

◆ XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -88544,6 +97760,20 @@

+ + + +

◆ XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -88572,6 +97802,104 @@

+ + + +

◆ XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -88656,6 +97984,20 @@

+ + + +

◆ XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -88768,6 +98110,20 @@

+ + + +

◆ XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -88880,6 +98236,20 @@

+ + + +

◆ XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -88992,6 +98362,20 @@

+ + + +

◆ XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -89020,6 +98404,20 @@

+ + + +

◆ XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -89076,6 +98474,104 @@

+ + + +

◆ XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -89160,6 +98656,20 @@

+ + + +

◆ XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -89272,6 +98782,20 @@

+ + + +

◆ XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -89384,6 +98908,20 @@

+ + + +

◆ XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -89496,6 +99034,20 @@

+ + + +

◆ XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -89524,6 +99076,20 @@

+ + + +

◆ XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -89580,6 +99146,104 @@

+ + + +

◆ XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -89664,6 +99328,20 @@

+ + + +

◆ XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -89776,6 +99454,20 @@

+ + + +

◆ XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -89888,6 +99580,20 @@

+ + + +

◆ XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -90000,6 +99706,20 @@

+ + + +

◆ XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -90028,6 +99748,20 @@

+ + + +

◆ XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -90084,6 +99818,20 @@

+ + + +

◆ XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -90140,6 +99888,20 @@

+ + + +

◆ XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1
+
+
@@ -90196,6 +99958,20 @@

+ + + +

◆ XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -90532,6 +100308,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -90644,6 +100434,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -90756,6 +100560,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -90896,6 +100714,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -91008,6 +100840,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -91120,6 +100966,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -91260,6 +101120,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -91372,6 +101246,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -91484,6 +101372,20 @@

+ + + +

◆ XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -91708,6 +101610,90 @@

+ + + +

◆ XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -91792,6 +101778,20 @@

+ + + +

◆ XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -91904,6 +101904,20 @@

+ + + +

◆ XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -92016,6 +102030,20 @@

+ + + +

◆ XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -92128,6 +102156,20 @@

+ + + +

◆ XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -92156,6 +102198,20 @@

+ + + +

◆ XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -92212,6 +102268,104 @@

+ + + +

◆ XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -92296,6 +102450,20 @@

+ + + +

◆ XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -92408,6 +102576,20 @@

+ + + +

◆ XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -92520,6 +102702,20 @@

+ + + +

◆ XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -92632,6 +102828,20 @@

+ + + +

◆ XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -92660,6 +102870,20 @@

+ + + +

◆ XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -92716,6 +102940,104 @@

+ + + +

◆ XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -92800,6 +103122,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -92912,6 +103248,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -93024,6 +103374,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -93136,6 +103500,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -93164,6 +103542,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -93220,6 +103612,20 @@

+ + + +

◆ XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -93304,6 +103710,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -93416,6 +103836,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -93528,6 +103962,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -93668,6 +104116,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -93780,6 +104242,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -93892,6 +104368,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -94032,6 +104522,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -94144,6 +104648,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -94256,6 +104774,20 @@

+ + + +

◆ XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -94788,6 +105320,20 @@

+ + + +

◆ XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC_DEFINED   1
+
+
@@ -94844,6 +105390,104 @@

+ + + +

◆ XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -94928,6 +105572,20 @@

+ + + +

◆ XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -95040,6 +105698,20 @@

+ + + +

◆ XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -95152,6 +105824,20 @@

+ + + +

◆ XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -95264,6 +105950,20 @@

+ + + +

◆ XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -95292,6 +105992,20 @@

+ + + +

◆ XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -95348,6 +106062,104 @@

+ + + +

◆ XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -95432,6 +106244,20 @@

+ + + +

◆ XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -95544,6 +106370,20 @@

+ + + +

◆ XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -95656,6 +106496,20 @@

+ + + +

◆ XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -95768,6 +106622,20 @@

+ + + +

◆ XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -95796,6 +106664,20 @@

+ + + +

◆ XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -95852,6 +106734,104 @@

+ + + +

◆ XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -95936,6 +106916,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -96048,6 +107042,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -96160,6 +107168,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -96272,6 +107294,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -96300,6 +107336,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -96356,6 +107406,20 @@

+ + + +

◆ XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -96608,6 +107672,90 @@

+ + + +

◆ XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -96692,6 +107840,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -96804,6 +107966,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -96916,6 +108092,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -97028,6 +108218,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -97056,6 +108260,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -97112,6 +108330,104 @@

+ + + +

◆ XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -97196,6 +108512,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -97308,6 +108638,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -97420,6 +108764,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -97532,6 +108890,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -97560,6 +108932,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -97616,6 +109002,104 @@

+ + + +

◆ XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
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+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -97700,6 +109184,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -97812,6 +109310,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -97924,6 +109436,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -98036,6 +109562,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -98064,6 +109604,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -98120,6 +109674,20 @@

+ + + +

◆ XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -98372,6 +109940,90 @@

+ + + +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+
@@ -99268,6 +110920,90 @@

+ + + +

◆ XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -99324,6 +111060,20 @@

+ + + +

◆ XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -99408,6 +111158,20 @@

+ + + +

◆ XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -99492,6 +111256,20 @@

+ + + +

◆ XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -99548,6 +111326,20 @@

+ + + +

◆ XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -99576,6 +111368,20 @@

+ + + +

◆ XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -99604,6 +111410,104 @@

+ + + +

◆ XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+
@@ -99660,6 +111564,20 @@

+ + + +

◆ XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -99744,6 +111662,20 @@

+ + + +

◆ XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -99828,6 +111760,20 @@

+ + + +

◆ XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -99884,6 +111830,20 @@

+ + + +

◆ XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -99912,6 +111872,20 @@

+ + + +

◆ XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -99940,6 +111914,20 @@

+ + + +

◆ XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -101200,6 +113188,90 @@

+ + + +

◆ XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -101284,6 +113356,20 @@

+ + + +

◆ XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -101396,6 +113482,20 @@

+ + + +

◆ XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -101508,6 +113608,20 @@

+ + + +

◆ XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -101620,6 +113734,20 @@

+ + + +

◆ XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -101648,6 +113776,20 @@

+ + + +

◆ XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -101704,6 +113846,20 @@

+ + + +

◆ XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -101746,6 +113902,510 @@

+ + + +

◆ XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -101830,6 +114490,20 @@

+ + + +

◆ XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -101942,6 +114616,20 @@

+ + + +

◆ XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -102054,6 +114742,20 @@

+ + + +

◆ XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -102166,6 +114868,20 @@

+ + + +

◆ XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -102194,6 +114910,20 @@

+ + + +

◆ XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -102250,6 +114980,20 @@

+ + + +

◆ XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -102824,6 +115568,20 @@

+ + + +

◆ XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED   1
+
+
@@ -102880,6 +115638,34 @@

+ + + +

◆ XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED   1
+
+
@@ -104798,6 +117584,174 @@

+ + + +

◆ XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
+
+
@@ -105820,6 +118774,20 @@

+ + + +

◆ XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED   1
+
+
@@ -105848,6 +118816,34 @@

+ + + +

◆ XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED   1
+
+
@@ -105876,6 +118872,34 @@

+ + + +

◆ XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
+
+
@@ -105904,6 +118928,62 @@

+ + + +

◆ XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
+
+
@@ -106030,6 +119110,90 @@

+ + + +

◆ XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -106114,6 +119278,20 @@

+ + + +

◆ XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -106226,6 +119404,20 @@

+ + + +

◆ XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -106338,6 +119530,20 @@

+ + + +

◆ XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -106450,6 +119656,20 @@

+ + + +

◆ XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -106478,6 +119698,20 @@

+ + + +

◆ XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -106534,6 +119768,20 @@

+ + + +

◆ XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -114402,6 +127650,34 @@

+ + + +

◆ XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1
+
+
@@ -114430,6 +127706,34 @@

+ + + +

◆ XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1
+
+
@@ -114458,6 +127762,62 @@

+ + + +

◆ XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1
+
+
@@ -114486,6 +127846,34 @@

+ + + +

◆ XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1
+
+
@@ -114514,6 +127902,62 @@

+ + + +

◆ XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1
+
+
@@ -114542,6 +127986,34 @@

+ + + +

◆ XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1
+
+
@@ -114570,6 +128042,62 @@

+ + + +

◆ XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1
+
+
@@ -114598,6 +128126,34 @@

+ + + +

◆ XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1
+
+
@@ -114626,6 +128182,34 @@

+ + + +

◆ XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1
+
+
@@ -114906,6 +128490,34 @@

+ + + +

◆ XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1
+
+
@@ -114934,6 +128546,34 @@

+ + + +

◆ XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1
+
+
@@ -114962,6 +128602,62 @@

+ + + +

◆ XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1
+
+
@@ -114990,6 +128686,34 @@

+ + + +

◆ XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1
+
+
@@ -115018,6 +128742,34 @@

+ + + +

◆ XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1
+
+
@@ -115298,6 +129050,34 @@

+ + + +

◆ XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1
+
+
@@ -115326,6 +129106,34 @@

+ + + +

◆ XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1
+
+
@@ -115354,6 +129162,62 @@

+ + + +

◆ XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1
+
+
@@ -115382,6 +129246,34 @@

+ + + +

◆ XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1
+
+
@@ -115410,6 +129302,62 @@

+ + + +

◆ XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1
+
+
@@ -115438,6 +129386,34 @@

+ + + +

◆ XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1
+
+
@@ -115466,6 +129442,62 @@

+ + + +

◆ XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1
+
+
@@ -115494,6 +129526,34 @@

+ + + +

◆ XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1
+
+
@@ -115522,6 +129582,62 @@

+ + + +

◆ XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1
+
+
@@ -115550,6 +129666,34 @@

+ + + +

◆ XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1
+
+
@@ -115578,6 +129722,62 @@

+ + + +

◆ XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1
+
+
@@ -115606,6 +129806,34 @@

+ + + +

◆ XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1
+
+
@@ -115634,6 +129862,34 @@

+ + + +

◆ XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1
+
+
@@ -138692,6 +152948,20 @@

+ + + +

◆ XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -138776,6 +153046,20 @@

+ + + +

◆ XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -138832,6 +153116,20 @@

+ + + +

◆ XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -138860,6 +153158,20 @@

+ + + +

◆ XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -139196,6 +153508,90 @@

+ + + +

◆ XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -139392,6 +153788,90 @@

+ + + +

◆ XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+
@@ -139448,6 +153928,20 @@

+ + + +

◆ XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -139532,6 +154026,20 @@

+ + + +

◆ XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -139616,6 +154124,20 @@

+ + + +

◆ XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -139672,6 +154194,20 @@

+ + + +

◆ XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -139700,6 +154236,20 @@

+ + + +

◆ XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -139728,6 +154278,104 @@

+ + + +

◆ XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
+
+
@@ -139784,6 +154432,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -139868,6 +154530,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -139952,6 +154628,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC_DEFINED   1
+
+
@@ -140008,6 +154698,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -140036,6 +154740,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -140064,6 +154782,20 @@

+ + + +

◆ XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -140568,6 +155300,90 @@

+ + + +

◆ XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -140764,6 +155580,90 @@

+ + + +

◆ XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -140820,6 +155720,20 @@

+ + + +

◆ XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -140904,6 +155818,20 @@

+ + + +

◆ XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -140988,6 +155916,20 @@

+ + + +

◆ XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -141044,6 +155986,20 @@

+ + + +

◆ XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -141072,6 +156028,20 @@

+ + + +

◆ XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -141100,6 +156070,20 @@

+ + + +

◆ XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -142010,6 +156994,20 @@

+ + + +

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1
+
+
@@ -142024,6 +157022,20 @@

+ + + +

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1
+
+
@@ -142038,6 +157050,20 @@

+ + + +

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1
+
+
@@ -142052,6 +157078,20 @@

+ + + +

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1
+
+
@@ -142066,6 +157106,48 @@

+ + + +

◆ XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1
+
+
@@ -142080,6 +157162,20 @@

+ + + +

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1
+
+
@@ -142094,6 +157190,20 @@

+ + + +

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1
+
+
@@ -142108,6 +157218,20 @@

+ + + +

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1
+
+
@@ -142122,6 +157246,118 @@

+ + + +

◆ XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -142206,6 +157442,20 @@

+ + + +

◆ XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -142318,6 +157568,20 @@

+ + + +

◆ XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -142430,6 +157694,20 @@

+ + + +

◆ XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -142542,6 +157820,20 @@

+ + + +

◆ XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -142570,6 +157862,20 @@

+ + + +

◆ XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -142626,6 +157932,20 @@

+ + + +

◆ XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -142640,6 +157960,90 @@

+ + + +

◆ XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
+
+
@@ -142724,6 +158128,20 @@

+ + + +

◆ XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC_DEFINED   1
+
+
@@ -142836,6 +158254,20 @@

+ + + +

◆ XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC_DEFINED   1
+
+
@@ -142948,6 +158380,20 @@

+ + + +

◆ XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC_DEFINED   1
+
+
@@ -143060,6 +158506,20 @@

+ + + +

◆ XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -143088,6 +158548,20 @@

+ + + +

◆ XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -143144,6 +158618,20 @@

+ + + +

◆ XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -143312,6 +158800,20 @@

+ + + +

◆ XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -143340,6 +158842,20 @@

+ + + +

◆ XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC_DEFINED   1
+
+
@@ -143396,6 +158912,104 @@

+ + + +

◆ XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1
+
+
@@ -144362,6 +159976,34 @@

+ + + +

◆ XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED

+ +
+
+ + + + +
#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED   1
+
+
@@ -147344,6 +162986,8 @@

XED_IFORM_MOVQ_XMMdq_XMMq_0F7E  XED_IFORM_MOVQ_XMMdq_XMMq_0FD6  XED_IFORM_MOVQ2DQ_XMMdq_MMXq  +XED_IFORM_MOVRS_GPR8i8_MEMi8  +XED_IFORM_MOVRS_GPRv_MEMv  XED_IFORM_MOVSB  XED_IFORM_MOVSD  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd  @@ -147447,7 +163091,6 @@

XED_IFORM_NOP_GPRv_GPRv_0F1E  XED_IFORM_NOP_GPRv_MEM_0F1B  XED_IFORM_NOP_GPRv_MEMv_0F1A  -XED_IFORM_NOP_MEMv_0F18r4  XED_IFORM_NOP_MEMv_0F18r5  XED_IFORM_NOP_MEMv_0F1F  XED_IFORM_NOP_MEMv_GPRv_0F19  @@ -147882,6 +163525,7 @@

XED_IFORM_PREFETCHIT0_MEMu8  XED_IFORM_PREFETCHIT1_MEMu8  XED_IFORM_PREFETCHNTA_MEMmprefetch  +XED_IFORM_PREFETCHRST2_MEMu8  XED_IFORM_PREFETCHT0_MEMmprefetch  XED_IFORM_PREFETCHT1_MEMmprefetch  XED_IFORM_PREFETCHT2_MEMmprefetch  @@ -148141,6 +163785,8 @@

XED_IFORM_RDFSBASE_GPRy  XED_IFORM_RDGSBASE_GPRy  XED_IFORM_RDMSR  +XED_IFORM_RDMSR_GPR64u64_IMM32  +XED_IFORM_RDMSR_GPR64u64_IMM32_APX  XED_IFORM_RDMSRLIST  XED_IFORM_RDPID_GPR32u32  XED_IFORM_RDPID_GPR64u64  @@ -148741,15 +164387,39 @@

XED_IFORM_T1MSKC_GPR32d_MEMd  XED_IFORM_T1MSKC_GPRyy_GPRyy  XED_IFORM_T1MSKC_GPRyy_MEMy  +XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16  +XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16  XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16  XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16  +XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16  +XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16  +XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32  +XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8  +XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32  +XED_IFORM_TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8  +XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32  +XED_IFORM_TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8  +XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32  +XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8  +XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32  +XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8  XED_IFORM_TDCALL  XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16  +XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8  +XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8  XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8  XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8  XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8  XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8  XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16  +XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8  +XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8  XED_IFORM_TEST_AL_IMMb  XED_IFORM_TEST_GPR8_GPR8  XED_IFORM_TEST_GPR8_IMMb_F6r0  @@ -148767,14 +164437,25 @@

XED_IFORM_TESTUI  XED_IFORM_TILELOADD_TMMu32_MEMu32  XED_IFORM_TILELOADD_TMMu32_MEMu32_APX  +XED_IFORM_TILELOADDRS_TMMu32_MEMu32  +XED_IFORM_TILELOADDRST1_TMMu32_MEMu32  XED_IFORM_TILELOADDT1_TMMu32_MEMu32  XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX  +XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32  +XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8  XED_IFORM_TILERELEASE  XED_IFORM_TILESTORED_MEMu32_TMMu32  XED_IFORM_TILESTORED_MEMu32_TMMu32_APX  XED_IFORM_TILEZERO_TMMu32  XED_IFORM_TLBSYNC  +XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32  XED_IFORM_TPAUSE_GPR32u32  +XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16  +XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16  +XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16  +XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16  +XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32  +XED_IFORM_TTRANSPOSED_TMMu32_TMMu32  XED_IFORM_TZCNT_GPRv_GPRv  XED_IFORM_TZCNT_GPRv_GPRv_APX  XED_IFORM_TZCNT_GPRv_MEMv  @@ -148816,12 +164497,19 @@

XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  +XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VADDNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VADDNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VADDNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -148830,6 +164518,7 @@

XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq  @@ -148838,6 +164527,7 @@

XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -148846,12 +164536,15 @@

XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq  @@ -149028,10 +164721,17 @@

XED_IFORM_VBROADCASTSS_YMMqq_XMMdq  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VCMPPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512  +XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb  @@ -149042,12 +164742,14 @@

XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512  +XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_VL256RC  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512  +XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb  @@ -149056,24 +164758,30 @@

XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512  +XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCOMISD_XMMq_MEMq  XED_IFORM_VCOMISD_XMMq_XMMq  XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512  +XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCOMISS_XMMd_MEMd  XED_IFORM_VCOMISS_XMMd_XMMd  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512  +XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512  @@ -149086,12 +164794,51 @@

XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCOMSBF16_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VCOMSBF16_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512  +XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512  +XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512  +XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512  +XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512  +XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512  +XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512  +XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128  +XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512  +XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256  +XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512  +XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512  +XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512  +XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128  +XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512  +XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256  +XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512  +XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512  +XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128  +XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256  +XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512  +XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128  +XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256  +XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512  +XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512  +XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512  +XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_VL256RC  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512  @@ -149100,6 +164847,7 @@

XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512  +XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_VL256RC  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq  @@ -149108,16 +164856,59 @@

XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512  +XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_VL256RC  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512  +XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512  +XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512  +XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512  +XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512  +XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512  +XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512  +XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512  +XED_IFORM_VCVTNE2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512  +XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16  XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16  XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16  @@ -149126,6 +164917,30 @@

XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16  XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16  XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16  +XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128  +XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256  +XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTNEPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512  +XED_IFORM_VCVTNEPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512  +XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128  +XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256  +XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTNEPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512  +XED_IFORM_VCVTNEPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128  +XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256  +XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512  +XED_IFORM_VCVTNEPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128  +XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256  +XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512  +XED_IFORM_VCVTNEPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512  @@ -149144,6 +164959,7 @@

XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256  +XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128  @@ -149151,6 +164967,7 @@

XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq  @@ -149160,36 +164977,54 @@

XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256  +XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256RC_VL256  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256  +XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2PS_XMMdq_MEMq  @@ -149198,6 +165033,7 @@

XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512  @@ -149206,36 +165042,42 @@

XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq  @@ -149244,16 +165086,30 @@

XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512  XED_IFORM_VCVTPS2PD_XMMdq_MEMq  XED_IFORM_VCVTPS2PD_XMMdq_XMMq  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512  @@ -149266,36 +165122,42 @@

XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512  +XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128  @@ -149303,53 +165165,71 @@

XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512  +XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256  +XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSD2SI_GPR32d_MEMq  XED_IFORM_VCVTSD2SI_GPR32d_XMMq  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512  +XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512  +XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSD2SI_GPR64q_MEMq  XED_IFORM_VCVTSD2SI_GPR64q_XMMq  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512  +XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512  +XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512  +XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512  +XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512  +XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512  +XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512  +XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512  +XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512  +XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512  +XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512  +XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512  +XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d  @@ -149357,27 +165237,47 @@

XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512  +XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512  +XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_SCALAR_RC  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512  +XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTSS2SI_GPR32d_MEMd  XED_IFORM_VCVTSS2SI_GPR32d_XMMd  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512  +XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512  +XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTSS2SI_GPR64q_MEMd  XED_IFORM_VCVTSS2SI_GPR64q_XMMd  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512  +XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512  +XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VCVTTNEBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq  @@ -149386,60 +165286,106 @@

XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256  +XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256RC_VL256  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512  +XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128  +XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256  +XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512  +XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512  +XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256  +XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256RC_VL256  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512  +XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128  +XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256  +XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512  +XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512  +XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512  +XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512  +XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512  +XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq  @@ -149448,82 +165394,154 @@

XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_VL256RC  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_VL256RC  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512  +XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512  +XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512  +XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq  +XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512  +XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512  +XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512  +XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512  +XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512  +XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_SCALAR_RC  +XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512  +XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512  +XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512  +XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512  XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512  +XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512  +XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512  +XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512  +XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512  +XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512  +XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd  +XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512  +XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512  +XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512  +XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512  +XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512  +XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512  +XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512  +XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512  +XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512  +XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_VL256RC  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512  +XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_VL256RC  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512  +XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_VL256RC  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512  +XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_VL256RC  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128  @@ -149531,35 +165549,45 @@

XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512  +XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_VL256RC  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256  +XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256RC_VL256  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512  +XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512  +XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512  +XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512  +XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512  +XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512  +XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_SCALAR_RC  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512  +XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_VL256RC  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512  +XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_VL256RC  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512  @@ -149568,12 +165596,19 @@

XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512  +XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VDIVNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VDIVNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VDIVNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149582,6 +165617,7 @@

XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq  @@ -149590,6 +165626,7 @@

XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149598,12 +165635,15 @@

XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512  @@ -149612,6 +165652,12 @@

XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb  +XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512  +XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512  +XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512  +XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512  +XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512  +XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb  @@ -149672,40 +165718,55 @@

XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512  +XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  +XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512  +XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  +XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512  +XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512  +XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  +XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149714,6 +165775,7 @@

XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq  @@ -149722,6 +165784,7 @@

XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149730,18 +165793,28 @@

XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149750,6 +165823,7 @@

XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq  @@ -149758,6 +165832,7 @@

XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149766,18 +165841,28 @@

XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149786,6 +165871,7 @@

XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq  @@ -149794,6 +165880,7 @@

XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149802,20 +165889,25 @@

XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512  +XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  +XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq  @@ -149840,6 +165932,7 @@

XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149848,6 +165941,7 @@

XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq  @@ -149856,6 +165950,7 @@

XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149866,6 +165961,7 @@

XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149874,6 +165970,7 @@

XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq  @@ -149882,6 +165979,7 @@

XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149892,6 +165990,7 @@

XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149900,6 +165999,7 @@

XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq  @@ -149908,6 +166008,7 @@

XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149924,12 +166025,19 @@

XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq  +XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149938,6 +166046,7 @@

XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq  @@ -149946,6 +166055,7 @@

XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149954,18 +166064,28 @@

XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -149974,6 +166094,7 @@

XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq  @@ -149982,6 +166103,7 @@

XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -149990,18 +166112,28 @@

XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150010,6 +166142,7 @@

XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq  @@ -150018,6 +166151,7 @@

XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150026,18 +166160,22 @@

XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150046,6 +166184,7 @@

XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq  @@ -150054,6 +166193,7 @@

XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150064,6 +166204,7 @@

XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150072,6 +166213,7 @@

XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq  @@ -150080,6 +166222,7 @@

XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150090,6 +166233,7 @@

XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150098,6 +166242,7 @@

XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq  @@ -150106,6 +166251,7 @@

XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150144,16 +166290,25 @@

XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512  +XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_VL256RC  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512  +XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_SCALAR_RC  +XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150162,6 +166317,7 @@

XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq  @@ -150170,6 +166326,7 @@

XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150178,18 +166335,28 @@

XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150198,6 +166365,7 @@

XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq  @@ -150206,6 +166374,7 @@

XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150214,18 +166383,28 @@

XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMADD231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150234,6 +166413,7 @@

XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq  @@ -150242,6 +166422,7 @@

XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150250,12 +166431,15 @@

XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq  @@ -150274,12 +166458,19 @@

XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd  +XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB132NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB132NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB132NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150288,6 +166479,7 @@

XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq  @@ -150296,6 +166488,7 @@

XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150304,18 +166497,28 @@

XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB213NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB213NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB213NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150324,6 +166527,7 @@

XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq  @@ -150332,6 +166536,7 @@

XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150340,18 +166545,28 @@

XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB231NEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB231NEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VFNMSUB231NEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150360,6 +166575,7 @@

XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq  @@ -150368,6 +166584,7 @@

XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150376,12 +166593,15 @@

XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq  @@ -150400,6 +166620,12 @@

XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512  +XED_IFORM_VFPCLASSPBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512  @@ -150464,54 +166690,78 @@

XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512  +XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VGETEXPPBF16_XMMu16_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VGETEXPPBF16_YMMu16_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VGETEXPPBF16_ZMMu16_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VGETMANTPBF16_XMMu16_MASKmskw_XMMbf16_IMM8_AVX512  +XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VGETMANTPBF16_YMMu16_MASKmskw_YMMbf16_IMM8_AVX512  +XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VGETMANTPBF16_ZMMu16_MASKmskw_ZMMbf16_IMM8_AVX512  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512  +XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512  +XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512  +XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8  @@ -150602,12 +166852,19 @@

XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq  +XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VMAXPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VMAXPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VMAXPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150616,6 +166873,7 @@

XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq  @@ -150624,6 +166882,7 @@

XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150632,21 +166891,61 @@

XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VMCALL  XED_IFORM_VMCLEAR_MEMq  XED_IFORM_VMFUNC  +XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512  +XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512  +XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512  +XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  +XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512  +XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512  +XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512  +XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512  +XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  +XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  +XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  +XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VMINPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VMINPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VMINPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150655,6 +166954,7 @@

XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq  @@ -150663,6 +166963,7 @@

XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150671,12 +166972,15 @@

XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VMLAUNCH  XED_IFORM_VMLOAD_ArAX  XED_IFORM_VMMCALL  @@ -150718,10 +167022,13 @@

XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512  XED_IFORM_VMOVD_MEMd_XMMd  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512  +XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC  XED_IFORM_VMOVD_XMMdq_GPR32d  XED_IFORM_VMOVD_XMMdq_MEMd  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512  +XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC  +XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC  XED_IFORM_VMOVDDUP_XMMdq_MEMq  XED_IFORM_VMOVDDUP_XMMdq_XMMq  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512  @@ -150859,6 +167166,18 @@

XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512  +XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512  +XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512  +XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512  +XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512  +XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512  +XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512  +XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512  +XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512  +XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512  +XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512  +XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512  +XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512  XED_IFORM_VMOVSD_MEMq_XMMq  XED_IFORM_VMOVSD_XMMdq_MEMq  @@ -150932,12 +167251,21 @@

XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512  XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512  XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512  +XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC  XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512  XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512  +XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC  +XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb  +XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512  +XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb  +XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512  +XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512  +XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512  +XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512  XED_IFORM_VMPTRLD_MEMq  XED_IFORM_VMPTRST_MEMq  XED_IFORM_VMREAD_GPR32_GPR32  @@ -150947,12 +167275,19 @@

XED_IFORM_VMRESUME  XED_IFORM_VMRUN_ArAX  XED_IFORM_VMSAVE  +XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VMULNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VMULNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VMULNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -150961,6 +167296,7 @@

XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq  @@ -150969,6 +167305,7 @@

XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -150977,12 +167314,15 @@

XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VMWRITE_GPR32_GPR32  XED_IFORM_VMWRITE_GPR32_MEMd  XED_IFORM_VMWRITE_GPR64_GPR64  @@ -151545,22 +167885,46 @@

XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD  +XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8  +XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8  +XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512  +XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8  +XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8  +XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512  +XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512  +XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8  +XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8  +XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512  +XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8  +XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8  +XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512  +XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32  @@ -151581,14 +167945,26 @@

XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512  +XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8  +XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8  +XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512  +XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8  +XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8  +XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512  +XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32  @@ -151609,30 +167985,66 @@

XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512  +XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16  +XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16  +XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512  +XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16  +XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16  +XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512  +XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512  +XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16  +XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16  +XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512  +XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16  +XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16  +XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512  +XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512  +XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16  +XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16  +XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512  +XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16  +XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16  +XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512  +XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb  @@ -153280,18 +169692,22 @@

XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512  +XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512  +XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512  @@ -153316,6 +169732,12 @@

XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER  +XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRCPPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRCPPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRCPPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512  XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512  @@ -153330,54 +169752,78 @@

XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd  +XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VREDUCENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512  +XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VREDUCENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512  +XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VREDUCENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512  +XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512  +XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512  +XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  +XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VRNDSCALENEPBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512  +XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VRNDSCALENEPBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512  +XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512  +XED_IFORM_VRNDSCALENEPBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512  +XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_VL256RC  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512  +XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_VL256RC  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512  +XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_VL256RC  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512  +XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_SCALAR_RC  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512  +XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_SCALAR_RC  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512  +XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_SCALAR_RC  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb  @@ -153414,6 +169860,12 @@

XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER  +XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRSQRTPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRSQRTPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VRSQRTPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512  @@ -153428,30 +169880,42 @@

XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd  +XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VSCALEFPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VSCALEFPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VSCALEFPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512  @@ -153518,19 +169982,38 @@

XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32  +XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32  +XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32  +XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32  +XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512  +XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512  +XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32  +XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32  +XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32  +XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32  +XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512  +XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512  +XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512  +XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VSQRTNEPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512  +XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VSQRTNEPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512  +XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512  +XED_IFORM_VSQRTNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512  XED_IFORM_VSQRTPD_XMMdq_MEMdq  XED_IFORM_VSQRTPD_XMMdq_XMMdq  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512  +XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_VL256RC  XED_IFORM_VSQRTPD_YMMqq_MEMqq  XED_IFORM_VSQRTPD_YMMqq_YMMqq  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512  @@ -153539,6 +170022,7 @@

XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512  +XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_VL256RC  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512  XED_IFORM_VSQRTPS_XMMdq_MEMdq  @@ -153547,6 +170031,7 @@

XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512  +XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_VL256RC  XED_IFORM_VSQRTPS_YMMqq_MEMqq  XED_IFORM_VSQRTPS_YMMqq_YMMqq  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512  @@ -153555,19 +170040,29 @@

XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VSTMXCSR_MEMd  +XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512  +XED_IFORM_VSUBNEPBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512  +XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512  +XED_IFORM_VSUBNEPBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512  +XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512  +XED_IFORM_VSUBNEPBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512  +XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_VL256RC  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512  @@ -153576,6 +170071,7 @@

XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512  +XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_VL256RC  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq  @@ -153584,6 +170080,7 @@

XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512  +XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_VL256RC  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512  @@ -153592,12 +170089,15 @@

XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512  +XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512  +XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512  +XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_SCALAR_RC  XED_IFORM_VTESTPD_XMMdq_MEMdq  XED_IFORM_VTESTPD_XMMdq_XMMdq  XED_IFORM_VTESTPD_YMMqq_MEMqq  @@ -153610,12 +170110,21 @@

XED_IFORM_VUCOMISD_XMMdq_XMMq  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512  +XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_SCALAR_RC  XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512  +XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_SCALAR_RC  XED_IFORM_VUCOMISS_XMMdq_MEMd  XED_IFORM_VUCOMISS_XMMdq_XMMd  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512  +XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_SCALAR_RC  +XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512  +XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512  +XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512  +XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512  +XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512  +XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512  @@ -153685,6 +170194,8 @@

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"XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21ab7f82d0539e12553d679a871eebeccd8", null ], + [ "XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21a89d3ce6d3f6086a779561a4d3f517525", null ], [ "XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21a3581133a657a4a7d3baa7859c29f4d2f", null ], [ "XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21a4593fcf1b06dc487a57df69e6f14a161", null ], [ "XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21a21568438073d4f914505211f6961fcf8", null ], @@ -16080,6 +17816,8 @@ var xed_iform_enum_8h = [ "XED_IFORM_WRMSR", "xed-iform-enum_8h.html#af48986d6e090a75f7ab50e6d4a182e21a55d2101e332cb64285c4afa138919706", null ], [ "XED_IFORM_WRMSRLIST", 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index a264435..3513d20 100644 --- a/ref-manual/xed-iformfl-enum_8h.html +++ b/ref-manual/xed-iformfl-enum_8h.html @@ -2212,6 +2212,10 @@   #define XED_IFORMFL_MOVQ_LAST_DEFINED   1   +#define XED_IFORMFL_MOVRS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_MOVRS_LAST_DEFINED   1 +  #define XED_IFORMFL_MOVSB_FIRST_DEFINED   1   #define XED_IFORMFL_MOVSB_LAST_DEFINED   1 @@ -2880,6 +2884,10 @@   #define XED_IFORMFL_PREFETCHNTA_LAST_DEFINED   1   +#define XED_IFORMFL_PREFETCHRST2_FIRST_DEFINED   1 +  +#define XED_IFORMFL_PREFETCHRST2_LAST_DEFINED   1 +  #define XED_IFORMFL_PREFETCHT0_FIRST_DEFINED   1   #define XED_IFORMFL_PREFETCHT0_LAST_DEFINED   1 @@ -3752,6 +3760,38 @@   #define XED_IFORMFL_T1MSKC_LAST_DEFINED   1   +#define XED_IFORMFL_T2RPNTLVWZ0_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0RS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0RS_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0RST1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0RST1_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0T1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ0T1_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1RS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1RS_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1RST1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1RST1_LAST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1T1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_T2RPNTLVWZ1T1_LAST_DEFINED   1 +  #define XED_IFORMFL_TCMMIMFP16PS_FIRST_DEFINED   1   #define XED_IFORMFL_TCMMIMFP16PS_LAST_DEFINED   1 @@ -3760,6 +3800,34 @@   #define XED_IFORMFL_TCMMRLFP16PS_LAST_DEFINED   1   +#define XED_IFORMFL_TCONJTCMMIMFP16PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCONJTCMMIMFP16PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCONJTFP16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCONJTFP16_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWD2PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWD2PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PBF16H_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PBF16H_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PBF16L_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PBF16L_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PHH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PHH_LAST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PHL_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TCVTROWPS2PHL_LAST_DEFINED   1 +  #define XED_IFORMFL_TDCALL_FIRST_DEFINED   1   #define XED_IFORMFL_TDCALL_LAST_DEFINED   1 @@ -3768,6 +3836,14 @@   #define XED_IFORMFL_TDPBF16PS_LAST_DEFINED   1   +#define XED_IFORMFL_TDPBF8PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TDPBF8PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TDPBHF8PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TDPBHF8PS_LAST_DEFINED   1 +  #define XED_IFORMFL_TDPBSSD_FIRST_DEFINED   1   #define XED_IFORMFL_TDPBSSD_LAST_DEFINED   1 @@ -3788,6 +3864,14 @@   #define XED_IFORMFL_TDPFP16PS_LAST_DEFINED   1   +#define XED_IFORMFL_TDPHBF8PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TDPHBF8PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TDPHF8PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TDPHF8PS_LAST_DEFINED   1 +  #define XED_IFORMFL_TEST_FIRST_DEFINED   1   #define XED_IFORMFL_TEST_LAST_DEFINED   1 @@ -3800,10 +3884,22 @@   #define XED_IFORMFL_TILELOADD_LAST_DEFINED   1   +#define XED_IFORMFL_TILELOADDRS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TILELOADDRS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TILELOADDRST1_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TILELOADDRST1_LAST_DEFINED   1 +  #define XED_IFORMFL_TILELOADDT1_FIRST_DEFINED   1   #define XED_IFORMFL_TILELOADDT1_LAST_DEFINED   1   +#define XED_IFORMFL_TILEMOVROW_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TILEMOVROW_LAST_DEFINED   1 +  #define XED_IFORMFL_TILERELEASE_FIRST_DEFINED   1   #define XED_IFORMFL_TILERELEASE_LAST_DEFINED   1 @@ -3820,10 +3916,38 @@   #define XED_IFORMFL_TLBSYNC_LAST_DEFINED   1   +#define XED_IFORMFL_TMMULTF32PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TMMULTF32PS_LAST_DEFINED   1 +  #define XED_IFORMFL_TPAUSE_FIRST_DEFINED   1   #define XED_IFORMFL_TPAUSE_LAST_DEFINED   1   +#define XED_IFORMFL_TTCMMIMFP16PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTCMMIMFP16PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TTCMMRLFP16PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTCMMRLFP16PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TTDPBF16PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTDPBF16PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TTDPFP16PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTDPFP16PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TTMMULTF32PS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTMMULTF32PS_LAST_DEFINED   1 +  +#define XED_IFORMFL_TTRANSPOSED_FIRST_DEFINED   1 +  +#define XED_IFORMFL_TTRANSPOSED_LAST_DEFINED   1 +  #define XED_IFORMFL_TZCNT_FIRST_DEFINED   1   #define XED_IFORMFL_TZCNT_LAST_DEFINED   1 @@ -3904,6 +4028,10 @@   #define XED_IFORMFL_V4FNMADDSS_LAST_DEFINED   1   +#define XED_IFORMFL_VADDNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VADDNEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VADDPD_FIRST_DEFINED   1   #define XED_IFORMFL_VADDPD_LAST_DEFINED   1 @@ -4072,6 +4200,10 @@   #define XED_IFORMFL_VBROADCASTSS_LAST_DEFINED   1   +#define XED_IFORMFL_VCMPPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCMPPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VCMPPD_FIRST_DEFINED   1   #define XED_IFORMFL_VCMPPD_LAST_DEFINED   1 @@ -4116,6 +4248,42 @@   #define XED_IFORMFL_VCOMPRESSPS_LAST_DEFINED   1   +#define XED_IFORMFL_VCOMSBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCOMSBF16_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSD_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSD_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSH_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCOMXSS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVT2PS2PHX_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVT2PS2PHX_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2BF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2BF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2BF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2BF8S_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2HF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2HF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2HF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTBIASPH2HF8S_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTDQ2PD_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTDQ2PD_LAST_DEFINED   1 @@ -4128,10 +4296,38 @@   #define XED_IFORMFL_VCVTDQ2PS_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTHF82PH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTHF82PH_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2BF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2BF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2BF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2BF8S_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2HF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2HF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2HF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNE2PH2HF8S_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTNE2PS2BF16_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTNE2PS2BF16_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTNEBF162IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEBF162IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEBF162IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEBF162IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTNEEBF162PS_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTNEEBF162PS_LAST_DEFINED   1 @@ -4148,6 +4344,22 @@   #define XED_IFORMFL_VCVTNEOPH2PS_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTNEPH2BF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2BF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2BF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2BF8S_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2HF8_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2HF8_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2HF8S_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTNEPH2HF8S_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTNEPS2BF16_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTNEPS2BF16_LAST_DEFINED   1 @@ -4180,6 +4392,14 @@   #define XED_IFORMFL_VCVTPH2DQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTPH2IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPH2IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPH2IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPH2IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTPH2PD_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTPH2PD_LAST_DEFINED   1 @@ -4216,6 +4436,14 @@   #define XED_IFORMFL_VCVTPS2DQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTPS2IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPS2IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPS2IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTPS2IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTPS2PD_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTPS2PD_LAST_DEFINED   1 @@ -4312,26 +4540,58 @@   #define XED_IFORMFL_VCVTSS2USI_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTNEBF162IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTNEBF162IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTNEBF162IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTNEBF162IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPD2DQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPD2DQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPD2DQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPD2DQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPD2QQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPD2QQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPD2QQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPD2QQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPD2UDQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPD2UDQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPD2UDQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPD2UDQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPD2UQQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPD2UQQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPD2UQQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPD2UQQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPH2DQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPH2DQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPH2IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPH2IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPH2IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPH2IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPH2QQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPH2QQ_LAST_DEFINED   1 @@ -4356,26 +4616,58 @@   #define XED_IFORMFL_VCVTTPS2DQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPS2DQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2DQS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2IBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2IBS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2IUBS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2IUBS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPS2QQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPS2QQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPS2QQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2QQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPS2UDQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPS2UDQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPS2UDQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2UDQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTPS2UQQ_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTPS2UQQ_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTPS2UQQS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTPS2UQQS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTSD2SI_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTSD2SI_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTSD2SIS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTSD2SIS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTSD2USI_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTSD2USI_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTSD2USIS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTSD2USIS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTSH2SI_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTSH2SI_LAST_DEFINED   1 @@ -4388,10 +4680,18 @@   #define XED_IFORMFL_VCVTTSS2SI_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTSS2SIS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTSS2SIS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTTSS2USI_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTTSS2USI_LAST_DEFINED   1   +#define XED_IFORMFL_VCVTTSS2USIS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VCVTTSS2USIS_LAST_DEFINED   1 +  #define XED_IFORMFL_VCVTUDQ2PD_FIRST_DEFINED   1   #define XED_IFORMFL_VCVTUDQ2PD_LAST_DEFINED   1 @@ -4440,6 +4740,10 @@   #define XED_IFORMFL_VDBPSADBW_LAST_DEFINED   1   +#define XED_IFORMFL_VDIVNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VDIVNEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VDIVPD_FIRST_DEFINED   1   #define XED_IFORMFL_VDIVPD_LAST_DEFINED   1 @@ -4472,6 +4776,10 @@   #define XED_IFORMFL_VDPPD_LAST_DEFINED   1   +#define XED_IFORMFL_VDPPHPS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VDPPHPS_LAST_DEFINED   1 +  #define XED_IFORMFL_VDPPS_FIRST_DEFINED   1   #define XED_IFORMFL_VDPPS_LAST_DEFINED   1 @@ -4576,6 +4884,10 @@   #define XED_IFORMFL_VFIXUPIMMSS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMADD132NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMADD132NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMADD132PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMADD132PD_LAST_DEFINED   1 @@ -4600,6 +4912,10 @@   #define XED_IFORMFL_VFMADD132SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMADD213NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMADD213NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMADD213PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMADD213PD_LAST_DEFINED   1 @@ -4624,6 +4940,10 @@   #define XED_IFORMFL_VFMADD213SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMADD231NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMADD231NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMADD231PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMADD231PD_LAST_DEFINED   1 @@ -4716,6 +5036,10 @@   #define XED_IFORMFL_VFMADDSUBPS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMSUB132NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMSUB132NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMSUB132PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMSUB132PD_LAST_DEFINED   1 @@ -4740,6 +5064,10 @@   #define XED_IFORMFL_VFMSUB132SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMSUB213NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMSUB213NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMSUB213PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMSUB213PD_LAST_DEFINED   1 @@ -4764,6 +5092,10 @@   #define XED_IFORMFL_VFMSUB213SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFMSUB231NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFMSUB231NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFMSUB231PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFMSUB231PD_LAST_DEFINED   1 @@ -4856,6 +5188,10 @@   #define XED_IFORMFL_VFMULCSH_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMADD132NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMADD132NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMADD132PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMADD132PD_LAST_DEFINED   1 @@ -4880,6 +5216,10 @@   #define XED_IFORMFL_VFNMADD132SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMADD213NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMADD213NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMADD213PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMADD213PD_LAST_DEFINED   1 @@ -4904,6 +5244,10 @@   #define XED_IFORMFL_VFNMADD213SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMADD231NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMADD231NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMADD231PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMADD231PD_LAST_DEFINED   1 @@ -4944,6 +5288,10 @@   #define XED_IFORMFL_VFNMADDSS_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMSUB132NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMSUB132NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMSUB132PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMSUB132PD_LAST_DEFINED   1 @@ -4968,6 +5316,10 @@   #define XED_IFORMFL_VFNMSUB132SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMSUB213NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMSUB213NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMSUB213PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMSUB213PD_LAST_DEFINED   1 @@ -4992,6 +5344,10 @@   #define XED_IFORMFL_VFNMSUB213SS_LAST_DEFINED   1   +#define XED_IFORMFL_VFNMSUB231NEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFNMSUB231NEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFNMSUB231PD_FIRST_DEFINED   1   #define XED_IFORMFL_VFNMSUB231PD_LAST_DEFINED   1 @@ -5032,6 +5388,10 @@   #define XED_IFORMFL_VFNMSUBSS_LAST_DEFINED   1   +#define XED_IFORMFL_VFPCLASSPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VFPCLASSPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VFPCLASSPD_FIRST_DEFINED   1   #define XED_IFORMFL_VFPCLASSPD_LAST_DEFINED   1 @@ -5120,6 +5480,10 @@   #define XED_IFORMFL_VGATHERQPS_LAST_DEFINED   1   +#define XED_IFORMFL_VGETEXPPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VGETEXPPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VGETEXPPD_FIRST_DEFINED   1   #define XED_IFORMFL_VGETEXPPD_LAST_DEFINED   1 @@ -5144,6 +5508,10 @@   #define XED_IFORMFL_VGETEXPSS_LAST_DEFINED   1   +#define XED_IFORMFL_VGETMANTPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VGETMANTPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VGETMANTPD_FIRST_DEFINED   1   #define XED_IFORMFL_VGETMANTPD_LAST_DEFINED   1 @@ -5260,6 +5628,10 @@   #define XED_IFORMFL_VMASKMOVPS_LAST_DEFINED   1   +#define XED_IFORMFL_VMAXPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMAXPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VMAXPD_FIRST_DEFINED   1   #define XED_IFORMFL_VMAXPD_LAST_DEFINED   1 @@ -5296,6 +5668,38 @@   #define XED_IFORMFL_VMFUNC_LAST_DEFINED   1   +#define XED_IFORMFL_VMINMAXNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXNEPBF16_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPD_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPD_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPH_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXPS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSD_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSD_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSH_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINMAXSS_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMINPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMINPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VMINPD_FIRST_DEFINED   1   #define XED_IFORMFL_VMINPD_LAST_DEFINED   1 @@ -5432,6 +5836,22 @@   #define XED_IFORMFL_VMOVQ_LAST_DEFINED   1   +#define XED_IFORMFL_VMOVRSB_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSB_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSD_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSD_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSQ_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSQ_LAST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSW_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMOVRSW_LAST_DEFINED   1 +  #define XED_IFORMFL_VMOVSD_FIRST_DEFINED   1   #define XED_IFORMFL_VMOVSD_LAST_DEFINED   1 @@ -5492,6 +5912,10 @@   #define XED_IFORMFL_VMSAVE_LAST_DEFINED   1   +#define XED_IFORMFL_VMULNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VMULNEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VMULPD_FIRST_DEFINED   1   #define XED_IFORMFL_VMULPD_LAST_DEFINED   1 @@ -6972,6 +7396,10 @@   #define XED_IFORMFL_VRCP28SS_LAST_DEFINED   1   +#define XED_IFORMFL_VRCPPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VRCPPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VRCPPH_FIRST_DEFINED   1   #define XED_IFORMFL_VRCPPH_LAST_DEFINED   1 @@ -6988,6 +7416,10 @@   #define XED_IFORMFL_VRCPSS_LAST_DEFINED   1   +#define XED_IFORMFL_VREDUCENEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VREDUCENEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VREDUCEPD_FIRST_DEFINED   1   #define XED_IFORMFL_VREDUCEPD_LAST_DEFINED   1 @@ -7012,6 +7444,10 @@   #define XED_IFORMFL_VREDUCESS_LAST_DEFINED   1   +#define XED_IFORMFL_VRNDSCALENEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VRNDSCALENEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VRNDSCALEPD_FIRST_DEFINED   1   #define XED_IFORMFL_VRNDSCALEPD_LAST_DEFINED   1 @@ -7084,6 +7520,10 @@   #define XED_IFORMFL_VRSQRT28SS_LAST_DEFINED   1   +#define XED_IFORMFL_VRSQRTPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VRSQRTPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VRSQRTPH_FIRST_DEFINED   1   #define XED_IFORMFL_VRSQRTPH_LAST_DEFINED   1 @@ -7100,6 +7540,10 @@   #define XED_IFORMFL_VRSQRTSS_LAST_DEFINED   1   +#define XED_IFORMFL_VSCALEFPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VSCALEFPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VSCALEFPD_FIRST_DEFINED   1   #define XED_IFORMFL_VSCALEFPD_LAST_DEFINED   1 @@ -7228,6 +7672,10 @@   #define XED_IFORMFL_VSM4RNDS4_LAST_DEFINED   1   +#define XED_IFORMFL_VSQRTNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VSQRTNEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VSQRTPD_FIRST_DEFINED   1   #define XED_IFORMFL_VSQRTPD_LAST_DEFINED   1 @@ -7256,6 +7704,10 @@   #define XED_IFORMFL_VSTMXCSR_LAST_DEFINED   1   +#define XED_IFORMFL_VSUBNEPBF16_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VSUBNEPBF16_LAST_DEFINED   1 +  #define XED_IFORMFL_VSUBPD_FIRST_DEFINED   1   #define XED_IFORMFL_VSUBPD_LAST_DEFINED   1 @@ -7300,6 +7752,18 @@   #define XED_IFORMFL_VUCOMISS_LAST_DEFINED   1   +#define XED_IFORMFL_VUCOMXSD_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VUCOMXSD_LAST_DEFINED   1 +  +#define XED_IFORMFL_VUCOMXSH_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VUCOMXSH_LAST_DEFINED   1 +  +#define XED_IFORMFL_VUCOMXSS_FIRST_DEFINED   1 +  +#define XED_IFORMFL_VUCOMXSS_LAST_DEFINED   1 +  #define XED_IFORMFL_VUNPCKHPD_FIRST_DEFINED   1   #define XED_IFORMFL_VUNPCKHPD_LAST_DEFINED   1 @@ -9608,5297 +10072,5761 @@
  XED_IFORMFL_MOVQ2DQ_LAST =1650,
-  XED_IFORMFL_MOVSB_FIRST =1651, +  XED_IFORMFL_MOVRS_FIRST =1651,
-  XED_IFORMFL_MOVSB_LAST =1651, +  XED_IFORMFL_MOVRS_LAST =1652,
-  XED_IFORMFL_MOVSD_FIRST =1652, +  XED_IFORMFL_MOVSB_FIRST =1653,
-  XED_IFORMFL_MOVSD_LAST =1652, +  XED_IFORMFL_MOVSB_LAST =1653,
-  XED_IFORMFL_MOVSD_XMM_FIRST =1653, +  XED_IFORMFL_MOVSD_FIRST =1654,
-  XED_IFORMFL_MOVSD_XMM_LAST =1656, +  XED_IFORMFL_MOVSD_LAST =1654,
-  XED_IFORMFL_MOVSHDUP_FIRST =1657, +  XED_IFORMFL_MOVSD_XMM_FIRST =1655,
-  XED_IFORMFL_MOVSHDUP_LAST =1658, +  XED_IFORMFL_MOVSD_XMM_LAST =1658,
-  XED_IFORMFL_MOVSLDUP_FIRST =1659, +  XED_IFORMFL_MOVSHDUP_FIRST =1659,
-  XED_IFORMFL_MOVSLDUP_LAST =1660, +  XED_IFORMFL_MOVSHDUP_LAST =1660,
-  XED_IFORMFL_MOVSQ_FIRST =1661, +  XED_IFORMFL_MOVSLDUP_FIRST =1661,
-  XED_IFORMFL_MOVSQ_LAST =1661, +  XED_IFORMFL_MOVSLDUP_LAST =1662,
-  XED_IFORMFL_MOVSS_FIRST =1662, +  XED_IFORMFL_MOVSQ_FIRST =1663,
-  XED_IFORMFL_MOVSS_LAST =1665, +  XED_IFORMFL_MOVSQ_LAST =1663,
-  XED_IFORMFL_MOVSW_FIRST =1666, +  XED_IFORMFL_MOVSS_FIRST =1664,
-  XED_IFORMFL_MOVSW_LAST =1666, +  XED_IFORMFL_MOVSS_LAST =1667,
-  XED_IFORMFL_MOVSX_FIRST =1667, +  XED_IFORMFL_MOVSW_FIRST =1668,
-  XED_IFORMFL_MOVSX_LAST =1670, +  XED_IFORMFL_MOVSW_LAST =1668,
-  XED_IFORMFL_MOVSXD_FIRST =1671, +  XED_IFORMFL_MOVSX_FIRST =1669,
-  XED_IFORMFL_MOVSXD_LAST =1672, +  XED_IFORMFL_MOVSX_LAST =1672,
-  XED_IFORMFL_MOVUPD_FIRST =1673, +  XED_IFORMFL_MOVSXD_FIRST =1673,
-  XED_IFORMFL_MOVUPD_LAST =1676, +  XED_IFORMFL_MOVSXD_LAST =1674,
-  XED_IFORMFL_MOVUPS_FIRST =1677, +  XED_IFORMFL_MOVUPD_FIRST =1675,
-  XED_IFORMFL_MOVUPS_LAST =1680, +  XED_IFORMFL_MOVUPD_LAST =1678,
-  XED_IFORMFL_MOVZX_FIRST =1681, +  XED_IFORMFL_MOVUPS_FIRST =1679,
-  XED_IFORMFL_MOVZX_LAST =1684, +  XED_IFORMFL_MOVUPS_LAST =1682,
-  XED_IFORMFL_MOV_CR_FIRST =1685, +  XED_IFORMFL_MOVZX_FIRST =1683,
-  XED_IFORMFL_MOV_CR_LAST =1688, +  XED_IFORMFL_MOVZX_LAST =1686,
-  XED_IFORMFL_MOV_DR_FIRST =1689, +  XED_IFORMFL_MOV_CR_FIRST =1687,
-  XED_IFORMFL_MOV_DR_LAST =1692, +  XED_IFORMFL_MOV_CR_LAST =1690,
-  XED_IFORMFL_MPSADBW_FIRST =1693, +  XED_IFORMFL_MOV_DR_FIRST =1691,
-  XED_IFORMFL_MPSADBW_LAST =1694, +  XED_IFORMFL_MOV_DR_LAST =1694,
-  XED_IFORMFL_MUL_FIRST =1695, +  XED_IFORMFL_MPSADBW_FIRST =1695,
-  XED_IFORMFL_MUL_LAST =1702, +  XED_IFORMFL_MPSADBW_LAST =1696,
-  XED_IFORMFL_MULPD_FIRST =1703, +  XED_IFORMFL_MUL_FIRST =1697,
-  XED_IFORMFL_MULPD_LAST =1704, +  XED_IFORMFL_MUL_LAST =1704,
-  XED_IFORMFL_MULPS_FIRST =1705, +  XED_IFORMFL_MULPD_FIRST =1705,
-  XED_IFORMFL_MULPS_LAST =1706, +  XED_IFORMFL_MULPD_LAST =1706,
-  XED_IFORMFL_MULSD_FIRST =1707, +  XED_IFORMFL_MULPS_FIRST =1707,
-  XED_IFORMFL_MULSD_LAST =1708, +  XED_IFORMFL_MULPS_LAST =1708,
-  XED_IFORMFL_MULSS_FIRST =1709, +  XED_IFORMFL_MULSD_FIRST =1709,
-  XED_IFORMFL_MULSS_LAST =1710, +  XED_IFORMFL_MULSD_LAST =1710,
-  XED_IFORMFL_MULX_FIRST =1711, +  XED_IFORMFL_MULSS_FIRST =1711,
-  XED_IFORMFL_MULX_LAST =1718, +  XED_IFORMFL_MULSS_LAST =1712,
-  XED_IFORMFL_MWAIT_FIRST =1719, +  XED_IFORMFL_MULX_FIRST =1713,
-  XED_IFORMFL_MWAIT_LAST =1719, +  XED_IFORMFL_MULX_LAST =1720,
-  XED_IFORMFL_MWAITX_FIRST =1720, +  XED_IFORMFL_MWAIT_FIRST =1721,
-  XED_IFORMFL_MWAITX_LAST =1720, +  XED_IFORMFL_MWAIT_LAST =1721,
-  XED_IFORMFL_NEG_FIRST =1721, +  XED_IFORMFL_MWAITX_FIRST =1722,
-  XED_IFORMFL_NEG_LAST =1732, +  XED_IFORMFL_MWAITX_LAST =1722,
-  XED_IFORMFL_NEG_LOCK_FIRST =1733, +  XED_IFORMFL_NEG_FIRST =1723,
-  XED_IFORMFL_NEG_LOCK_LAST =1734, +  XED_IFORMFL_NEG_LAST =1734,
-  XED_IFORMFL_NOP_FIRST =1735, +  XED_IFORMFL_NEG_LOCK_FIRST =1735,
-  XED_IFORMFL_NOP_LAST =1760, +  XED_IFORMFL_NEG_LOCK_LAST =1736,
-  XED_IFORMFL_NOT_FIRST =1761, +  XED_IFORMFL_NOP_FIRST =1737,
-  XED_IFORMFL_NOT_LAST =1772, +  XED_IFORMFL_NOP_LAST =1761,
-  XED_IFORMFL_NOT_LOCK_FIRST =1773, +  XED_IFORMFL_NOT_FIRST =1762,
-  XED_IFORMFL_NOT_LOCK_LAST =1774, +  XED_IFORMFL_NOT_LAST =1773,
-  XED_IFORMFL_OR_FIRST =1775, +  XED_IFORMFL_NOT_LOCK_FIRST =1774,
-  XED_IFORMFL_OR_LAST =1816, +  XED_IFORMFL_NOT_LOCK_LAST =1775,
-  XED_IFORMFL_ORPD_FIRST =1817, +  XED_IFORMFL_OR_FIRST =1776,
-  XED_IFORMFL_ORPD_LAST =1818, +  XED_IFORMFL_OR_LAST =1817,
-  XED_IFORMFL_ORPS_FIRST =1819, +  XED_IFORMFL_ORPD_FIRST =1818,
-  XED_IFORMFL_ORPS_LAST =1820, +  XED_IFORMFL_ORPD_LAST =1819,
-  XED_IFORMFL_OR_LOCK_FIRST =1821, +  XED_IFORMFL_ORPS_FIRST =1820,
-  XED_IFORMFL_OR_LOCK_LAST =1826, +  XED_IFORMFL_ORPS_LAST =1821,
-  XED_IFORMFL_OUT_FIRST =1827, +  XED_IFORMFL_OR_LOCK_FIRST =1822,
-  XED_IFORMFL_OUT_LAST =1830, +  XED_IFORMFL_OR_LOCK_LAST =1827,
-  XED_IFORMFL_OUTSB_FIRST =1831, +  XED_IFORMFL_OUT_FIRST =1828,
-  XED_IFORMFL_OUTSB_LAST =1831, +  XED_IFORMFL_OUT_LAST =1831,
-  XED_IFORMFL_OUTSD_FIRST =1832, +  XED_IFORMFL_OUTSB_FIRST =1832,
-  XED_IFORMFL_OUTSD_LAST =1832, +  XED_IFORMFL_OUTSB_LAST =1832,
-  XED_IFORMFL_OUTSW_FIRST =1833, +  XED_IFORMFL_OUTSD_FIRST =1833,
-  XED_IFORMFL_OUTSW_LAST =1833, +  XED_IFORMFL_OUTSD_LAST =1833,
-  XED_IFORMFL_PABSB_FIRST =1834, +  XED_IFORMFL_OUTSW_FIRST =1834,
-  XED_IFORMFL_PABSB_LAST =1837, +  XED_IFORMFL_OUTSW_LAST =1834,
-  XED_IFORMFL_PABSD_FIRST =1838, +  XED_IFORMFL_PABSB_FIRST =1835,
-  XED_IFORMFL_PABSD_LAST =1841, +  XED_IFORMFL_PABSB_LAST =1838,
-  XED_IFORMFL_PABSW_FIRST =1842, +  XED_IFORMFL_PABSD_FIRST =1839,
-  XED_IFORMFL_PABSW_LAST =1845, +  XED_IFORMFL_PABSD_LAST =1842,
-  XED_IFORMFL_PACKSSDW_FIRST =1846, +  XED_IFORMFL_PABSW_FIRST =1843,
-  XED_IFORMFL_PACKSSDW_LAST =1849, +  XED_IFORMFL_PABSW_LAST =1846,
-  XED_IFORMFL_PACKSSWB_FIRST =1850, +  XED_IFORMFL_PACKSSDW_FIRST =1847,
-  XED_IFORMFL_PACKSSWB_LAST =1853, +  XED_IFORMFL_PACKSSDW_LAST =1850,
-  XED_IFORMFL_PACKUSDW_FIRST =1854, +  XED_IFORMFL_PACKSSWB_FIRST =1851,
-  XED_IFORMFL_PACKUSDW_LAST =1855, +  XED_IFORMFL_PACKSSWB_LAST =1854,
-  XED_IFORMFL_PACKUSWB_FIRST =1856, +  XED_IFORMFL_PACKUSDW_FIRST =1855,
-  XED_IFORMFL_PACKUSWB_LAST =1859, +  XED_IFORMFL_PACKUSDW_LAST =1856,
-  XED_IFORMFL_PADDB_FIRST =1860, +  XED_IFORMFL_PACKUSWB_FIRST =1857,
-  XED_IFORMFL_PADDB_LAST =1863, +  XED_IFORMFL_PACKUSWB_LAST =1860,
-  XED_IFORMFL_PADDD_FIRST =1864, +  XED_IFORMFL_PADDB_FIRST =1861,
-  XED_IFORMFL_PADDD_LAST =1867, +  XED_IFORMFL_PADDB_LAST =1864,
-  XED_IFORMFL_PADDQ_FIRST =1868, +  XED_IFORMFL_PADDD_FIRST =1865,
-  XED_IFORMFL_PADDQ_LAST =1871, +  XED_IFORMFL_PADDD_LAST =1868,
-  XED_IFORMFL_PADDSB_FIRST =1872, +  XED_IFORMFL_PADDQ_FIRST =1869,
-  XED_IFORMFL_PADDSB_LAST =1875, +  XED_IFORMFL_PADDQ_LAST =1872,
-  XED_IFORMFL_PADDSW_FIRST =1876, +  XED_IFORMFL_PADDSB_FIRST =1873,
-  XED_IFORMFL_PADDSW_LAST =1879, +  XED_IFORMFL_PADDSB_LAST =1876,
-  XED_IFORMFL_PADDUSB_FIRST =1880, +  XED_IFORMFL_PADDSW_FIRST =1877,
-  XED_IFORMFL_PADDUSB_LAST =1883, +  XED_IFORMFL_PADDSW_LAST =1880,
-  XED_IFORMFL_PADDUSW_FIRST =1884, +  XED_IFORMFL_PADDUSB_FIRST =1881,
-  XED_IFORMFL_PADDUSW_LAST =1887, +  XED_IFORMFL_PADDUSB_LAST =1884,
-  XED_IFORMFL_PADDW_FIRST =1888, +  XED_IFORMFL_PADDUSW_FIRST =1885,
-  XED_IFORMFL_PADDW_LAST =1891, +  XED_IFORMFL_PADDUSW_LAST =1888,
-  XED_IFORMFL_PALIGNR_FIRST =1892, +  XED_IFORMFL_PADDW_FIRST =1889,
-  XED_IFORMFL_PALIGNR_LAST =1895, +  XED_IFORMFL_PADDW_LAST =1892,
-  XED_IFORMFL_PAND_FIRST =1896, +  XED_IFORMFL_PALIGNR_FIRST =1893,
-  XED_IFORMFL_PAND_LAST =1899, +  XED_IFORMFL_PALIGNR_LAST =1896,
-  XED_IFORMFL_PANDN_FIRST =1900, +  XED_IFORMFL_PAND_FIRST =1897,
-  XED_IFORMFL_PANDN_LAST =1903, +  XED_IFORMFL_PAND_LAST =1900,
-  XED_IFORMFL_PAUSE_FIRST =1904, +  XED_IFORMFL_PANDN_FIRST =1901,
-  XED_IFORMFL_PAUSE_LAST =1904, +  XED_IFORMFL_PANDN_LAST =1904,
-  XED_IFORMFL_PAVGB_FIRST =1905, +  XED_IFORMFL_PAUSE_FIRST =1905,
-  XED_IFORMFL_PAVGB_LAST =1908, +  XED_IFORMFL_PAUSE_LAST =1905,
-  XED_IFORMFL_PAVGUSB_FIRST =1909, +  XED_IFORMFL_PAVGB_FIRST =1906,
-  XED_IFORMFL_PAVGUSB_LAST =1910, +  XED_IFORMFL_PAVGB_LAST =1909,
-  XED_IFORMFL_PAVGW_FIRST =1911, +  XED_IFORMFL_PAVGUSB_FIRST =1910,
-  XED_IFORMFL_PAVGW_LAST =1914, +  XED_IFORMFL_PAVGUSB_LAST =1911,
-  XED_IFORMFL_PBLENDVB_FIRST =1915, +  XED_IFORMFL_PAVGW_FIRST =1912,
-  XED_IFORMFL_PBLENDVB_LAST =1916, +  XED_IFORMFL_PAVGW_LAST =1915,
-  XED_IFORMFL_PBLENDW_FIRST =1917, +  XED_IFORMFL_PBLENDVB_FIRST =1916,
-  XED_IFORMFL_PBLENDW_LAST =1918, +  XED_IFORMFL_PBLENDVB_LAST =1917,
-  XED_IFORMFL_PBNDKB_FIRST =1919, +  XED_IFORMFL_PBLENDW_FIRST =1918,
-  XED_IFORMFL_PBNDKB_LAST =1919, +  XED_IFORMFL_PBLENDW_LAST =1919,
-  XED_IFORMFL_PCLMULQDQ_FIRST =1920, +  XED_IFORMFL_PBNDKB_FIRST =1920,
-  XED_IFORMFL_PCLMULQDQ_LAST =1921, +  XED_IFORMFL_PBNDKB_LAST =1920,
-  XED_IFORMFL_PCMPEQB_FIRST =1922, +  XED_IFORMFL_PCLMULQDQ_FIRST =1921,
-  XED_IFORMFL_PCMPEQB_LAST =1925, +  XED_IFORMFL_PCLMULQDQ_LAST =1922,
-  XED_IFORMFL_PCMPEQD_FIRST =1926, +  XED_IFORMFL_PCMPEQB_FIRST =1923,
-  XED_IFORMFL_PCMPEQD_LAST =1929, +  XED_IFORMFL_PCMPEQB_LAST =1926,
-  XED_IFORMFL_PCMPEQQ_FIRST =1930, +  XED_IFORMFL_PCMPEQD_FIRST =1927,
-  XED_IFORMFL_PCMPEQQ_LAST =1931, +  XED_IFORMFL_PCMPEQD_LAST =1930,
-  XED_IFORMFL_PCMPEQW_FIRST =1932, +  XED_IFORMFL_PCMPEQQ_FIRST =1931,
-  XED_IFORMFL_PCMPEQW_LAST =1935, +  XED_IFORMFL_PCMPEQQ_LAST =1932,
-  XED_IFORMFL_PCMPESTRI_FIRST =1936, +  XED_IFORMFL_PCMPEQW_FIRST =1933,
-  XED_IFORMFL_PCMPESTRI_LAST =1937, +  XED_IFORMFL_PCMPEQW_LAST =1936,
-  XED_IFORMFL_PCMPESTRI64_FIRST =1938, +  XED_IFORMFL_PCMPESTRI_FIRST =1937,
-  XED_IFORMFL_PCMPESTRI64_LAST =1939, +  XED_IFORMFL_PCMPESTRI_LAST =1938,
-  XED_IFORMFL_PCMPESTRM_FIRST =1940, +  XED_IFORMFL_PCMPESTRI64_FIRST =1939,
-  XED_IFORMFL_PCMPESTRM_LAST =1941, +  XED_IFORMFL_PCMPESTRI64_LAST =1940,
-  XED_IFORMFL_PCMPESTRM64_FIRST =1942, +  XED_IFORMFL_PCMPESTRM_FIRST =1941,
-  XED_IFORMFL_PCMPESTRM64_LAST =1943, +  XED_IFORMFL_PCMPESTRM_LAST =1942,
-  XED_IFORMFL_PCMPGTB_FIRST =1944, +  XED_IFORMFL_PCMPESTRM64_FIRST =1943,
-  XED_IFORMFL_PCMPGTB_LAST =1947, +  XED_IFORMFL_PCMPESTRM64_LAST =1944,
-  XED_IFORMFL_PCMPGTD_FIRST =1948, +  XED_IFORMFL_PCMPGTB_FIRST =1945,
-  XED_IFORMFL_PCMPGTD_LAST =1951, +  XED_IFORMFL_PCMPGTB_LAST =1948,
-  XED_IFORMFL_PCMPGTQ_FIRST =1952, +  XED_IFORMFL_PCMPGTD_FIRST =1949,
-  XED_IFORMFL_PCMPGTQ_LAST =1953, +  XED_IFORMFL_PCMPGTD_LAST =1952,
-  XED_IFORMFL_PCMPGTW_FIRST =1954, +  XED_IFORMFL_PCMPGTQ_FIRST =1953,
-  XED_IFORMFL_PCMPGTW_LAST =1957, +  XED_IFORMFL_PCMPGTQ_LAST =1954,
-  XED_IFORMFL_PCMPISTRI_FIRST =1958, +  XED_IFORMFL_PCMPGTW_FIRST =1955,
-  XED_IFORMFL_PCMPISTRI_LAST =1959, +  XED_IFORMFL_PCMPGTW_LAST =1958,
-  XED_IFORMFL_PCMPISTRI64_FIRST =1960, +  XED_IFORMFL_PCMPISTRI_FIRST =1959,
-  XED_IFORMFL_PCMPISTRI64_LAST =1961, +  XED_IFORMFL_PCMPISTRI_LAST =1960,
-  XED_IFORMFL_PCMPISTRM_FIRST =1962, +  XED_IFORMFL_PCMPISTRI64_FIRST =1961,
-  XED_IFORMFL_PCMPISTRM_LAST =1963, +  XED_IFORMFL_PCMPISTRI64_LAST =1962,
-  XED_IFORMFL_PCONFIG_FIRST =1964, +  XED_IFORMFL_PCMPISTRM_FIRST =1963,
-  XED_IFORMFL_PCONFIG_LAST =1965, +  XED_IFORMFL_PCMPISTRM_LAST =1964,
-  XED_IFORMFL_PDEP_FIRST =1966, +  XED_IFORMFL_PCONFIG_FIRST =1965,
-  XED_IFORMFL_PDEP_LAST =1973, +  XED_IFORMFL_PCONFIG_LAST =1966,
-  XED_IFORMFL_PEXT_FIRST =1974, +  XED_IFORMFL_PDEP_FIRST =1967,
-  XED_IFORMFL_PEXT_LAST =1981, +  XED_IFORMFL_PDEP_LAST =1974,
-  XED_IFORMFL_PEXTRB_FIRST =1982, +  XED_IFORMFL_PEXT_FIRST =1975,
-  XED_IFORMFL_PEXTRB_LAST =1983, +  XED_IFORMFL_PEXT_LAST =1982,
-  XED_IFORMFL_PEXTRD_FIRST =1984, +  XED_IFORMFL_PEXTRB_FIRST =1983,
-  XED_IFORMFL_PEXTRD_LAST =1985, +  XED_IFORMFL_PEXTRB_LAST =1984,
-  XED_IFORMFL_PEXTRQ_FIRST =1986, +  XED_IFORMFL_PEXTRD_FIRST =1985,
-  XED_IFORMFL_PEXTRQ_LAST =1987, +  XED_IFORMFL_PEXTRD_LAST =1986,
-  XED_IFORMFL_PEXTRW_FIRST =1988, +  XED_IFORMFL_PEXTRQ_FIRST =1987,
-  XED_IFORMFL_PEXTRW_LAST =1989, +  XED_IFORMFL_PEXTRQ_LAST =1988,
-  XED_IFORMFL_PEXTRW_SSE4_FIRST =1990, +  XED_IFORMFL_PEXTRW_FIRST =1989,
-  XED_IFORMFL_PEXTRW_SSE4_LAST =1991, +  XED_IFORMFL_PEXTRW_LAST =1990,
-  XED_IFORMFL_PF2ID_FIRST =1992, +  XED_IFORMFL_PEXTRW_SSE4_FIRST =1991,
-  XED_IFORMFL_PF2ID_LAST =1993, +  XED_IFORMFL_PEXTRW_SSE4_LAST =1992,
-  XED_IFORMFL_PF2IW_FIRST =1994, +  XED_IFORMFL_PF2ID_FIRST =1993,
-  XED_IFORMFL_PF2IW_LAST =1995, +  XED_IFORMFL_PF2ID_LAST =1994,
-  XED_IFORMFL_PFACC_FIRST =1996, +  XED_IFORMFL_PF2IW_FIRST =1995,
-  XED_IFORMFL_PFACC_LAST =1997, +  XED_IFORMFL_PF2IW_LAST =1996,
-  XED_IFORMFL_PFADD_FIRST =1998, +  XED_IFORMFL_PFACC_FIRST =1997,
-  XED_IFORMFL_PFADD_LAST =1999, +  XED_IFORMFL_PFACC_LAST =1998,
-  XED_IFORMFL_PFCMPEQ_FIRST =2000, +  XED_IFORMFL_PFADD_FIRST =1999,
-  XED_IFORMFL_PFCMPEQ_LAST =2001, +  XED_IFORMFL_PFADD_LAST =2000,
-  XED_IFORMFL_PFCMPGE_FIRST =2002, +  XED_IFORMFL_PFCMPEQ_FIRST =2001,
-  XED_IFORMFL_PFCMPGE_LAST =2003, +  XED_IFORMFL_PFCMPEQ_LAST =2002,
-  XED_IFORMFL_PFCMPGT_FIRST =2004, +  XED_IFORMFL_PFCMPGE_FIRST =2003,
-  XED_IFORMFL_PFCMPGT_LAST =2005, +  XED_IFORMFL_PFCMPGE_LAST =2004,
-  XED_IFORMFL_PFMAX_FIRST =2006, +  XED_IFORMFL_PFCMPGT_FIRST =2005,
-  XED_IFORMFL_PFMAX_LAST =2007, +  XED_IFORMFL_PFCMPGT_LAST =2006,
-  XED_IFORMFL_PFMIN_FIRST =2008, +  XED_IFORMFL_PFMAX_FIRST =2007,
-  XED_IFORMFL_PFMIN_LAST =2009, +  XED_IFORMFL_PFMAX_LAST =2008,
-  XED_IFORMFL_PFMUL_FIRST =2010, +  XED_IFORMFL_PFMIN_FIRST =2009,
-  XED_IFORMFL_PFMUL_LAST =2011, +  XED_IFORMFL_PFMIN_LAST =2010,
-  XED_IFORMFL_PFNACC_FIRST =2012, +  XED_IFORMFL_PFMUL_FIRST =2011,
-  XED_IFORMFL_PFNACC_LAST =2013, +  XED_IFORMFL_PFMUL_LAST =2012,
-  XED_IFORMFL_PFPNACC_FIRST =2014, +  XED_IFORMFL_PFNACC_FIRST =2013,
-  XED_IFORMFL_PFPNACC_LAST =2015, +  XED_IFORMFL_PFNACC_LAST =2014,
-  XED_IFORMFL_PFRCP_FIRST =2016, +  XED_IFORMFL_PFPNACC_FIRST =2015,
-  XED_IFORMFL_PFRCP_LAST =2017, +  XED_IFORMFL_PFPNACC_LAST =2016,
-  XED_IFORMFL_PFRCPIT1_FIRST =2018, +  XED_IFORMFL_PFRCP_FIRST =2017,
-  XED_IFORMFL_PFRCPIT1_LAST =2019, +  XED_IFORMFL_PFRCP_LAST =2018,
-  XED_IFORMFL_PFRCPIT2_FIRST =2020, +  XED_IFORMFL_PFRCPIT1_FIRST =2019,
-  XED_IFORMFL_PFRCPIT2_LAST =2021, +  XED_IFORMFL_PFRCPIT1_LAST =2020,
-  XED_IFORMFL_PFRSQIT1_FIRST =2022, +  XED_IFORMFL_PFRCPIT2_FIRST =2021,
-  XED_IFORMFL_PFRSQIT1_LAST =2023, +  XED_IFORMFL_PFRCPIT2_LAST =2022,
-  XED_IFORMFL_PFRSQRT_FIRST =2024, +  XED_IFORMFL_PFRSQIT1_FIRST =2023,
-  XED_IFORMFL_PFRSQRT_LAST =2025, +  XED_IFORMFL_PFRSQIT1_LAST =2024,
-  XED_IFORMFL_PFSUB_FIRST =2026, +  XED_IFORMFL_PFRSQRT_FIRST =2025,
-  XED_IFORMFL_PFSUB_LAST =2027, +  XED_IFORMFL_PFRSQRT_LAST =2026,
-  XED_IFORMFL_PFSUBR_FIRST =2028, +  XED_IFORMFL_PFSUB_FIRST =2027,
-  XED_IFORMFL_PFSUBR_LAST =2029, +  XED_IFORMFL_PFSUB_LAST =2028,
-  XED_IFORMFL_PHADDD_FIRST =2030, +  XED_IFORMFL_PFSUBR_FIRST =2029,
-  XED_IFORMFL_PHADDD_LAST =2033, +  XED_IFORMFL_PFSUBR_LAST =2030,
-  XED_IFORMFL_PHADDSW_FIRST =2034, +  XED_IFORMFL_PHADDD_FIRST =2031,
-  XED_IFORMFL_PHADDSW_LAST =2037, +  XED_IFORMFL_PHADDD_LAST =2034,
-  XED_IFORMFL_PHADDW_FIRST =2038, +  XED_IFORMFL_PHADDSW_FIRST =2035,
-  XED_IFORMFL_PHADDW_LAST =2041, +  XED_IFORMFL_PHADDSW_LAST =2038,
-  XED_IFORMFL_PHMINPOSUW_FIRST =2042, +  XED_IFORMFL_PHADDW_FIRST =2039,
-  XED_IFORMFL_PHMINPOSUW_LAST =2043, +  XED_IFORMFL_PHADDW_LAST =2042,
-  XED_IFORMFL_PHSUBD_FIRST =2044, +  XED_IFORMFL_PHMINPOSUW_FIRST =2043,
-  XED_IFORMFL_PHSUBD_LAST =2047, +  XED_IFORMFL_PHMINPOSUW_LAST =2044,
-  XED_IFORMFL_PHSUBSW_FIRST =2048, +  XED_IFORMFL_PHSUBD_FIRST =2045,
-  XED_IFORMFL_PHSUBSW_LAST =2051, +  XED_IFORMFL_PHSUBD_LAST =2048,
-  XED_IFORMFL_PHSUBW_FIRST =2052, +  XED_IFORMFL_PHSUBSW_FIRST =2049,
-  XED_IFORMFL_PHSUBW_LAST =2055, +  XED_IFORMFL_PHSUBSW_LAST =2052,
-  XED_IFORMFL_PI2FD_FIRST =2056, +  XED_IFORMFL_PHSUBW_FIRST =2053,
-  XED_IFORMFL_PI2FD_LAST =2057, +  XED_IFORMFL_PHSUBW_LAST =2056,
-  XED_IFORMFL_PI2FW_FIRST =2058, +  XED_IFORMFL_PI2FD_FIRST =2057,
-  XED_IFORMFL_PI2FW_LAST =2059, +  XED_IFORMFL_PI2FD_LAST =2058,
-  XED_IFORMFL_PINSRB_FIRST =2060, +  XED_IFORMFL_PI2FW_FIRST =2059,
-  XED_IFORMFL_PINSRB_LAST =2061, +  XED_IFORMFL_PI2FW_LAST =2060,
-  XED_IFORMFL_PINSRD_FIRST =2062, +  XED_IFORMFL_PINSRB_FIRST =2061,
-  XED_IFORMFL_PINSRD_LAST =2063, +  XED_IFORMFL_PINSRB_LAST =2062,
-  XED_IFORMFL_PINSRQ_FIRST =2064, +  XED_IFORMFL_PINSRD_FIRST =2063,
-  XED_IFORMFL_PINSRQ_LAST =2065, +  XED_IFORMFL_PINSRD_LAST =2064,
-  XED_IFORMFL_PINSRW_FIRST =2066, +  XED_IFORMFL_PINSRQ_FIRST =2065,
-  XED_IFORMFL_PINSRW_LAST =2069, +  XED_IFORMFL_PINSRQ_LAST =2066,
-  XED_IFORMFL_PMADDUBSW_FIRST =2070, +  XED_IFORMFL_PINSRW_FIRST =2067,
-  XED_IFORMFL_PMADDUBSW_LAST =2073, +  XED_IFORMFL_PINSRW_LAST =2070,
-  XED_IFORMFL_PMADDWD_FIRST =2074, +  XED_IFORMFL_PMADDUBSW_FIRST =2071,
-  XED_IFORMFL_PMADDWD_LAST =2077, +  XED_IFORMFL_PMADDUBSW_LAST =2074,
-  XED_IFORMFL_PMAXSB_FIRST =2078, +  XED_IFORMFL_PMADDWD_FIRST =2075,
-  XED_IFORMFL_PMAXSB_LAST =2079, +  XED_IFORMFL_PMADDWD_LAST =2078,
-  XED_IFORMFL_PMAXSD_FIRST =2080, +  XED_IFORMFL_PMAXSB_FIRST =2079,
-  XED_IFORMFL_PMAXSD_LAST =2081, +  XED_IFORMFL_PMAXSB_LAST =2080,
-  XED_IFORMFL_PMAXSW_FIRST =2082, +  XED_IFORMFL_PMAXSD_FIRST =2081,
-  XED_IFORMFL_PMAXSW_LAST =2085, +  XED_IFORMFL_PMAXSD_LAST =2082,
-  XED_IFORMFL_PMAXUB_FIRST =2086, +  XED_IFORMFL_PMAXSW_FIRST =2083,
-  XED_IFORMFL_PMAXUB_LAST =2089, +  XED_IFORMFL_PMAXSW_LAST =2086,
-  XED_IFORMFL_PMAXUD_FIRST =2090, +  XED_IFORMFL_PMAXUB_FIRST =2087,
-  XED_IFORMFL_PMAXUD_LAST =2091, +  XED_IFORMFL_PMAXUB_LAST =2090,
-  XED_IFORMFL_PMAXUW_FIRST =2092, +  XED_IFORMFL_PMAXUD_FIRST =2091,
-  XED_IFORMFL_PMAXUW_LAST =2093, +  XED_IFORMFL_PMAXUD_LAST =2092,
-  XED_IFORMFL_PMINSB_FIRST =2094, +  XED_IFORMFL_PMAXUW_FIRST =2093,
-  XED_IFORMFL_PMINSB_LAST =2095, +  XED_IFORMFL_PMAXUW_LAST =2094,
-  XED_IFORMFL_PMINSD_FIRST =2096, +  XED_IFORMFL_PMINSB_FIRST =2095,
-  XED_IFORMFL_PMINSD_LAST =2097, +  XED_IFORMFL_PMINSB_LAST =2096,
-  XED_IFORMFL_PMINSW_FIRST =2098, +  XED_IFORMFL_PMINSD_FIRST =2097,
-  XED_IFORMFL_PMINSW_LAST =2101, +  XED_IFORMFL_PMINSD_LAST =2098,
-  XED_IFORMFL_PMINUB_FIRST =2102, +  XED_IFORMFL_PMINSW_FIRST =2099,
-  XED_IFORMFL_PMINUB_LAST =2105, +  XED_IFORMFL_PMINSW_LAST =2102,
-  XED_IFORMFL_PMINUD_FIRST =2106, +  XED_IFORMFL_PMINUB_FIRST =2103,
-  XED_IFORMFL_PMINUD_LAST =2107, +  XED_IFORMFL_PMINUB_LAST =2106,
-  XED_IFORMFL_PMINUW_FIRST =2108, +  XED_IFORMFL_PMINUD_FIRST =2107,
-  XED_IFORMFL_PMINUW_LAST =2109, +  XED_IFORMFL_PMINUD_LAST =2108,
-  XED_IFORMFL_PMOVMSKB_FIRST =2110, +  XED_IFORMFL_PMINUW_FIRST =2109,
-  XED_IFORMFL_PMOVMSKB_LAST =2111, +  XED_IFORMFL_PMINUW_LAST =2110,
-  XED_IFORMFL_PMOVSXBD_FIRST =2112, +  XED_IFORMFL_PMOVMSKB_FIRST =2111,
-  XED_IFORMFL_PMOVSXBD_LAST =2113, +  XED_IFORMFL_PMOVMSKB_LAST =2112,
-  XED_IFORMFL_PMOVSXBQ_FIRST =2114, +  XED_IFORMFL_PMOVSXBD_FIRST =2113,
-  XED_IFORMFL_PMOVSXBQ_LAST =2115, +  XED_IFORMFL_PMOVSXBD_LAST =2114,
-  XED_IFORMFL_PMOVSXBW_FIRST =2116, +  XED_IFORMFL_PMOVSXBQ_FIRST =2115,
-  XED_IFORMFL_PMOVSXBW_LAST =2117, +  XED_IFORMFL_PMOVSXBQ_LAST =2116,
-  XED_IFORMFL_PMOVSXDQ_FIRST =2118, +  XED_IFORMFL_PMOVSXBW_FIRST =2117,
-  XED_IFORMFL_PMOVSXDQ_LAST =2119, +  XED_IFORMFL_PMOVSXBW_LAST =2118,
-  XED_IFORMFL_PMOVSXWD_FIRST =2120, +  XED_IFORMFL_PMOVSXDQ_FIRST =2119,
-  XED_IFORMFL_PMOVSXWD_LAST =2121, +  XED_IFORMFL_PMOVSXDQ_LAST =2120,
-  XED_IFORMFL_PMOVSXWQ_FIRST =2122, +  XED_IFORMFL_PMOVSXWD_FIRST =2121,
-  XED_IFORMFL_PMOVSXWQ_LAST =2123, +  XED_IFORMFL_PMOVSXWD_LAST =2122,
-  XED_IFORMFL_PMOVZXBD_FIRST =2124, +  XED_IFORMFL_PMOVSXWQ_FIRST =2123,
-  XED_IFORMFL_PMOVZXBD_LAST =2125, +  XED_IFORMFL_PMOVSXWQ_LAST =2124,
-  XED_IFORMFL_PMOVZXBQ_FIRST =2126, +  XED_IFORMFL_PMOVZXBD_FIRST =2125,
-  XED_IFORMFL_PMOVZXBQ_LAST =2127, +  XED_IFORMFL_PMOVZXBD_LAST =2126,
-  XED_IFORMFL_PMOVZXBW_FIRST =2128, +  XED_IFORMFL_PMOVZXBQ_FIRST =2127,
-  XED_IFORMFL_PMOVZXBW_LAST =2129, +  XED_IFORMFL_PMOVZXBQ_LAST =2128,
-  XED_IFORMFL_PMOVZXDQ_FIRST =2130, +  XED_IFORMFL_PMOVZXBW_FIRST =2129,
-  XED_IFORMFL_PMOVZXDQ_LAST =2131, +  XED_IFORMFL_PMOVZXBW_LAST =2130,
-  XED_IFORMFL_PMOVZXWD_FIRST =2132, +  XED_IFORMFL_PMOVZXDQ_FIRST =2131,
-  XED_IFORMFL_PMOVZXWD_LAST =2133, +  XED_IFORMFL_PMOVZXDQ_LAST =2132,
-  XED_IFORMFL_PMOVZXWQ_FIRST =2134, +  XED_IFORMFL_PMOVZXWD_FIRST =2133,
-  XED_IFORMFL_PMOVZXWQ_LAST =2135, +  XED_IFORMFL_PMOVZXWD_LAST =2134,
-  XED_IFORMFL_PMULDQ_FIRST =2136, +  XED_IFORMFL_PMOVZXWQ_FIRST =2135,
-  XED_IFORMFL_PMULDQ_LAST =2137, +  XED_IFORMFL_PMOVZXWQ_LAST =2136,
-  XED_IFORMFL_PMULHRSW_FIRST =2138, +  XED_IFORMFL_PMULDQ_FIRST =2137,
-  XED_IFORMFL_PMULHRSW_LAST =2141, +  XED_IFORMFL_PMULDQ_LAST =2138,
-  XED_IFORMFL_PMULHRW_FIRST =2142, +  XED_IFORMFL_PMULHRSW_FIRST =2139,
-  XED_IFORMFL_PMULHRW_LAST =2143, +  XED_IFORMFL_PMULHRSW_LAST =2142,
-  XED_IFORMFL_PMULHUW_FIRST =2144, +  XED_IFORMFL_PMULHRW_FIRST =2143,
-  XED_IFORMFL_PMULHUW_LAST =2147, +  XED_IFORMFL_PMULHRW_LAST =2144,
-  XED_IFORMFL_PMULHW_FIRST =2148, +  XED_IFORMFL_PMULHUW_FIRST =2145,
-  XED_IFORMFL_PMULHW_LAST =2151, +  XED_IFORMFL_PMULHUW_LAST =2148,
-  XED_IFORMFL_PMULLD_FIRST =2152, +  XED_IFORMFL_PMULHW_FIRST =2149,
-  XED_IFORMFL_PMULLD_LAST =2153, +  XED_IFORMFL_PMULHW_LAST =2152,
-  XED_IFORMFL_PMULLW_FIRST =2154, +  XED_IFORMFL_PMULLD_FIRST =2153,
-  XED_IFORMFL_PMULLW_LAST =2157, +  XED_IFORMFL_PMULLD_LAST =2154,
-  XED_IFORMFL_PMULUDQ_FIRST =2158, +  XED_IFORMFL_PMULLW_FIRST =2155,
-  XED_IFORMFL_PMULUDQ_LAST =2161, +  XED_IFORMFL_PMULLW_LAST =2158,
-  XED_IFORMFL_POP_FIRST =2162, +  XED_IFORMFL_PMULUDQ_FIRST =2159,
-  XED_IFORMFL_POP_LAST =2169, +  XED_IFORMFL_PMULUDQ_LAST =2162,
-  XED_IFORMFL_POP2_FIRST =2170, +  XED_IFORMFL_POP_FIRST =2163,
-  XED_IFORMFL_POP2_LAST =2170, +  XED_IFORMFL_POP_LAST =2170,
-  XED_IFORMFL_POP2P_FIRST =2171, +  XED_IFORMFL_POP2_FIRST =2171,
-  XED_IFORMFL_POP2P_LAST =2171, +  XED_IFORMFL_POP2_LAST =2171,
-  XED_IFORMFL_POPA_FIRST =2172, +  XED_IFORMFL_POP2P_FIRST =2172,
-  XED_IFORMFL_POPA_LAST =2172, +  XED_IFORMFL_POP2P_LAST =2172,
-  XED_IFORMFL_POPAD_FIRST =2173, +  XED_IFORMFL_POPA_FIRST =2173,
-  XED_IFORMFL_POPAD_LAST =2173, +  XED_IFORMFL_POPA_LAST =2173,
-  XED_IFORMFL_POPCNT_FIRST =2174, +  XED_IFORMFL_POPAD_FIRST =2174,
-  XED_IFORMFL_POPCNT_LAST =2177, +  XED_IFORMFL_POPAD_LAST =2174,
-  XED_IFORMFL_POPF_FIRST =2178, +  XED_IFORMFL_POPCNT_FIRST =2175,
-  XED_IFORMFL_POPF_LAST =2178, +  XED_IFORMFL_POPCNT_LAST =2178,
-  XED_IFORMFL_POPFD_FIRST =2179, +  XED_IFORMFL_POPF_FIRST =2179,
-  XED_IFORMFL_POPFD_LAST =2179, +  XED_IFORMFL_POPF_LAST =2179,
-  XED_IFORMFL_POPFQ_FIRST =2180, +  XED_IFORMFL_POPFD_FIRST =2180,
-  XED_IFORMFL_POPFQ_LAST =2180, +  XED_IFORMFL_POPFD_LAST =2180,
-  XED_IFORMFL_POPP_FIRST =2181, +  XED_IFORMFL_POPFQ_FIRST =2181,
-  XED_IFORMFL_POPP_LAST =2181, +  XED_IFORMFL_POPFQ_LAST =2181,
-  XED_IFORMFL_POR_FIRST =2182, +  XED_IFORMFL_POPP_FIRST =2182,
-  XED_IFORMFL_POR_LAST =2185, +  XED_IFORMFL_POPP_LAST =2182,
-  XED_IFORMFL_PREFETCHIT0_FIRST =2186, +  XED_IFORMFL_POR_FIRST =2183,
-  XED_IFORMFL_PREFETCHIT0_LAST =2186, +  XED_IFORMFL_POR_LAST =2186,
-  XED_IFORMFL_PREFETCHIT1_FIRST =2187, +  XED_IFORMFL_PREFETCHIT0_FIRST =2187,
-  XED_IFORMFL_PREFETCHIT1_LAST =2187, +  XED_IFORMFL_PREFETCHIT0_LAST =2187,
-  XED_IFORMFL_PREFETCHNTA_FIRST =2188, +  XED_IFORMFL_PREFETCHIT1_FIRST =2188,
-  XED_IFORMFL_PREFETCHNTA_LAST =2188, +  XED_IFORMFL_PREFETCHIT1_LAST =2188,
-  XED_IFORMFL_PREFETCHT0_FIRST =2189, +  XED_IFORMFL_PREFETCHNTA_FIRST =2189,
-  XED_IFORMFL_PREFETCHT0_LAST =2189, +  XED_IFORMFL_PREFETCHNTA_LAST =2189,
-  XED_IFORMFL_PREFETCHT1_FIRST =2190, +  XED_IFORMFL_PREFETCHRST2_FIRST =2190,
-  XED_IFORMFL_PREFETCHT1_LAST =2190, +  XED_IFORMFL_PREFETCHRST2_LAST =2190,
-  XED_IFORMFL_PREFETCHT2_FIRST =2191, +  XED_IFORMFL_PREFETCHT0_FIRST =2191,
-  XED_IFORMFL_PREFETCHT2_LAST =2191, +  XED_IFORMFL_PREFETCHT0_LAST =2191,
-  XED_IFORMFL_PREFETCHW_FIRST =2192, +  XED_IFORMFL_PREFETCHT1_FIRST =2192,
-  XED_IFORMFL_PREFETCHW_LAST =2193, +  XED_IFORMFL_PREFETCHT1_LAST =2192,
-  XED_IFORMFL_PREFETCHWT1_FIRST =2194, +  XED_IFORMFL_PREFETCHT2_FIRST =2193,
-  XED_IFORMFL_PREFETCHWT1_LAST =2194, +  XED_IFORMFL_PREFETCHT2_LAST =2193,
-  XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST =2195, +  XED_IFORMFL_PREFETCHW_FIRST =2194,
-  XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST =2195, +  XED_IFORMFL_PREFETCHW_LAST =2195,
-  XED_IFORMFL_PREFETCH_RESERVED_FIRST =2196, +  XED_IFORMFL_PREFETCHWT1_FIRST =2196,
-  XED_IFORMFL_PREFETCH_RESERVED_LAST =2199, +  XED_IFORMFL_PREFETCHWT1_LAST =2196,
-  XED_IFORMFL_PSADBW_FIRST =2200, +  XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST =2197,
-  XED_IFORMFL_PSADBW_LAST =2203, +  XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST =2197,
-  XED_IFORMFL_PSHUFB_FIRST =2204, +  XED_IFORMFL_PREFETCH_RESERVED_FIRST =2198,
-  XED_IFORMFL_PSHUFB_LAST =2207, +  XED_IFORMFL_PREFETCH_RESERVED_LAST =2201,
-  XED_IFORMFL_PSHUFD_FIRST =2208, +  XED_IFORMFL_PSADBW_FIRST =2202,
-  XED_IFORMFL_PSHUFD_LAST =2209, +  XED_IFORMFL_PSADBW_LAST =2205,
-  XED_IFORMFL_PSHUFHW_FIRST =2210, +  XED_IFORMFL_PSHUFB_FIRST =2206,
-  XED_IFORMFL_PSHUFHW_LAST =2211, +  XED_IFORMFL_PSHUFB_LAST =2209,
-  XED_IFORMFL_PSHUFLW_FIRST =2212, +  XED_IFORMFL_PSHUFD_FIRST =2210,
-  XED_IFORMFL_PSHUFLW_LAST =2213, +  XED_IFORMFL_PSHUFD_LAST =2211,
-  XED_IFORMFL_PSHUFW_FIRST =2214, +  XED_IFORMFL_PSHUFHW_FIRST =2212,
-  XED_IFORMFL_PSHUFW_LAST =2215, +  XED_IFORMFL_PSHUFHW_LAST =2213,
-  XED_IFORMFL_PSIGNB_FIRST =2216, +  XED_IFORMFL_PSHUFLW_FIRST =2214,
-  XED_IFORMFL_PSIGNB_LAST =2219, +  XED_IFORMFL_PSHUFLW_LAST =2215,
-  XED_IFORMFL_PSIGND_FIRST =2220, +  XED_IFORMFL_PSHUFW_FIRST =2216,
-  XED_IFORMFL_PSIGND_LAST =2223, +  XED_IFORMFL_PSHUFW_LAST =2217,
-  XED_IFORMFL_PSIGNW_FIRST =2224, +  XED_IFORMFL_PSIGNB_FIRST =2218,
-  XED_IFORMFL_PSIGNW_LAST =2227, +  XED_IFORMFL_PSIGNB_LAST =2221,
-  XED_IFORMFL_PSLLD_FIRST =2228, +  XED_IFORMFL_PSIGND_FIRST =2222,
-  XED_IFORMFL_PSLLD_LAST =2233, +  XED_IFORMFL_PSIGND_LAST =2225,
-  XED_IFORMFL_PSLLDQ_FIRST =2234, +  XED_IFORMFL_PSIGNW_FIRST =2226,
-  XED_IFORMFL_PSLLDQ_LAST =2234, +  XED_IFORMFL_PSIGNW_LAST =2229,
-  XED_IFORMFL_PSLLQ_FIRST =2235, +  XED_IFORMFL_PSLLD_FIRST =2230,
-  XED_IFORMFL_PSLLQ_LAST =2240, +  XED_IFORMFL_PSLLD_LAST =2235,
-  XED_IFORMFL_PSLLW_FIRST =2241, +  XED_IFORMFL_PSLLDQ_FIRST =2236,
-  XED_IFORMFL_PSLLW_LAST =2246, +  XED_IFORMFL_PSLLDQ_LAST =2236,
-  XED_IFORMFL_PSMASH_FIRST =2247, +  XED_IFORMFL_PSLLQ_FIRST =2237,
-  XED_IFORMFL_PSMASH_LAST =2247, +  XED_IFORMFL_PSLLQ_LAST =2242,
-  XED_IFORMFL_PSRAD_FIRST =2248, +  XED_IFORMFL_PSLLW_FIRST =2243,
-  XED_IFORMFL_PSRAD_LAST =2253, +  XED_IFORMFL_PSLLW_LAST =2248,
-  XED_IFORMFL_PSRAW_FIRST =2254, +  XED_IFORMFL_PSMASH_FIRST =2249,
-  XED_IFORMFL_PSRAW_LAST =2259, +  XED_IFORMFL_PSMASH_LAST =2249,
-  XED_IFORMFL_PSRLD_FIRST =2260, +  XED_IFORMFL_PSRAD_FIRST =2250,
-  XED_IFORMFL_PSRLD_LAST =2265, +  XED_IFORMFL_PSRAD_LAST =2255,
-  XED_IFORMFL_PSRLDQ_FIRST =2266, +  XED_IFORMFL_PSRAW_FIRST =2256,
-  XED_IFORMFL_PSRLDQ_LAST =2266, +  XED_IFORMFL_PSRAW_LAST =2261,
-  XED_IFORMFL_PSRLQ_FIRST =2267, +  XED_IFORMFL_PSRLD_FIRST =2262,
-  XED_IFORMFL_PSRLQ_LAST =2272, +  XED_IFORMFL_PSRLD_LAST =2267,
-  XED_IFORMFL_PSRLW_FIRST =2273, +  XED_IFORMFL_PSRLDQ_FIRST =2268,
-  XED_IFORMFL_PSRLW_LAST =2278, +  XED_IFORMFL_PSRLDQ_LAST =2268,
-  XED_IFORMFL_PSUBB_FIRST =2279, +  XED_IFORMFL_PSRLQ_FIRST =2269,
-  XED_IFORMFL_PSUBB_LAST =2282, +  XED_IFORMFL_PSRLQ_LAST =2274,
-  XED_IFORMFL_PSUBD_FIRST =2283, +  XED_IFORMFL_PSRLW_FIRST =2275,
-  XED_IFORMFL_PSUBD_LAST =2286, +  XED_IFORMFL_PSRLW_LAST =2280,
-  XED_IFORMFL_PSUBQ_FIRST =2287, +  XED_IFORMFL_PSUBB_FIRST =2281,
-  XED_IFORMFL_PSUBQ_LAST =2290, +  XED_IFORMFL_PSUBB_LAST =2284,
-  XED_IFORMFL_PSUBSB_FIRST =2291, +  XED_IFORMFL_PSUBD_FIRST =2285,
-  XED_IFORMFL_PSUBSB_LAST =2294, +  XED_IFORMFL_PSUBD_LAST =2288,
-  XED_IFORMFL_PSUBSW_FIRST =2295, +  XED_IFORMFL_PSUBQ_FIRST =2289,
-  XED_IFORMFL_PSUBSW_LAST =2298, +  XED_IFORMFL_PSUBQ_LAST =2292,
-  XED_IFORMFL_PSUBUSB_FIRST =2299, +  XED_IFORMFL_PSUBSB_FIRST =2293,
-  XED_IFORMFL_PSUBUSB_LAST =2302, +  XED_IFORMFL_PSUBSB_LAST =2296,
-  XED_IFORMFL_PSUBUSW_FIRST =2303, +  XED_IFORMFL_PSUBSW_FIRST =2297,
-  XED_IFORMFL_PSUBUSW_LAST =2306, +  XED_IFORMFL_PSUBSW_LAST =2300,
-  XED_IFORMFL_PSUBW_FIRST =2307, +  XED_IFORMFL_PSUBUSB_FIRST =2301,
-  XED_IFORMFL_PSUBW_LAST =2310, +  XED_IFORMFL_PSUBUSB_LAST =2304,
-  XED_IFORMFL_PSWAPD_FIRST =2311, +  XED_IFORMFL_PSUBUSW_FIRST =2305,
-  XED_IFORMFL_PSWAPD_LAST =2312, +  XED_IFORMFL_PSUBUSW_LAST =2308,
-  XED_IFORMFL_PTEST_FIRST =2313, +  XED_IFORMFL_PSUBW_FIRST =2309,
-  XED_IFORMFL_PTEST_LAST =2314, +  XED_IFORMFL_PSUBW_LAST =2312,
-  XED_IFORMFL_PTWRITE_FIRST =2315, +  XED_IFORMFL_PSWAPD_FIRST =2313,
-  XED_IFORMFL_PTWRITE_LAST =2316, +  XED_IFORMFL_PSWAPD_LAST =2314,
-  XED_IFORMFL_PUNPCKHBW_FIRST =2317, +  XED_IFORMFL_PTEST_FIRST =2315,
-  XED_IFORMFL_PUNPCKHBW_LAST =2320, +  XED_IFORMFL_PTEST_LAST =2316,
-  XED_IFORMFL_PUNPCKHDQ_FIRST =2321, +  XED_IFORMFL_PTWRITE_FIRST =2317,
-  XED_IFORMFL_PUNPCKHDQ_LAST =2324, +  XED_IFORMFL_PTWRITE_LAST =2318,
-  XED_IFORMFL_PUNPCKHQDQ_FIRST =2325, +  XED_IFORMFL_PUNPCKHBW_FIRST =2319,
-  XED_IFORMFL_PUNPCKHQDQ_LAST =2326, +  XED_IFORMFL_PUNPCKHBW_LAST =2322,
-  XED_IFORMFL_PUNPCKHWD_FIRST =2327, +  XED_IFORMFL_PUNPCKHDQ_FIRST =2323,
-  XED_IFORMFL_PUNPCKHWD_LAST =2330, +  XED_IFORMFL_PUNPCKHDQ_LAST =2326,
-  XED_IFORMFL_PUNPCKLBW_FIRST =2331, +  XED_IFORMFL_PUNPCKHQDQ_FIRST =2327,
-  XED_IFORMFL_PUNPCKLBW_LAST =2334, +  XED_IFORMFL_PUNPCKHQDQ_LAST =2328,
-  XED_IFORMFL_PUNPCKLDQ_FIRST =2335, +  XED_IFORMFL_PUNPCKHWD_FIRST =2329,
-  XED_IFORMFL_PUNPCKLDQ_LAST =2338, +  XED_IFORMFL_PUNPCKHWD_LAST =2332,
-  XED_IFORMFL_PUNPCKLQDQ_FIRST =2339, +  XED_IFORMFL_PUNPCKLBW_FIRST =2333,
-  XED_IFORMFL_PUNPCKLQDQ_LAST =2340, +  XED_IFORMFL_PUNPCKLBW_LAST =2336,
-  XED_IFORMFL_PUNPCKLWD_FIRST =2341, +  XED_IFORMFL_PUNPCKLDQ_FIRST =2337,
-  XED_IFORMFL_PUNPCKLWD_LAST =2344, +  XED_IFORMFL_PUNPCKLDQ_LAST =2340,
-  XED_IFORMFL_PUSH_FIRST =2345, +  XED_IFORMFL_PUNPCKLQDQ_FIRST =2341,
-  XED_IFORMFL_PUSH_LAST =2355, +  XED_IFORMFL_PUNPCKLQDQ_LAST =2342,
-  XED_IFORMFL_PUSH2_FIRST =2356, +  XED_IFORMFL_PUNPCKLWD_FIRST =2343,
-  XED_IFORMFL_PUSH2_LAST =2356, +  XED_IFORMFL_PUNPCKLWD_LAST =2346,
-  XED_IFORMFL_PUSH2P_FIRST =2357, +  XED_IFORMFL_PUSH_FIRST =2347,
-  XED_IFORMFL_PUSH2P_LAST =2357, +  XED_IFORMFL_PUSH_LAST =2357,
-  XED_IFORMFL_PUSHA_FIRST =2358, +  XED_IFORMFL_PUSH2_FIRST =2358,
-  XED_IFORMFL_PUSHA_LAST =2358, +  XED_IFORMFL_PUSH2_LAST =2358,
-  XED_IFORMFL_PUSHAD_FIRST =2359, +  XED_IFORMFL_PUSH2P_FIRST =2359,
-  XED_IFORMFL_PUSHAD_LAST =2359, +  XED_IFORMFL_PUSH2P_LAST =2359,
-  XED_IFORMFL_PUSHF_FIRST =2360, +  XED_IFORMFL_PUSHA_FIRST =2360,
-  XED_IFORMFL_PUSHF_LAST =2360, +  XED_IFORMFL_PUSHA_LAST =2360,
-  XED_IFORMFL_PUSHFD_FIRST =2361, +  XED_IFORMFL_PUSHAD_FIRST =2361,
-  XED_IFORMFL_PUSHFD_LAST =2361, +  XED_IFORMFL_PUSHAD_LAST =2361,
-  XED_IFORMFL_PUSHFQ_FIRST =2362, +  XED_IFORMFL_PUSHF_FIRST =2362,
-  XED_IFORMFL_PUSHFQ_LAST =2362, +  XED_IFORMFL_PUSHF_LAST =2362,
-  XED_IFORMFL_PUSHP_FIRST =2363, +  XED_IFORMFL_PUSHFD_FIRST =2363,
-  XED_IFORMFL_PUSHP_LAST =2363, +  XED_IFORMFL_PUSHFD_LAST =2363,
-  XED_IFORMFL_PVALIDATE_FIRST =2364, +  XED_IFORMFL_PUSHFQ_FIRST =2364,
-  XED_IFORMFL_PVALIDATE_LAST =2364, +  XED_IFORMFL_PUSHFQ_LAST =2364,
-  XED_IFORMFL_PXOR_FIRST =2365, +  XED_IFORMFL_PUSHP_FIRST =2365,
-  XED_IFORMFL_PXOR_LAST =2368, +  XED_IFORMFL_PUSHP_LAST =2365,
-  XED_IFORMFL_RCL_FIRST =2369, +  XED_IFORMFL_PVALIDATE_FIRST =2366,
-  XED_IFORMFL_RCL_LAST =2404, +  XED_IFORMFL_PVALIDATE_LAST =2366,
-  XED_IFORMFL_RCPPS_FIRST =2405, +  XED_IFORMFL_PXOR_FIRST =2367,
-  XED_IFORMFL_RCPPS_LAST =2406, +  XED_IFORMFL_PXOR_LAST =2370,
-  XED_IFORMFL_RCPSS_FIRST =2407, +  XED_IFORMFL_RCL_FIRST =2371,
-  XED_IFORMFL_RCPSS_LAST =2408, +  XED_IFORMFL_RCL_LAST =2406,
-  XED_IFORMFL_RCR_FIRST =2409, +  XED_IFORMFL_RCPPS_FIRST =2407,
-  XED_IFORMFL_RCR_LAST =2444, +  XED_IFORMFL_RCPPS_LAST =2408,
-  XED_IFORMFL_RDFSBASE_FIRST =2445, +  XED_IFORMFL_RCPSS_FIRST =2409,
-  XED_IFORMFL_RDFSBASE_LAST =2445, +  XED_IFORMFL_RCPSS_LAST =2410,
-  XED_IFORMFL_RDGSBASE_FIRST =2446, +  XED_IFORMFL_RCR_FIRST =2411,
-  XED_IFORMFL_RDGSBASE_LAST =2446, +  XED_IFORMFL_RCR_LAST =2446,
-  XED_IFORMFL_RDMSR_FIRST =2447, +  XED_IFORMFL_RDFSBASE_FIRST =2447,
-  XED_IFORMFL_RDMSR_LAST =2447, +  XED_IFORMFL_RDFSBASE_LAST =2447,
-  XED_IFORMFL_RDMSRLIST_FIRST =2448, +  XED_IFORMFL_RDGSBASE_FIRST =2448,
-  XED_IFORMFL_RDMSRLIST_LAST =2448, +  XED_IFORMFL_RDGSBASE_LAST =2448,
-  XED_IFORMFL_RDPID_FIRST =2449, +  XED_IFORMFL_RDMSR_FIRST =2449,
-  XED_IFORMFL_RDPID_LAST =2450, +  XED_IFORMFL_RDMSR_LAST =2451,
-  XED_IFORMFL_RDPKRU_FIRST =2451, +  XED_IFORMFL_RDMSRLIST_FIRST =2452,
-  XED_IFORMFL_RDPKRU_LAST =2451, +  XED_IFORMFL_RDMSRLIST_LAST =2452,
-  XED_IFORMFL_RDPMC_FIRST =2452, +  XED_IFORMFL_RDPID_FIRST =2453,
-  XED_IFORMFL_RDPMC_LAST =2452, +  XED_IFORMFL_RDPID_LAST =2454,
-  XED_IFORMFL_RDPRU_FIRST =2453, +  XED_IFORMFL_RDPKRU_FIRST =2455,
-  XED_IFORMFL_RDPRU_LAST =2453, +  XED_IFORMFL_RDPKRU_LAST =2455,
-  XED_IFORMFL_RDRAND_FIRST =2454, +  XED_IFORMFL_RDPMC_FIRST =2456,
-  XED_IFORMFL_RDRAND_LAST =2454, +  XED_IFORMFL_RDPMC_LAST =2456,
-  XED_IFORMFL_RDSEED_FIRST =2455, +  XED_IFORMFL_RDPRU_FIRST =2457,
-  XED_IFORMFL_RDSEED_LAST =2455, +  XED_IFORMFL_RDPRU_LAST =2457,
-  XED_IFORMFL_RDSSPD_FIRST =2456, +  XED_IFORMFL_RDRAND_FIRST =2458,
-  XED_IFORMFL_RDSSPD_LAST =2456, +  XED_IFORMFL_RDRAND_LAST =2458,
-  XED_IFORMFL_RDSSPQ_FIRST =2457, +  XED_IFORMFL_RDSEED_FIRST =2459,
-  XED_IFORMFL_RDSSPQ_LAST =2457, +  XED_IFORMFL_RDSEED_LAST =2459,
-  XED_IFORMFL_RDTSC_FIRST =2458, +  XED_IFORMFL_RDSSPD_FIRST =2460,
-  XED_IFORMFL_RDTSC_LAST =2458, +  XED_IFORMFL_RDSSPD_LAST =2460,
-  XED_IFORMFL_RDTSCP_FIRST =2459, +  XED_IFORMFL_RDSSPQ_FIRST =2461,
-  XED_IFORMFL_RDTSCP_LAST =2459, +  XED_IFORMFL_RDSSPQ_LAST =2461,
-  XED_IFORMFL_REPE_CMPSB_FIRST =2460, +  XED_IFORMFL_RDTSC_FIRST =2462,
-  XED_IFORMFL_REPE_CMPSB_LAST =2460, +  XED_IFORMFL_RDTSC_LAST =2462,
-  XED_IFORMFL_REPE_CMPSD_FIRST =2461, +  XED_IFORMFL_RDTSCP_FIRST =2463,
-  XED_IFORMFL_REPE_CMPSD_LAST =2461, +  XED_IFORMFL_RDTSCP_LAST =2463,
-  XED_IFORMFL_REPE_CMPSQ_FIRST =2462, +  XED_IFORMFL_REPE_CMPSB_FIRST =2464,
-  XED_IFORMFL_REPE_CMPSQ_LAST =2462, +  XED_IFORMFL_REPE_CMPSB_LAST =2464,
-  XED_IFORMFL_REPE_CMPSW_FIRST =2463, +  XED_IFORMFL_REPE_CMPSD_FIRST =2465,
-  XED_IFORMFL_REPE_CMPSW_LAST =2463, +  XED_IFORMFL_REPE_CMPSD_LAST =2465,
-  XED_IFORMFL_REPE_SCASB_FIRST =2464, +  XED_IFORMFL_REPE_CMPSQ_FIRST =2466,
-  XED_IFORMFL_REPE_SCASB_LAST =2464, +  XED_IFORMFL_REPE_CMPSQ_LAST =2466,
-  XED_IFORMFL_REPE_SCASD_FIRST =2465, +  XED_IFORMFL_REPE_CMPSW_FIRST =2467,
-  XED_IFORMFL_REPE_SCASD_LAST =2465, +  XED_IFORMFL_REPE_CMPSW_LAST =2467,
-  XED_IFORMFL_REPE_SCASQ_FIRST =2466, +  XED_IFORMFL_REPE_SCASB_FIRST =2468,
-  XED_IFORMFL_REPE_SCASQ_LAST =2466, +  XED_IFORMFL_REPE_SCASB_LAST =2468,
-  XED_IFORMFL_REPE_SCASW_FIRST =2467, +  XED_IFORMFL_REPE_SCASD_FIRST =2469,
-  XED_IFORMFL_REPE_SCASW_LAST =2467, +  XED_IFORMFL_REPE_SCASD_LAST =2469,
-  XED_IFORMFL_REPNE_CMPSB_FIRST =2468, +  XED_IFORMFL_REPE_SCASQ_FIRST =2470,
-  XED_IFORMFL_REPNE_CMPSB_LAST =2468, +  XED_IFORMFL_REPE_SCASQ_LAST =2470,
-  XED_IFORMFL_REPNE_CMPSD_FIRST =2469, +  XED_IFORMFL_REPE_SCASW_FIRST =2471,
-  XED_IFORMFL_REPNE_CMPSD_LAST =2469, +  XED_IFORMFL_REPE_SCASW_LAST =2471,
-  XED_IFORMFL_REPNE_CMPSQ_FIRST =2470, +  XED_IFORMFL_REPNE_CMPSB_FIRST =2472,
-  XED_IFORMFL_REPNE_CMPSQ_LAST =2470, +  XED_IFORMFL_REPNE_CMPSB_LAST =2472,
-  XED_IFORMFL_REPNE_CMPSW_FIRST =2471, +  XED_IFORMFL_REPNE_CMPSD_FIRST =2473,
-  XED_IFORMFL_REPNE_CMPSW_LAST =2471, +  XED_IFORMFL_REPNE_CMPSD_LAST =2473,
-  XED_IFORMFL_REPNE_SCASB_FIRST =2472, +  XED_IFORMFL_REPNE_CMPSQ_FIRST =2474,
-  XED_IFORMFL_REPNE_SCASB_LAST =2472, +  XED_IFORMFL_REPNE_CMPSQ_LAST =2474,
-  XED_IFORMFL_REPNE_SCASD_FIRST =2473, +  XED_IFORMFL_REPNE_CMPSW_FIRST =2475,
-  XED_IFORMFL_REPNE_SCASD_LAST =2473, +  XED_IFORMFL_REPNE_CMPSW_LAST =2475,
-  XED_IFORMFL_REPNE_SCASQ_FIRST =2474, +  XED_IFORMFL_REPNE_SCASB_FIRST =2476,
-  XED_IFORMFL_REPNE_SCASQ_LAST =2474, +  XED_IFORMFL_REPNE_SCASB_LAST =2476,
-  XED_IFORMFL_REPNE_SCASW_FIRST =2475, +  XED_IFORMFL_REPNE_SCASD_FIRST =2477,
-  XED_IFORMFL_REPNE_SCASW_LAST =2475, +  XED_IFORMFL_REPNE_SCASD_LAST =2477,
-  XED_IFORMFL_REP_INSB_FIRST =2476, +  XED_IFORMFL_REPNE_SCASQ_FIRST =2478,
-  XED_IFORMFL_REP_INSB_LAST =2476, +  XED_IFORMFL_REPNE_SCASQ_LAST =2478,
-  XED_IFORMFL_REP_INSD_FIRST =2477, +  XED_IFORMFL_REPNE_SCASW_FIRST =2479,
-  XED_IFORMFL_REP_INSD_LAST =2477, +  XED_IFORMFL_REPNE_SCASW_LAST =2479,
-  XED_IFORMFL_REP_INSW_FIRST =2478, +  XED_IFORMFL_REP_INSB_FIRST =2480,
-  XED_IFORMFL_REP_INSW_LAST =2478, +  XED_IFORMFL_REP_INSB_LAST =2480,
-  XED_IFORMFL_REP_LODSB_FIRST =2479, +  XED_IFORMFL_REP_INSD_FIRST =2481,
-  XED_IFORMFL_REP_LODSB_LAST =2479, +  XED_IFORMFL_REP_INSD_LAST =2481,
-  XED_IFORMFL_REP_LODSD_FIRST =2480, +  XED_IFORMFL_REP_INSW_FIRST =2482,
-  XED_IFORMFL_REP_LODSD_LAST =2480, +  XED_IFORMFL_REP_INSW_LAST =2482,
-  XED_IFORMFL_REP_LODSQ_FIRST =2481, +  XED_IFORMFL_REP_LODSB_FIRST =2483,
-  XED_IFORMFL_REP_LODSQ_LAST =2481, +  XED_IFORMFL_REP_LODSB_LAST =2483,
-  XED_IFORMFL_REP_LODSW_FIRST =2482, +  XED_IFORMFL_REP_LODSD_FIRST =2484,
-  XED_IFORMFL_REP_LODSW_LAST =2482, +  XED_IFORMFL_REP_LODSD_LAST =2484,
-  XED_IFORMFL_REP_MONTMUL_FIRST =2483, +  XED_IFORMFL_REP_LODSQ_FIRST =2485,
-  XED_IFORMFL_REP_MONTMUL_LAST =2483, +  XED_IFORMFL_REP_LODSQ_LAST =2485,
-  XED_IFORMFL_REP_MOVSB_FIRST =2484, +  XED_IFORMFL_REP_LODSW_FIRST =2486,
-  XED_IFORMFL_REP_MOVSB_LAST =2484, +  XED_IFORMFL_REP_LODSW_LAST =2486,
-  XED_IFORMFL_REP_MOVSD_FIRST =2485, +  XED_IFORMFL_REP_MONTMUL_FIRST =2487,
-  XED_IFORMFL_REP_MOVSD_LAST =2485, +  XED_IFORMFL_REP_MONTMUL_LAST =2487,
-  XED_IFORMFL_REP_MOVSQ_FIRST =2486, +  XED_IFORMFL_REP_MOVSB_FIRST =2488,
-  XED_IFORMFL_REP_MOVSQ_LAST =2486, +  XED_IFORMFL_REP_MOVSB_LAST =2488,
-  XED_IFORMFL_REP_MOVSW_FIRST =2487, +  XED_IFORMFL_REP_MOVSD_FIRST =2489,
-  XED_IFORMFL_REP_MOVSW_LAST =2487, +  XED_IFORMFL_REP_MOVSD_LAST =2489,
-  XED_IFORMFL_REP_OUTSB_FIRST =2488, +  XED_IFORMFL_REP_MOVSQ_FIRST =2490,
-  XED_IFORMFL_REP_OUTSB_LAST =2488, +  XED_IFORMFL_REP_MOVSQ_LAST =2490,
-  XED_IFORMFL_REP_OUTSD_FIRST =2489, +  XED_IFORMFL_REP_MOVSW_FIRST =2491,
-  XED_IFORMFL_REP_OUTSD_LAST =2489, +  XED_IFORMFL_REP_MOVSW_LAST =2491,
-  XED_IFORMFL_REP_OUTSW_FIRST =2490, +  XED_IFORMFL_REP_OUTSB_FIRST =2492,
-  XED_IFORMFL_REP_OUTSW_LAST =2490, +  XED_IFORMFL_REP_OUTSB_LAST =2492,
-  XED_IFORMFL_REP_STOSB_FIRST =2491, +  XED_IFORMFL_REP_OUTSD_FIRST =2493,
-  XED_IFORMFL_REP_STOSB_LAST =2491, +  XED_IFORMFL_REP_OUTSD_LAST =2493,
-  XED_IFORMFL_REP_STOSD_FIRST =2492, +  XED_IFORMFL_REP_OUTSW_FIRST =2494,
-  XED_IFORMFL_REP_STOSD_LAST =2492, +  XED_IFORMFL_REP_OUTSW_LAST =2494,
-  XED_IFORMFL_REP_STOSQ_FIRST =2493, +  XED_IFORMFL_REP_STOSB_FIRST =2495,
-  XED_IFORMFL_REP_STOSQ_LAST =2493, +  XED_IFORMFL_REP_STOSB_LAST =2495,
-  XED_IFORMFL_REP_STOSW_FIRST =2494, +  XED_IFORMFL_REP_STOSD_FIRST =2496,
-  XED_IFORMFL_REP_STOSW_LAST =2494, +  XED_IFORMFL_REP_STOSD_LAST =2496,
-  XED_IFORMFL_REP_XCRYPTCBC_FIRST =2495, +  XED_IFORMFL_REP_STOSQ_FIRST =2497,
-  XED_IFORMFL_REP_XCRYPTCBC_LAST =2495, +  XED_IFORMFL_REP_STOSQ_LAST =2497,
-  XED_IFORMFL_REP_XCRYPTCFB_FIRST =2496, +  XED_IFORMFL_REP_STOSW_FIRST =2498,
-  XED_IFORMFL_REP_XCRYPTCFB_LAST =2496, +  XED_IFORMFL_REP_STOSW_LAST =2498,
-  XED_IFORMFL_REP_XCRYPTCTR_FIRST =2497, +  XED_IFORMFL_REP_XCRYPTCBC_FIRST =2499,
-  XED_IFORMFL_REP_XCRYPTCTR_LAST =2497, +  XED_IFORMFL_REP_XCRYPTCBC_LAST =2499,
-  XED_IFORMFL_REP_XCRYPTECB_FIRST =2498, +  XED_IFORMFL_REP_XCRYPTCFB_FIRST =2500,
-  XED_IFORMFL_REP_XCRYPTECB_LAST =2498, +  XED_IFORMFL_REP_XCRYPTCFB_LAST =2500,
-  XED_IFORMFL_REP_XCRYPTOFB_FIRST =2499, +  XED_IFORMFL_REP_XCRYPTCTR_FIRST =2501,
-  XED_IFORMFL_REP_XCRYPTOFB_LAST =2499, +  XED_IFORMFL_REP_XCRYPTCTR_LAST =2501,
-  XED_IFORMFL_REP_XSHA1_FIRST =2500, +  XED_IFORMFL_REP_XCRYPTECB_FIRST =2502,
-  XED_IFORMFL_REP_XSHA1_LAST =2500, +  XED_IFORMFL_REP_XCRYPTECB_LAST =2502,
-  XED_IFORMFL_REP_XSHA256_FIRST =2501, +  XED_IFORMFL_REP_XCRYPTOFB_FIRST =2503,
-  XED_IFORMFL_REP_XSHA256_LAST =2501, +  XED_IFORMFL_REP_XCRYPTOFB_LAST =2503,
-  XED_IFORMFL_REP_XSTORE_FIRST =2502, +  XED_IFORMFL_REP_XSHA1_FIRST =2504,
-  XED_IFORMFL_REP_XSTORE_LAST =2502, +  XED_IFORMFL_REP_XSHA1_LAST =2504,
-  XED_IFORMFL_RET_FAR_FIRST =2503, +  XED_IFORMFL_REP_XSHA256_FIRST =2505,
-  XED_IFORMFL_RET_FAR_LAST =2504, +  XED_IFORMFL_REP_XSHA256_LAST =2505,
-  XED_IFORMFL_RET_NEAR_FIRST =2505, +  XED_IFORMFL_REP_XSTORE_FIRST =2506,
-  XED_IFORMFL_RET_NEAR_LAST =2506, +  XED_IFORMFL_REP_XSTORE_LAST =2506,
-  XED_IFORMFL_RMPADJUST_FIRST =2507, +  XED_IFORMFL_RET_FAR_FIRST =2507,
-  XED_IFORMFL_RMPADJUST_LAST =2507, +  XED_IFORMFL_RET_FAR_LAST =2508,
-  XED_IFORMFL_RMPUPDATE_FIRST =2508, +  XED_IFORMFL_RET_NEAR_FIRST =2509,
-  XED_IFORMFL_RMPUPDATE_LAST =2508, +  XED_IFORMFL_RET_NEAR_LAST =2510,
-  XED_IFORMFL_ROL_FIRST =2509, +  XED_IFORMFL_RMPADJUST_FIRST =2511,
-  XED_IFORMFL_ROL_LAST =2544, +  XED_IFORMFL_RMPADJUST_LAST =2511,
-  XED_IFORMFL_ROR_FIRST =2545, +  XED_IFORMFL_RMPUPDATE_FIRST =2512,
-  XED_IFORMFL_ROR_LAST =2580, +  XED_IFORMFL_RMPUPDATE_LAST =2512,
-  XED_IFORMFL_RORX_FIRST =2581, +  XED_IFORMFL_ROL_FIRST =2513,
-  XED_IFORMFL_RORX_LAST =2588, +  XED_IFORMFL_ROL_LAST =2548,
-  XED_IFORMFL_ROUNDPD_FIRST =2589, +  XED_IFORMFL_ROR_FIRST =2549,
-  XED_IFORMFL_ROUNDPD_LAST =2590, +  XED_IFORMFL_ROR_LAST =2584,
-  XED_IFORMFL_ROUNDPS_FIRST =2591, +  XED_IFORMFL_RORX_FIRST =2585,
-  XED_IFORMFL_ROUNDPS_LAST =2592, +  XED_IFORMFL_RORX_LAST =2592,
-  XED_IFORMFL_ROUNDSD_FIRST =2593, +  XED_IFORMFL_ROUNDPD_FIRST =2593,
-  XED_IFORMFL_ROUNDSD_LAST =2594, +  XED_IFORMFL_ROUNDPD_LAST =2594,
-  XED_IFORMFL_ROUNDSS_FIRST =2595, +  XED_IFORMFL_ROUNDPS_FIRST =2595,
-  XED_IFORMFL_ROUNDSS_LAST =2596, +  XED_IFORMFL_ROUNDPS_LAST =2596,
-  XED_IFORMFL_RSM_FIRST =2597, +  XED_IFORMFL_ROUNDSD_FIRST =2597,
-  XED_IFORMFL_RSM_LAST =2597, +  XED_IFORMFL_ROUNDSD_LAST =2598,
-  XED_IFORMFL_RSQRTPS_FIRST =2598, +  XED_IFORMFL_ROUNDSS_FIRST =2599,
-  XED_IFORMFL_RSQRTPS_LAST =2599, +  XED_IFORMFL_ROUNDSS_LAST =2600,
-  XED_IFORMFL_RSQRTSS_FIRST =2600, +  XED_IFORMFL_RSM_FIRST =2601,
-  XED_IFORMFL_RSQRTSS_LAST =2601, +  XED_IFORMFL_RSM_LAST =2601,
-  XED_IFORMFL_RSTORSSP_FIRST =2602, +  XED_IFORMFL_RSQRTPS_FIRST =2602,
-  XED_IFORMFL_RSTORSSP_LAST =2602, +  XED_IFORMFL_RSQRTPS_LAST =2603,
-  XED_IFORMFL_SAHF_FIRST =2603, +  XED_IFORMFL_RSQRTSS_FIRST =2604,
-  XED_IFORMFL_SAHF_LAST =2603, +  XED_IFORMFL_RSQRTSS_LAST =2605,
-  XED_IFORMFL_SALC_FIRST =2604, +  XED_IFORMFL_RSTORSSP_FIRST =2606,
-  XED_IFORMFL_SALC_LAST =2604, +  XED_IFORMFL_RSTORSSP_LAST =2606,
-  XED_IFORMFL_SAR_FIRST =2605, +  XED_IFORMFL_SAHF_FIRST =2607,
-  XED_IFORMFL_SAR_LAST =2640, +  XED_IFORMFL_SAHF_LAST =2607,
-  XED_IFORMFL_SARX_FIRST =2641, +  XED_IFORMFL_SALC_FIRST =2608,
-  XED_IFORMFL_SARX_LAST =2648, +  XED_IFORMFL_SALC_LAST =2608,
-  XED_IFORMFL_SAVEPREVSSP_FIRST =2649, +  XED_IFORMFL_SAR_FIRST =2609,
-  XED_IFORMFL_SAVEPREVSSP_LAST =2649, +  XED_IFORMFL_SAR_LAST =2644,
-  XED_IFORMFL_SBB_FIRST =2650, +  XED_IFORMFL_SARX_FIRST =2645,
-  XED_IFORMFL_SBB_LAST =2691, +  XED_IFORMFL_SARX_LAST =2652,
-  XED_IFORMFL_SBB_LOCK_FIRST =2692, +  XED_IFORMFL_SAVEPREVSSP_FIRST =2653,
-  XED_IFORMFL_SBB_LOCK_LAST =2697, +  XED_IFORMFL_SAVEPREVSSP_LAST =2653,
-  XED_IFORMFL_SCASB_FIRST =2698, +  XED_IFORMFL_SBB_FIRST =2654,
-  XED_IFORMFL_SCASB_LAST =2698, +  XED_IFORMFL_SBB_LAST =2695,
-  XED_IFORMFL_SCASD_FIRST =2699, +  XED_IFORMFL_SBB_LOCK_FIRST =2696,
-  XED_IFORMFL_SCASD_LAST =2699, +  XED_IFORMFL_SBB_LOCK_LAST =2701,
-  XED_IFORMFL_SCASQ_FIRST =2700, +  XED_IFORMFL_SCASB_FIRST =2702,
-  XED_IFORMFL_SCASQ_LAST =2700, +  XED_IFORMFL_SCASB_LAST =2702,
-  XED_IFORMFL_SCASW_FIRST =2701, +  XED_IFORMFL_SCASD_FIRST =2703,
-  XED_IFORMFL_SCASW_LAST =2701, +  XED_IFORMFL_SCASD_LAST =2703,
-  XED_IFORMFL_SEAMCALL_FIRST =2702, +  XED_IFORMFL_SCASQ_FIRST =2704,
-  XED_IFORMFL_SEAMCALL_LAST =2702, +  XED_IFORMFL_SCASQ_LAST =2704,
-  XED_IFORMFL_SEAMOPS_FIRST =2703, +  XED_IFORMFL_SCASW_FIRST =2705,
-  XED_IFORMFL_SEAMOPS_LAST =2703, +  XED_IFORMFL_SCASW_LAST =2705,
-  XED_IFORMFL_SEAMRET_FIRST =2704, +  XED_IFORMFL_SEAMCALL_FIRST =2706,
-  XED_IFORMFL_SEAMRET_LAST =2704, +  XED_IFORMFL_SEAMCALL_LAST =2706,
-  XED_IFORMFL_SENDUIPI_FIRST =2705, +  XED_IFORMFL_SEAMOPS_FIRST =2707,
-  XED_IFORMFL_SENDUIPI_LAST =2705, +  XED_IFORMFL_SEAMOPS_LAST =2707,
-  XED_IFORMFL_SERIALIZE_FIRST =2706, +  XED_IFORMFL_SEAMRET_FIRST =2708,
-  XED_IFORMFL_SERIALIZE_LAST =2706, +  XED_IFORMFL_SEAMRET_LAST =2708,
-  XED_IFORMFL_SETB_FIRST =2707, +  XED_IFORMFL_SENDUIPI_FIRST =2709,
-  XED_IFORMFL_SETB_LAST =2712, +  XED_IFORMFL_SENDUIPI_LAST =2709,
-  XED_IFORMFL_SETBE_FIRST =2713, +  XED_IFORMFL_SERIALIZE_FIRST =2710,
-  XED_IFORMFL_SETBE_LAST =2718, +  XED_IFORMFL_SERIALIZE_LAST =2710,
-  XED_IFORMFL_SETL_FIRST =2719, +  XED_IFORMFL_SETB_FIRST =2711,
-  XED_IFORMFL_SETL_LAST =2724, +  XED_IFORMFL_SETB_LAST =2716,
-  XED_IFORMFL_SETLE_FIRST =2725, +  XED_IFORMFL_SETBE_FIRST =2717,
-  XED_IFORMFL_SETLE_LAST =2730, +  XED_IFORMFL_SETBE_LAST =2722,
-  XED_IFORMFL_SETNB_FIRST =2731, +  XED_IFORMFL_SETL_FIRST =2723,
-  XED_IFORMFL_SETNB_LAST =2736, +  XED_IFORMFL_SETL_LAST =2728,
-  XED_IFORMFL_SETNBE_FIRST =2737, +  XED_IFORMFL_SETLE_FIRST =2729,
-  XED_IFORMFL_SETNBE_LAST =2742, +  XED_IFORMFL_SETLE_LAST =2734,
-  XED_IFORMFL_SETNL_FIRST =2743, +  XED_IFORMFL_SETNB_FIRST =2735,
-  XED_IFORMFL_SETNL_LAST =2748, +  XED_IFORMFL_SETNB_LAST =2740,
-  XED_IFORMFL_SETNLE_FIRST =2749, +  XED_IFORMFL_SETNBE_FIRST =2741,
-  XED_IFORMFL_SETNLE_LAST =2754, +  XED_IFORMFL_SETNBE_LAST =2746,
-  XED_IFORMFL_SETNO_FIRST =2755, +  XED_IFORMFL_SETNL_FIRST =2747,
-  XED_IFORMFL_SETNO_LAST =2760, +  XED_IFORMFL_SETNL_LAST =2752,
-  XED_IFORMFL_SETNP_FIRST =2761, +  XED_IFORMFL_SETNLE_FIRST =2753,
-  XED_IFORMFL_SETNP_LAST =2766, +  XED_IFORMFL_SETNLE_LAST =2758,
-  XED_IFORMFL_SETNS_FIRST =2767, +  XED_IFORMFL_SETNO_FIRST =2759,
-  XED_IFORMFL_SETNS_LAST =2772, +  XED_IFORMFL_SETNO_LAST =2764,
-  XED_IFORMFL_SETNZ_FIRST =2773, +  XED_IFORMFL_SETNP_FIRST =2765,
-  XED_IFORMFL_SETNZ_LAST =2778, +  XED_IFORMFL_SETNP_LAST =2770,
-  XED_IFORMFL_SETO_FIRST =2779, +  XED_IFORMFL_SETNS_FIRST =2771,
-  XED_IFORMFL_SETO_LAST =2784, +  XED_IFORMFL_SETNS_LAST =2776,
-  XED_IFORMFL_SETP_FIRST =2785, +  XED_IFORMFL_SETNZ_FIRST =2777,
-  XED_IFORMFL_SETP_LAST =2790, +  XED_IFORMFL_SETNZ_LAST =2782,
-  XED_IFORMFL_SETS_FIRST =2791, +  XED_IFORMFL_SETO_FIRST =2783,
-  XED_IFORMFL_SETS_LAST =2796, +  XED_IFORMFL_SETO_LAST =2788,
-  XED_IFORMFL_SETSSBSY_FIRST =2797, +  XED_IFORMFL_SETP_FIRST =2789,
-  XED_IFORMFL_SETSSBSY_LAST =2797, +  XED_IFORMFL_SETP_LAST =2794,
-  XED_IFORMFL_SETZ_FIRST =2798, +  XED_IFORMFL_SETS_FIRST =2795,
-  XED_IFORMFL_SETZ_LAST =2803, +  XED_IFORMFL_SETS_LAST =2800,
-  XED_IFORMFL_SFENCE_FIRST =2804, +  XED_IFORMFL_SETSSBSY_FIRST =2801,
-  XED_IFORMFL_SFENCE_LAST =2804, +  XED_IFORMFL_SETSSBSY_LAST =2801,
-  XED_IFORMFL_SGDT_FIRST =2805, +  XED_IFORMFL_SETZ_FIRST =2802,
-  XED_IFORMFL_SGDT_LAST =2806, +  XED_IFORMFL_SETZ_LAST =2807,
-  XED_IFORMFL_SHA1MSG1_FIRST =2807, +  XED_IFORMFL_SFENCE_FIRST =2808,
-  XED_IFORMFL_SHA1MSG1_LAST =2808, +  XED_IFORMFL_SFENCE_LAST =2808,
-  XED_IFORMFL_SHA1MSG2_FIRST =2809, +  XED_IFORMFL_SGDT_FIRST =2809,
-  XED_IFORMFL_SHA1MSG2_LAST =2810, +  XED_IFORMFL_SGDT_LAST =2810,
-  XED_IFORMFL_SHA1NEXTE_FIRST =2811, +  XED_IFORMFL_SHA1MSG1_FIRST =2811,
-  XED_IFORMFL_SHA1NEXTE_LAST =2812, +  XED_IFORMFL_SHA1MSG1_LAST =2812,
-  XED_IFORMFL_SHA1RNDS4_FIRST =2813, +  XED_IFORMFL_SHA1MSG2_FIRST =2813,
-  XED_IFORMFL_SHA1RNDS4_LAST =2814, +  XED_IFORMFL_SHA1MSG2_LAST =2814,
-  XED_IFORMFL_SHA256MSG1_FIRST =2815, +  XED_IFORMFL_SHA1NEXTE_FIRST =2815,
-  XED_IFORMFL_SHA256MSG1_LAST =2816, +  XED_IFORMFL_SHA1NEXTE_LAST =2816,
-  XED_IFORMFL_SHA256MSG2_FIRST =2817, +  XED_IFORMFL_SHA1RNDS4_FIRST =2817,
-  XED_IFORMFL_SHA256MSG2_LAST =2818, +  XED_IFORMFL_SHA1RNDS4_LAST =2818,
-  XED_IFORMFL_SHA256RNDS2_FIRST =2819, +  XED_IFORMFL_SHA256MSG1_FIRST =2819,
-  XED_IFORMFL_SHA256RNDS2_LAST =2820, +  XED_IFORMFL_SHA256MSG1_LAST =2820,
-  XED_IFORMFL_SHL_FIRST =2821, +  XED_IFORMFL_SHA256MSG2_FIRST =2821,
-  XED_IFORMFL_SHL_LAST =2868, +  XED_IFORMFL_SHA256MSG2_LAST =2822,
-  XED_IFORMFL_SHLD_FIRST =2869, +  XED_IFORMFL_SHA256RNDS2_FIRST =2823,
-  XED_IFORMFL_SHLD_LAST =2880, +  XED_IFORMFL_SHA256RNDS2_LAST =2824,
-  XED_IFORMFL_SHLX_FIRST =2881, +  XED_IFORMFL_SHL_FIRST =2825,
-  XED_IFORMFL_SHLX_LAST =2888, +  XED_IFORMFL_SHL_LAST =2872,
-  XED_IFORMFL_SHR_FIRST =2889, +  XED_IFORMFL_SHLD_FIRST =2873,
-  XED_IFORMFL_SHR_LAST =2924, +  XED_IFORMFL_SHLD_LAST =2884,
-  XED_IFORMFL_SHRD_FIRST =2925, +  XED_IFORMFL_SHLX_FIRST =2885,
-  XED_IFORMFL_SHRD_LAST =2936, +  XED_IFORMFL_SHLX_LAST =2892,
-  XED_IFORMFL_SHRX_FIRST =2937, +  XED_IFORMFL_SHR_FIRST =2893,
-  XED_IFORMFL_SHRX_LAST =2944, +  XED_IFORMFL_SHR_LAST =2928,
-  XED_IFORMFL_SHUFPD_FIRST =2945, +  XED_IFORMFL_SHRD_FIRST =2929,
-  XED_IFORMFL_SHUFPD_LAST =2946, +  XED_IFORMFL_SHRD_LAST =2940,
-  XED_IFORMFL_SHUFPS_FIRST =2947, +  XED_IFORMFL_SHRX_FIRST =2941,
-  XED_IFORMFL_SHUFPS_LAST =2948, +  XED_IFORMFL_SHRX_LAST =2948,
-  XED_IFORMFL_SIDT_FIRST =2949, +  XED_IFORMFL_SHUFPD_FIRST =2949,
-  XED_IFORMFL_SIDT_LAST =2950, +  XED_IFORMFL_SHUFPD_LAST =2950,
-  XED_IFORMFL_SKINIT_FIRST =2951, +  XED_IFORMFL_SHUFPS_FIRST =2951,
-  XED_IFORMFL_SKINIT_LAST =2951, +  XED_IFORMFL_SHUFPS_LAST =2952,
-  XED_IFORMFL_SLDT_FIRST =2952, +  XED_IFORMFL_SIDT_FIRST =2953,
-  XED_IFORMFL_SLDT_LAST =2953, +  XED_IFORMFL_SIDT_LAST =2954,
-  XED_IFORMFL_SLWPCB_FIRST =2954, +  XED_IFORMFL_SKINIT_FIRST =2955,
-  XED_IFORMFL_SLWPCB_LAST =2954, +  XED_IFORMFL_SKINIT_LAST =2955,
-  XED_IFORMFL_SMSW_FIRST =2955, +  XED_IFORMFL_SLDT_FIRST =2956,
-  XED_IFORMFL_SMSW_LAST =2956, +  XED_IFORMFL_SLDT_LAST =2957,
-  XED_IFORMFL_SQRTPD_FIRST =2957, +  XED_IFORMFL_SLWPCB_FIRST =2958,
-  XED_IFORMFL_SQRTPD_LAST =2958, +  XED_IFORMFL_SLWPCB_LAST =2958,
-  XED_IFORMFL_SQRTPS_FIRST =2959, +  XED_IFORMFL_SMSW_FIRST =2959,
-  XED_IFORMFL_SQRTPS_LAST =2960, +  XED_IFORMFL_SMSW_LAST =2960,
-  XED_IFORMFL_SQRTSD_FIRST =2961, +  XED_IFORMFL_SQRTPD_FIRST =2961,
-  XED_IFORMFL_SQRTSD_LAST =2962, +  XED_IFORMFL_SQRTPD_LAST =2962,
-  XED_IFORMFL_SQRTSS_FIRST =2963, +  XED_IFORMFL_SQRTPS_FIRST =2963,
-  XED_IFORMFL_SQRTSS_LAST =2964, +  XED_IFORMFL_SQRTPS_LAST =2964,
-  XED_IFORMFL_STAC_FIRST =2965, +  XED_IFORMFL_SQRTSD_FIRST =2965,
-  XED_IFORMFL_STAC_LAST =2965, +  XED_IFORMFL_SQRTSD_LAST =2966,
-  XED_IFORMFL_STC_FIRST =2966, +  XED_IFORMFL_SQRTSS_FIRST =2967,
-  XED_IFORMFL_STC_LAST =2966, +  XED_IFORMFL_SQRTSS_LAST =2968,
-  XED_IFORMFL_STD_FIRST =2967, +  XED_IFORMFL_STAC_FIRST =2969,
-  XED_IFORMFL_STD_LAST =2967, +  XED_IFORMFL_STAC_LAST =2969,
-  XED_IFORMFL_STGI_FIRST =2968, +  XED_IFORMFL_STC_FIRST =2970,
-  XED_IFORMFL_STGI_LAST =2968, +  XED_IFORMFL_STC_LAST =2970,
-  XED_IFORMFL_STI_FIRST =2969, +  XED_IFORMFL_STD_FIRST =2971,
-  XED_IFORMFL_STI_LAST =2969, +  XED_IFORMFL_STD_LAST =2971,
-  XED_IFORMFL_STMXCSR_FIRST =2970, +  XED_IFORMFL_STGI_FIRST =2972,
-  XED_IFORMFL_STMXCSR_LAST =2970, +  XED_IFORMFL_STGI_LAST =2972,
-  XED_IFORMFL_STOSB_FIRST =2971, +  XED_IFORMFL_STI_FIRST =2973,
-  XED_IFORMFL_STOSB_LAST =2971, +  XED_IFORMFL_STI_LAST =2973,
-  XED_IFORMFL_STOSD_FIRST =2972, +  XED_IFORMFL_STMXCSR_FIRST =2974,
-  XED_IFORMFL_STOSD_LAST =2972, +  XED_IFORMFL_STMXCSR_LAST =2974,
-  XED_IFORMFL_STOSQ_FIRST =2973, +  XED_IFORMFL_STOSB_FIRST =2975,
-  XED_IFORMFL_STOSQ_LAST =2973, +  XED_IFORMFL_STOSB_LAST =2975,
-  XED_IFORMFL_STOSW_FIRST =2974, +  XED_IFORMFL_STOSD_FIRST =2976,
-  XED_IFORMFL_STOSW_LAST =2974, +  XED_IFORMFL_STOSD_LAST =2976,
-  XED_IFORMFL_STR_FIRST =2975, +  XED_IFORMFL_STOSQ_FIRST =2977,
-  XED_IFORMFL_STR_LAST =2976, +  XED_IFORMFL_STOSQ_LAST =2977,
-  XED_IFORMFL_STTILECFG_FIRST =2977, +  XED_IFORMFL_STOSW_FIRST =2978,
-  XED_IFORMFL_STTILECFG_LAST =2978, +  XED_IFORMFL_STOSW_LAST =2978,
-  XED_IFORMFL_STUI_FIRST =2979, +  XED_IFORMFL_STR_FIRST =2979,
-  XED_IFORMFL_STUI_LAST =2979, +  XED_IFORMFL_STR_LAST =2980,
-  XED_IFORMFL_SUB_FIRST =2980, +  XED_IFORMFL_STTILECFG_FIRST =2981,
-  XED_IFORMFL_SUB_LAST =3021, +  XED_IFORMFL_STTILECFG_LAST =2982,
-  XED_IFORMFL_SUBPD_FIRST =3022, +  XED_IFORMFL_STUI_FIRST =2983,
-  XED_IFORMFL_SUBPD_LAST =3023, +  XED_IFORMFL_STUI_LAST =2983,
-  XED_IFORMFL_SUBPS_FIRST =3024, +  XED_IFORMFL_SUB_FIRST =2984,
-  XED_IFORMFL_SUBPS_LAST =3025, +  XED_IFORMFL_SUB_LAST =3025,
-  XED_IFORMFL_SUBSD_FIRST =3026, +  XED_IFORMFL_SUBPD_FIRST =3026,
-  XED_IFORMFL_SUBSD_LAST =3027, +  XED_IFORMFL_SUBPD_LAST =3027,
-  XED_IFORMFL_SUBSS_FIRST =3028, +  XED_IFORMFL_SUBPS_FIRST =3028,
-  XED_IFORMFL_SUBSS_LAST =3029, +  XED_IFORMFL_SUBPS_LAST =3029,
-  XED_IFORMFL_SUB_LOCK_FIRST =3030, +  XED_IFORMFL_SUBSD_FIRST =3030,
-  XED_IFORMFL_SUB_LOCK_LAST =3035, +  XED_IFORMFL_SUBSD_LAST =3031,
-  XED_IFORMFL_SWAPGS_FIRST =3036, +  XED_IFORMFL_SUBSS_FIRST =3032,
-  XED_IFORMFL_SWAPGS_LAST =3036, +  XED_IFORMFL_SUBSS_LAST =3033,
-  XED_IFORMFL_SYSCALL_FIRST =3037, +  XED_IFORMFL_SUB_LOCK_FIRST =3034,
-  XED_IFORMFL_SYSCALL_LAST =3037, +  XED_IFORMFL_SUB_LOCK_LAST =3039,
-  XED_IFORMFL_SYSCALL_32_FIRST =3038, +  XED_IFORMFL_SWAPGS_FIRST =3040,
-  XED_IFORMFL_SYSCALL_32_LAST =3038, +  XED_IFORMFL_SWAPGS_LAST =3040,
-  XED_IFORMFL_SYSENTER_FIRST =3039, +  XED_IFORMFL_SYSCALL_FIRST =3041,
-  XED_IFORMFL_SYSENTER_LAST =3039, +  XED_IFORMFL_SYSCALL_LAST =3041,
-  XED_IFORMFL_SYSEXIT_FIRST =3040, +  XED_IFORMFL_SYSCALL_32_FIRST =3042,
-  XED_IFORMFL_SYSEXIT_LAST =3040, +  XED_IFORMFL_SYSCALL_32_LAST =3042,
-  XED_IFORMFL_SYSRET_FIRST =3041, +  XED_IFORMFL_SYSENTER_FIRST =3043,
-  XED_IFORMFL_SYSRET_LAST =3041, +  XED_IFORMFL_SYSENTER_LAST =3043,
-  XED_IFORMFL_SYSRET64_FIRST =3042, +  XED_IFORMFL_SYSEXIT_FIRST =3044,
-  XED_IFORMFL_SYSRET64_LAST =3042, +  XED_IFORMFL_SYSEXIT_LAST =3044,
-  XED_IFORMFL_SYSRET_AMD_FIRST =3043, +  XED_IFORMFL_SYSRET_FIRST =3045,
-  XED_IFORMFL_SYSRET_AMD_LAST =3043, +  XED_IFORMFL_SYSRET_LAST =3045,
-  XED_IFORMFL_T1MSKC_FIRST =3044, +  XED_IFORMFL_SYSRET64_FIRST =3046,
-  XED_IFORMFL_T1MSKC_LAST =3047, +  XED_IFORMFL_SYSRET64_LAST =3046,
-  XED_IFORMFL_TCMMIMFP16PS_FIRST =3048, +  XED_IFORMFL_SYSRET_AMD_FIRST =3047,
-  XED_IFORMFL_TCMMIMFP16PS_LAST =3048, +  XED_IFORMFL_SYSRET_AMD_LAST =3047,
-  XED_IFORMFL_TCMMRLFP16PS_FIRST =3049, +  XED_IFORMFL_T1MSKC_FIRST =3048,
-  XED_IFORMFL_TCMMRLFP16PS_LAST =3049, +  XED_IFORMFL_T1MSKC_LAST =3051,
-  XED_IFORMFL_TDCALL_FIRST =3050, +  XED_IFORMFL_T2RPNTLVWZ0_FIRST =3052,
-  XED_IFORMFL_TDCALL_LAST =3050, +  XED_IFORMFL_T2RPNTLVWZ0_LAST =3052,
-  XED_IFORMFL_TDPBF16PS_FIRST =3051, +  XED_IFORMFL_T2RPNTLVWZ0RS_FIRST =3053,
-  XED_IFORMFL_TDPBF16PS_LAST =3051, +  XED_IFORMFL_T2RPNTLVWZ0RS_LAST =3053,
-  XED_IFORMFL_TDPBSSD_FIRST =3052, +  XED_IFORMFL_T2RPNTLVWZ0RST1_FIRST =3054,
-  XED_IFORMFL_TDPBSSD_LAST =3052, +  XED_IFORMFL_T2RPNTLVWZ0RST1_LAST =3054,
-  XED_IFORMFL_TDPBSUD_FIRST =3053, +  XED_IFORMFL_T2RPNTLVWZ0T1_FIRST =3055,
-  XED_IFORMFL_TDPBSUD_LAST =3053, +  XED_IFORMFL_T2RPNTLVWZ0T1_LAST =3055,
-  XED_IFORMFL_TDPBUSD_FIRST =3054, +  XED_IFORMFL_T2RPNTLVWZ1_FIRST =3056,
-  XED_IFORMFL_TDPBUSD_LAST =3054, +  XED_IFORMFL_T2RPNTLVWZ1_LAST =3056,
-  XED_IFORMFL_TDPBUUD_FIRST =3055, +  XED_IFORMFL_T2RPNTLVWZ1RS_FIRST =3057,
-  XED_IFORMFL_TDPBUUD_LAST =3055, +  XED_IFORMFL_T2RPNTLVWZ1RS_LAST =3057,
-  XED_IFORMFL_TDPFP16PS_FIRST =3056, +  XED_IFORMFL_T2RPNTLVWZ1RST1_FIRST =3058,
-  XED_IFORMFL_TDPFP16PS_LAST =3056, +  XED_IFORMFL_T2RPNTLVWZ1RST1_LAST =3058,
-  XED_IFORMFL_TEST_FIRST =3057, +  XED_IFORMFL_T2RPNTLVWZ1T1_FIRST =3059,
-  XED_IFORMFL_TEST_LAST =3070, +  XED_IFORMFL_T2RPNTLVWZ1T1_LAST =3059,
-  XED_IFORMFL_TESTUI_FIRST =3071, +  XED_IFORMFL_TCMMIMFP16PS_FIRST =3060,
-  XED_IFORMFL_TESTUI_LAST =3071, +  XED_IFORMFL_TCMMIMFP16PS_LAST =3060,
-  XED_IFORMFL_TILELOADD_FIRST =3072, +  XED_IFORMFL_TCMMRLFP16PS_FIRST =3061,
-  XED_IFORMFL_TILELOADD_LAST =3073, +  XED_IFORMFL_TCMMRLFP16PS_LAST =3061,
-  XED_IFORMFL_TILELOADDT1_FIRST =3074, +  XED_IFORMFL_TCONJTCMMIMFP16PS_FIRST =3062,
-  XED_IFORMFL_TILELOADDT1_LAST =3075, +  XED_IFORMFL_TCONJTCMMIMFP16PS_LAST =3062,
-  XED_IFORMFL_TILERELEASE_FIRST =3076, +  XED_IFORMFL_TCONJTFP16_FIRST =3063,
-  XED_IFORMFL_TILERELEASE_LAST =3076, +  XED_IFORMFL_TCONJTFP16_LAST =3063,
-  XED_IFORMFL_TILESTORED_FIRST =3077, +  XED_IFORMFL_TCVTROWD2PS_FIRST =3064,
-  XED_IFORMFL_TILESTORED_LAST =3078, +  XED_IFORMFL_TCVTROWD2PS_LAST =3065,
-  XED_IFORMFL_TILEZERO_FIRST =3079, +  XED_IFORMFL_TCVTROWPS2PBF16H_FIRST =3066,
-  XED_IFORMFL_TILEZERO_LAST =3079, +  XED_IFORMFL_TCVTROWPS2PBF16H_LAST =3067,
-  XED_IFORMFL_TLBSYNC_FIRST =3080, +  XED_IFORMFL_TCVTROWPS2PBF16L_FIRST =3068,
-  XED_IFORMFL_TLBSYNC_LAST =3080, +  XED_IFORMFL_TCVTROWPS2PBF16L_LAST =3069,
-  XED_IFORMFL_TPAUSE_FIRST =3081, +  XED_IFORMFL_TCVTROWPS2PHH_FIRST =3070,
-  XED_IFORMFL_TPAUSE_LAST =3081, +  XED_IFORMFL_TCVTROWPS2PHH_LAST =3071,
-  XED_IFORMFL_TZCNT_FIRST =3082, +  XED_IFORMFL_TCVTROWPS2PHL_FIRST =3072,
-  XED_IFORMFL_TZCNT_LAST =3085, +  XED_IFORMFL_TCVTROWPS2PHL_LAST =3073,
-  XED_IFORMFL_TZMSK_FIRST =3086, +  XED_IFORMFL_TDCALL_FIRST =3074,
-  XED_IFORMFL_TZMSK_LAST =3089, +  XED_IFORMFL_TDCALL_LAST =3074,
-  XED_IFORMFL_UCOMISD_FIRST =3090, +  XED_IFORMFL_TDPBF16PS_FIRST =3075,
-  XED_IFORMFL_UCOMISD_LAST =3091, +  XED_IFORMFL_TDPBF16PS_LAST =3075,
-  XED_IFORMFL_UCOMISS_FIRST =3092, +  XED_IFORMFL_TDPBF8PS_FIRST =3076,
-  XED_IFORMFL_UCOMISS_LAST =3093, +  XED_IFORMFL_TDPBF8PS_LAST =3076,
-  XED_IFORMFL_UD0_FIRST =3094, +  XED_IFORMFL_TDPBHF8PS_FIRST =3077,
-  XED_IFORMFL_UD0_LAST =3096, +  XED_IFORMFL_TDPBHF8PS_LAST =3077,
-  XED_IFORMFL_UD1_FIRST =3097, +  XED_IFORMFL_TDPBSSD_FIRST =3078,
-  XED_IFORMFL_UD1_LAST =3098, +  XED_IFORMFL_TDPBSSD_LAST =3078,
-  XED_IFORMFL_UD2_FIRST =3099, +  XED_IFORMFL_TDPBSUD_FIRST =3079,
-  XED_IFORMFL_UD2_LAST =3099, +  XED_IFORMFL_TDPBSUD_LAST =3079,
-  XED_IFORMFL_UIRET_FIRST =3100, +  XED_IFORMFL_TDPBUSD_FIRST =3080,
-  XED_IFORMFL_UIRET_LAST =3100, +  XED_IFORMFL_TDPBUSD_LAST =3080,
-  XED_IFORMFL_UMONITOR_FIRST =3101, +  XED_IFORMFL_TDPBUUD_FIRST =3081,
-  XED_IFORMFL_UMONITOR_LAST =3101, +  XED_IFORMFL_TDPBUUD_LAST =3081,
-  XED_IFORMFL_UMWAIT_FIRST =3102, +  XED_IFORMFL_TDPFP16PS_FIRST =3082,
-  XED_IFORMFL_UMWAIT_LAST =3102, +  XED_IFORMFL_TDPFP16PS_LAST =3082,
-  XED_IFORMFL_UNPCKHPD_FIRST =3103, +  XED_IFORMFL_TDPHBF8PS_FIRST =3083,
-  XED_IFORMFL_UNPCKHPD_LAST =3104, +  XED_IFORMFL_TDPHBF8PS_LAST =3083,
-  XED_IFORMFL_UNPCKHPS_FIRST =3105, +  XED_IFORMFL_TDPHF8PS_FIRST =3084,
-  XED_IFORMFL_UNPCKHPS_LAST =3106, +  XED_IFORMFL_TDPHF8PS_LAST =3084,
-  XED_IFORMFL_UNPCKLPD_FIRST =3107, +  XED_IFORMFL_TEST_FIRST =3085,
-  XED_IFORMFL_UNPCKLPD_LAST =3108, +  XED_IFORMFL_TEST_LAST =3098,
-  XED_IFORMFL_UNPCKLPS_FIRST =3109, +  XED_IFORMFL_TESTUI_FIRST =3099,
-  XED_IFORMFL_UNPCKLPS_LAST =3110, +  XED_IFORMFL_TESTUI_LAST =3099,
-  XED_IFORMFL_URDMSR_FIRST =3111, +  XED_IFORMFL_TILELOADD_FIRST =3100,
-  XED_IFORMFL_URDMSR_LAST =3114, +  XED_IFORMFL_TILELOADD_LAST =3101,
-  XED_IFORMFL_UWRMSR_FIRST =3115, +  XED_IFORMFL_TILELOADDRS_FIRST =3102,
-  XED_IFORMFL_UWRMSR_LAST =3118, +  XED_IFORMFL_TILELOADDRS_LAST =3102,
-  XED_IFORMFL_V4FMADDPS_FIRST =3119, +  XED_IFORMFL_TILELOADDRST1_FIRST =3103,
-  XED_IFORMFL_V4FMADDPS_LAST =3119, +  XED_IFORMFL_TILELOADDRST1_LAST =3103,
-  XED_IFORMFL_V4FMADDSS_FIRST =3120, +  XED_IFORMFL_TILELOADDT1_FIRST =3104,
-  XED_IFORMFL_V4FMADDSS_LAST =3120, +  XED_IFORMFL_TILELOADDT1_LAST =3105,
-  XED_IFORMFL_V4FNMADDPS_FIRST =3121, +  XED_IFORMFL_TILEMOVROW_FIRST =3106,
-  XED_IFORMFL_V4FNMADDPS_LAST =3121, +  XED_IFORMFL_TILEMOVROW_LAST =3107,
-  XED_IFORMFL_V4FNMADDSS_FIRST =3122, +  XED_IFORMFL_TILERELEASE_FIRST =3108,
-  XED_IFORMFL_V4FNMADDSS_LAST =3122, +  XED_IFORMFL_TILERELEASE_LAST =3108,
-  XED_IFORMFL_VADDPD_FIRST =3123, +  XED_IFORMFL_TILESTORED_FIRST =3109,
-  XED_IFORMFL_VADDPD_LAST =3132, +  XED_IFORMFL_TILESTORED_LAST =3110,
-  XED_IFORMFL_VADDPH_FIRST =3133, +  XED_IFORMFL_TILEZERO_FIRST =3111,
-  XED_IFORMFL_VADDPH_LAST =3138, +  XED_IFORMFL_TILEZERO_LAST =3111,
-  XED_IFORMFL_VADDPS_FIRST =3139, +  XED_IFORMFL_TLBSYNC_FIRST =3112,
-  XED_IFORMFL_VADDPS_LAST =3148, +  XED_IFORMFL_TLBSYNC_LAST =3112,
-  XED_IFORMFL_VADDSD_FIRST =3149, +  XED_IFORMFL_TMMULTF32PS_FIRST =3113,
-  XED_IFORMFL_VADDSD_LAST =3152, +  XED_IFORMFL_TMMULTF32PS_LAST =3113,
-  XED_IFORMFL_VADDSH_FIRST =3153, +  XED_IFORMFL_TPAUSE_FIRST =3114,
-  XED_IFORMFL_VADDSH_LAST =3154, +  XED_IFORMFL_TPAUSE_LAST =3114,
-  XED_IFORMFL_VADDSS_FIRST =3155, +  XED_IFORMFL_TTCMMIMFP16PS_FIRST =3115,
-  XED_IFORMFL_VADDSS_LAST =3158, +  XED_IFORMFL_TTCMMIMFP16PS_LAST =3115,
-  XED_IFORMFL_VADDSUBPD_FIRST =3159, +  XED_IFORMFL_TTCMMRLFP16PS_FIRST =3116,
-  XED_IFORMFL_VADDSUBPD_LAST =3162, +  XED_IFORMFL_TTCMMRLFP16PS_LAST =3116,
-  XED_IFORMFL_VADDSUBPS_FIRST =3163, +  XED_IFORMFL_TTDPBF16PS_FIRST =3117,
-  XED_IFORMFL_VADDSUBPS_LAST =3166, +  XED_IFORMFL_TTDPBF16PS_LAST =3117,
-  XED_IFORMFL_VAESDEC_FIRST =3167, +  XED_IFORMFL_TTDPFP16PS_FIRST =3118,
-  XED_IFORMFL_VAESDEC_LAST =3176, +  XED_IFORMFL_TTDPFP16PS_LAST =3118,
-  XED_IFORMFL_VAESDECLAST_FIRST =3177, +  XED_IFORMFL_TTMMULTF32PS_FIRST =3119,
-  XED_IFORMFL_VAESDECLAST_LAST =3186, +  XED_IFORMFL_TTMMULTF32PS_LAST =3119,
-  XED_IFORMFL_VAESENC_FIRST =3187, +  XED_IFORMFL_TTRANSPOSED_FIRST =3120,
-  XED_IFORMFL_VAESENC_LAST =3196, +  XED_IFORMFL_TTRANSPOSED_LAST =3120,
-  XED_IFORMFL_VAESENCLAST_FIRST =3197, +  XED_IFORMFL_TZCNT_FIRST =3121,
-  XED_IFORMFL_VAESENCLAST_LAST =3206, +  XED_IFORMFL_TZCNT_LAST =3124,
-  XED_IFORMFL_VAESIMC_FIRST =3207, +  XED_IFORMFL_TZMSK_FIRST =3125,
-  XED_IFORMFL_VAESIMC_LAST =3208, +  XED_IFORMFL_TZMSK_LAST =3128,
-  XED_IFORMFL_VAESKEYGENASSIST_FIRST =3209, +  XED_IFORMFL_UCOMISD_FIRST =3129,
-  XED_IFORMFL_VAESKEYGENASSIST_LAST =3210, +  XED_IFORMFL_UCOMISD_LAST =3130,
-  XED_IFORMFL_VALIGND_FIRST =3211, +  XED_IFORMFL_UCOMISS_FIRST =3131,
-  XED_IFORMFL_VALIGND_LAST =3216, +  XED_IFORMFL_UCOMISS_LAST =3132,
-  XED_IFORMFL_VALIGNQ_FIRST =3217, +  XED_IFORMFL_UD0_FIRST =3133,
-  XED_IFORMFL_VALIGNQ_LAST =3222, +  XED_IFORMFL_UD0_LAST =3135,
-  XED_IFORMFL_VANDNPD_FIRST =3223, +  XED_IFORMFL_UD1_FIRST =3136,
-  XED_IFORMFL_VANDNPD_LAST =3232, +  XED_IFORMFL_UD1_LAST =3137,
-  XED_IFORMFL_VANDNPS_FIRST =3233, +  XED_IFORMFL_UD2_FIRST =3138,
-  XED_IFORMFL_VANDNPS_LAST =3242, +  XED_IFORMFL_UD2_LAST =3138,
-  XED_IFORMFL_VANDPD_FIRST =3243, +  XED_IFORMFL_UIRET_FIRST =3139,
-  XED_IFORMFL_VANDPD_LAST =3252, +  XED_IFORMFL_UIRET_LAST =3139,
-  XED_IFORMFL_VANDPS_FIRST =3253, +  XED_IFORMFL_UMONITOR_FIRST =3140,
-  XED_IFORMFL_VANDPS_LAST =3262, +  XED_IFORMFL_UMONITOR_LAST =3140,
-  XED_IFORMFL_VBCSTNEBF162PS_FIRST =3263, +  XED_IFORMFL_UMWAIT_FIRST =3141,
-  XED_IFORMFL_VBCSTNEBF162PS_LAST =3264, +  XED_IFORMFL_UMWAIT_LAST =3141,
-  XED_IFORMFL_VBCSTNESH2PS_FIRST =3265, +  XED_IFORMFL_UNPCKHPD_FIRST =3142,
-  XED_IFORMFL_VBCSTNESH2PS_LAST =3266, +  XED_IFORMFL_UNPCKHPD_LAST =3143,
-  XED_IFORMFL_VBLENDMPD_FIRST =3267, +  XED_IFORMFL_UNPCKHPS_FIRST =3144,
-  XED_IFORMFL_VBLENDMPD_LAST =3272, +  XED_IFORMFL_UNPCKHPS_LAST =3145,
-  XED_IFORMFL_VBLENDMPS_FIRST =3273, +  XED_IFORMFL_UNPCKLPD_FIRST =3146,
-  XED_IFORMFL_VBLENDMPS_LAST =3278, +  XED_IFORMFL_UNPCKLPD_LAST =3147,
-  XED_IFORMFL_VBLENDPD_FIRST =3279, +  XED_IFORMFL_UNPCKLPS_FIRST =3148,
-  XED_IFORMFL_VBLENDPD_LAST =3282, +  XED_IFORMFL_UNPCKLPS_LAST =3149,
-  XED_IFORMFL_VBLENDPS_FIRST =3283, +  XED_IFORMFL_URDMSR_FIRST =3150,
-  XED_IFORMFL_VBLENDPS_LAST =3286, +  XED_IFORMFL_URDMSR_LAST =3153,
-  XED_IFORMFL_VBLENDVPD_FIRST =3287, +  XED_IFORMFL_UWRMSR_FIRST =3154,
-  XED_IFORMFL_VBLENDVPD_LAST =3290, +  XED_IFORMFL_UWRMSR_LAST =3157,
-  XED_IFORMFL_VBLENDVPS_FIRST =3291, +  XED_IFORMFL_V4FMADDPS_FIRST =3158,
-  XED_IFORMFL_VBLENDVPS_LAST =3294, +  XED_IFORMFL_V4FMADDPS_LAST =3158,
-  XED_IFORMFL_VBROADCASTF128_FIRST =3295, +  XED_IFORMFL_V4FMADDSS_FIRST =3159,
-  XED_IFORMFL_VBROADCASTF128_LAST =3295, +  XED_IFORMFL_V4FMADDSS_LAST =3159,
-  XED_IFORMFL_VBROADCASTF32X2_FIRST =3296, +  XED_IFORMFL_V4FNMADDPS_FIRST =3160,
-  XED_IFORMFL_VBROADCASTF32X2_LAST =3299, +  XED_IFORMFL_V4FNMADDPS_LAST =3160,
-  XED_IFORMFL_VBROADCASTF32X4_FIRST =3300, +  XED_IFORMFL_V4FNMADDSS_FIRST =3161,
-  XED_IFORMFL_VBROADCASTF32X4_LAST =3301, +  XED_IFORMFL_V4FNMADDSS_LAST =3161,
-  XED_IFORMFL_VBROADCASTF32X8_FIRST =3302, +  XED_IFORMFL_VADDNEPBF16_FIRST =3162,
-  XED_IFORMFL_VBROADCASTF32X8_LAST =3302, +  XED_IFORMFL_VADDNEPBF16_LAST =3167,
-  XED_IFORMFL_VBROADCASTF64X2_FIRST =3303, +  XED_IFORMFL_VADDPD_FIRST =3168,
-  XED_IFORMFL_VBROADCASTF64X2_LAST =3304, +  XED_IFORMFL_VADDPD_LAST =3178,
-  XED_IFORMFL_VBROADCASTF64X4_FIRST =3305, +  XED_IFORMFL_VADDPH_FIRST =3179,
-  XED_IFORMFL_VBROADCASTF64X4_LAST =3305, +  XED_IFORMFL_VADDPH_LAST =3185,
-  XED_IFORMFL_VBROADCASTI128_FIRST =3306, +  XED_IFORMFL_VADDPS_FIRST =3186,
-  XED_IFORMFL_VBROADCASTI128_LAST =3306, +  XED_IFORMFL_VADDPS_LAST =3196,
-  XED_IFORMFL_VBROADCASTI32X2_FIRST =3307, +  XED_IFORMFL_VADDSD_FIRST =3197,
-  XED_IFORMFL_VBROADCASTI32X2_LAST =3312, +  XED_IFORMFL_VADDSD_LAST =3201,
-  XED_IFORMFL_VBROADCASTI32X4_FIRST =3313, +  XED_IFORMFL_VADDSH_FIRST =3202,
-  XED_IFORMFL_VBROADCASTI32X4_LAST =3314, +  XED_IFORMFL_VADDSH_LAST =3204,
-  XED_IFORMFL_VBROADCASTI32X8_FIRST =3315, +  XED_IFORMFL_VADDSS_FIRST =3205,
-  XED_IFORMFL_VBROADCASTI32X8_LAST =3315, +  XED_IFORMFL_VADDSS_LAST =3209,
-  XED_IFORMFL_VBROADCASTI64X2_FIRST =3316, +  XED_IFORMFL_VADDSUBPD_FIRST =3210,
-  XED_IFORMFL_VBROADCASTI64X2_LAST =3317, +  XED_IFORMFL_VADDSUBPD_LAST =3213,
-  XED_IFORMFL_VBROADCASTI64X4_FIRST =3318, +  XED_IFORMFL_VADDSUBPS_FIRST =3214,
-  XED_IFORMFL_VBROADCASTI64X4_LAST =3318, +  XED_IFORMFL_VADDSUBPS_LAST =3217,
-  XED_IFORMFL_VBROADCASTSD_FIRST =3319, +  XED_IFORMFL_VAESDEC_FIRST =3218,
-  XED_IFORMFL_VBROADCASTSD_LAST =3324, +  XED_IFORMFL_VAESDEC_LAST =3227,
-  XED_IFORMFL_VBROADCASTSS_FIRST =3325, +  XED_IFORMFL_VAESDECLAST_FIRST =3228,
-  XED_IFORMFL_VBROADCASTSS_LAST =3334, +  XED_IFORMFL_VAESDECLAST_LAST =3237,
-  XED_IFORMFL_VCMPPD_FIRST =3335, +  XED_IFORMFL_VAESENC_FIRST =3238,
-  XED_IFORMFL_VCMPPD_LAST =3344, +  XED_IFORMFL_VAESENC_LAST =3247,
-  XED_IFORMFL_VCMPPH_FIRST =3345, +  XED_IFORMFL_VAESENCLAST_FIRST =3248,
-  XED_IFORMFL_VCMPPH_LAST =3350, +  XED_IFORMFL_VAESENCLAST_LAST =3257,
-  XED_IFORMFL_VCMPPS_FIRST =3351, +  XED_IFORMFL_VAESIMC_FIRST =3258,
-  XED_IFORMFL_VCMPPS_LAST =3360, +  XED_IFORMFL_VAESIMC_LAST =3259,
-  XED_IFORMFL_VCMPSD_FIRST =3361, +  XED_IFORMFL_VAESKEYGENASSIST_FIRST =3260,
-  XED_IFORMFL_VCMPSD_LAST =3364, +  XED_IFORMFL_VAESKEYGENASSIST_LAST =3261,
-  XED_IFORMFL_VCMPSH_FIRST =3365, +  XED_IFORMFL_VALIGND_FIRST =3262,
-  XED_IFORMFL_VCMPSH_LAST =3366, +  XED_IFORMFL_VALIGND_LAST =3267,
-  XED_IFORMFL_VCMPSS_FIRST =3367, +  XED_IFORMFL_VALIGNQ_FIRST =3268,
-  XED_IFORMFL_VCMPSS_LAST =3370, +  XED_IFORMFL_VALIGNQ_LAST =3273,
-  XED_IFORMFL_VCOMISD_FIRST =3371, +  XED_IFORMFL_VANDNPD_FIRST =3274,
-  XED_IFORMFL_VCOMISD_LAST =3374, +  XED_IFORMFL_VANDNPD_LAST =3283,
-  XED_IFORMFL_VCOMISH_FIRST =3375, +  XED_IFORMFL_VANDNPS_FIRST =3284,
-  XED_IFORMFL_VCOMISH_LAST =3376, +  XED_IFORMFL_VANDNPS_LAST =3293,
-  XED_IFORMFL_VCOMISS_FIRST =3377, +  XED_IFORMFL_VANDPD_FIRST =3294,
-  XED_IFORMFL_VCOMISS_LAST =3380, +  XED_IFORMFL_VANDPD_LAST =3303,
-  XED_IFORMFL_VCOMPRESSPD_FIRST =3381, +  XED_IFORMFL_VANDPS_FIRST =3304,
-  XED_IFORMFL_VCOMPRESSPD_LAST =3386, +  XED_IFORMFL_VANDPS_LAST =3313,
-  XED_IFORMFL_VCOMPRESSPS_FIRST =3387, +  XED_IFORMFL_VBCSTNEBF162PS_FIRST =3314,
-  XED_IFORMFL_VCOMPRESSPS_LAST =3392, +  XED_IFORMFL_VBCSTNEBF162PS_LAST =3315,
-  XED_IFORMFL_VCVTDQ2PD_FIRST =3393, +  XED_IFORMFL_VBCSTNESH2PS_FIRST =3316,
-  XED_IFORMFL_VCVTDQ2PD_LAST =3402, +  XED_IFORMFL_VBCSTNESH2PS_LAST =3317,
-  XED_IFORMFL_VCVTDQ2PH_FIRST =3403, +  XED_IFORMFL_VBLENDMPD_FIRST =3318,
-  XED_IFORMFL_VCVTDQ2PH_LAST =3408, +  XED_IFORMFL_VBLENDMPD_LAST =3323,
-  XED_IFORMFL_VCVTDQ2PS_FIRST =3409, +  XED_IFORMFL_VBLENDMPS_FIRST =3324,
-  XED_IFORMFL_VCVTDQ2PS_LAST =3418, +  XED_IFORMFL_VBLENDMPS_LAST =3329,
-  XED_IFORMFL_VCVTNE2PS2BF16_FIRST =3419, +  XED_IFORMFL_VBLENDPD_FIRST =3330,
-  XED_IFORMFL_VCVTNE2PS2BF16_LAST =3424, +  XED_IFORMFL_VBLENDPD_LAST =3333,
-  XED_IFORMFL_VCVTNEEBF162PS_FIRST =3425, +  XED_IFORMFL_VBLENDPS_FIRST =3334,
-  XED_IFORMFL_VCVTNEEBF162PS_LAST =3426, +  XED_IFORMFL_VBLENDPS_LAST =3337,
-  XED_IFORMFL_VCVTNEEPH2PS_FIRST =3427, +  XED_IFORMFL_VBLENDVPD_FIRST =3338,
-  XED_IFORMFL_VCVTNEEPH2PS_LAST =3428, +  XED_IFORMFL_VBLENDVPD_LAST =3341,
-  XED_IFORMFL_VCVTNEOBF162PS_FIRST =3429, +  XED_IFORMFL_VBLENDVPS_FIRST =3342,
-  XED_IFORMFL_VCVTNEOBF162PS_LAST =3430, +  XED_IFORMFL_VBLENDVPS_LAST =3345,
-  XED_IFORMFL_VCVTNEOPH2PS_FIRST =3431, +  XED_IFORMFL_VBROADCASTF128_FIRST =3346,
-  XED_IFORMFL_VCVTNEOPH2PS_LAST =3432, +  XED_IFORMFL_VBROADCASTF128_LAST =3346,
-  XED_IFORMFL_VCVTNEPS2BF16_FIRST =3433, +  XED_IFORMFL_VBROADCASTF32X2_FIRST =3347,
-  XED_IFORMFL_VCVTNEPS2BF16_LAST =3442, +  XED_IFORMFL_VBROADCASTF32X2_LAST =3350,
-  XED_IFORMFL_VCVTPD2DQ_FIRST =3443, +  XED_IFORMFL_VBROADCASTF32X4_FIRST =3351,
-  XED_IFORMFL_VCVTPD2DQ_LAST =3452, +  XED_IFORMFL_VBROADCASTF32X4_LAST =3352,
-  XED_IFORMFL_VCVTPD2PH_FIRST =3453, +  XED_IFORMFL_VBROADCASTF32X8_FIRST =3353,
-  XED_IFORMFL_VCVTPD2PH_LAST =3458, +  XED_IFORMFL_VBROADCASTF32X8_LAST =3353,
-  XED_IFORMFL_VCVTPD2PS_FIRST =3459, +  XED_IFORMFL_VBROADCASTF64X2_FIRST =3354,
-  XED_IFORMFL_VCVTPD2PS_LAST =3468, +  XED_IFORMFL_VBROADCASTF64X2_LAST =3355,
-  XED_IFORMFL_VCVTPD2QQ_FIRST =3469, +  XED_IFORMFL_VBROADCASTF64X4_FIRST =3356,
-  XED_IFORMFL_VCVTPD2QQ_LAST =3474, +  XED_IFORMFL_VBROADCASTF64X4_LAST =3356,
-  XED_IFORMFL_VCVTPD2UDQ_FIRST =3475, +  XED_IFORMFL_VBROADCASTI128_FIRST =3357,
-  XED_IFORMFL_VCVTPD2UDQ_LAST =3480, +  XED_IFORMFL_VBROADCASTI128_LAST =3357,
-  XED_IFORMFL_VCVTPD2UQQ_FIRST =3481, +  XED_IFORMFL_VBROADCASTI32X2_FIRST =3358,
-  XED_IFORMFL_VCVTPD2UQQ_LAST =3486, +  XED_IFORMFL_VBROADCASTI32X2_LAST =3363,
-  XED_IFORMFL_VCVTPH2DQ_FIRST =3487, +  XED_IFORMFL_VBROADCASTI32X4_FIRST =3364,
-  XED_IFORMFL_VCVTPH2DQ_LAST =3492, +  XED_IFORMFL_VBROADCASTI32X4_LAST =3365,
-  XED_IFORMFL_VCVTPH2PD_FIRST =3493, +  XED_IFORMFL_VBROADCASTI32X8_FIRST =3366,
-  XED_IFORMFL_VCVTPH2PD_LAST =3498, +  XED_IFORMFL_VBROADCASTI32X8_LAST =3366,
-  XED_IFORMFL_VCVTPH2PS_FIRST =3499, +  XED_IFORMFL_VBROADCASTI64X2_FIRST =3367,
-  XED_IFORMFL_VCVTPH2PS_LAST =3508, +  XED_IFORMFL_VBROADCASTI64X2_LAST =3368,
-  XED_IFORMFL_VCVTPH2PSX_FIRST =3509, +  XED_IFORMFL_VBROADCASTI64X4_FIRST =3369,
-  XED_IFORMFL_VCVTPH2PSX_LAST =3514, +  XED_IFORMFL_VBROADCASTI64X4_LAST =3369,
-  XED_IFORMFL_VCVTPH2QQ_FIRST =3515, +  XED_IFORMFL_VBROADCASTSD_FIRST =3370,
-  XED_IFORMFL_VCVTPH2QQ_LAST =3520, +  XED_IFORMFL_VBROADCASTSD_LAST =3375,
-  XED_IFORMFL_VCVTPH2UDQ_FIRST =3521, +  XED_IFORMFL_VBROADCASTSS_FIRST =3376,
-  XED_IFORMFL_VCVTPH2UDQ_LAST =3526, +  XED_IFORMFL_VBROADCASTSS_LAST =3385,
-  XED_IFORMFL_VCVTPH2UQQ_FIRST =3527, +  XED_IFORMFL_VCMPPBF16_FIRST =3386,
-  XED_IFORMFL_VCVTPH2UQQ_LAST =3532, +  XED_IFORMFL_VCMPPBF16_LAST =3391,
-  XED_IFORMFL_VCVTPH2UW_FIRST =3533, +  XED_IFORMFL_VCMPPD_FIRST =3392,
-  XED_IFORMFL_VCVTPH2UW_LAST =3538, +  XED_IFORMFL_VCMPPD_LAST =3402,
-  XED_IFORMFL_VCVTPH2W_FIRST =3539, +  XED_IFORMFL_VCMPPH_FIRST =3403,
-  XED_IFORMFL_VCVTPH2W_LAST =3544, +  XED_IFORMFL_VCMPPH_LAST =3409,
-  XED_IFORMFL_VCVTPS2DQ_FIRST =3545, +  XED_IFORMFL_VCMPPS_FIRST =3410,
-  XED_IFORMFL_VCVTPS2DQ_LAST =3554, +  XED_IFORMFL_VCMPPS_LAST =3420,
-  XED_IFORMFL_VCVTPS2PD_FIRST =3555, +  XED_IFORMFL_VCMPSD_FIRST =3421,
-  XED_IFORMFL_VCVTPS2PD_LAST =3564, +  XED_IFORMFL_VCMPSD_LAST =3425,
-  XED_IFORMFL_VCVTPS2PH_FIRST =3565, +  XED_IFORMFL_VCMPSH_FIRST =3426,
-  XED_IFORMFL_VCVTPS2PH_LAST =3574, +  XED_IFORMFL_VCMPSH_LAST =3428,
-  XED_IFORMFL_VCVTPS2PHX_FIRST =3575, +  XED_IFORMFL_VCMPSS_FIRST =3429,
-  XED_IFORMFL_VCVTPS2PHX_LAST =3580, +  XED_IFORMFL_VCMPSS_LAST =3433,
-  XED_IFORMFL_VCVTPS2QQ_FIRST =3581, +  XED_IFORMFL_VCOMISD_FIRST =3434,
-  XED_IFORMFL_VCVTPS2QQ_LAST =3586, +  XED_IFORMFL_VCOMISD_LAST =3438,
-  XED_IFORMFL_VCVTPS2UDQ_FIRST =3587, +  XED_IFORMFL_VCOMISH_FIRST =3439,
-  XED_IFORMFL_VCVTPS2UDQ_LAST =3592, +  XED_IFORMFL_VCOMISH_LAST =3441,
-  XED_IFORMFL_VCVTPS2UQQ_FIRST =3593, +  XED_IFORMFL_VCOMISS_FIRST =3442,
-  XED_IFORMFL_VCVTPS2UQQ_LAST =3598, +  XED_IFORMFL_VCOMISS_LAST =3446,
-  XED_IFORMFL_VCVTQQ2PD_FIRST =3599, +  XED_IFORMFL_VCOMPRESSPD_FIRST =3447,
-  XED_IFORMFL_VCVTQQ2PD_LAST =3604, +  XED_IFORMFL_VCOMPRESSPD_LAST =3452,
-  XED_IFORMFL_VCVTQQ2PH_FIRST =3605, +  XED_IFORMFL_VCOMPRESSPS_FIRST =3453,
-  XED_IFORMFL_VCVTQQ2PH_LAST =3610, +  XED_IFORMFL_VCOMPRESSPS_LAST =3458,
-  XED_IFORMFL_VCVTQQ2PS_FIRST =3611, +  XED_IFORMFL_VCOMSBF16_FIRST =3459,
-  XED_IFORMFL_VCVTQQ2PS_LAST =3616, +  XED_IFORMFL_VCOMSBF16_LAST =3460,
-  XED_IFORMFL_VCVTSD2SH_FIRST =3617, +  XED_IFORMFL_VCOMXSD_FIRST =3461,
-  XED_IFORMFL_VCVTSD2SH_LAST =3618, +  XED_IFORMFL_VCOMXSD_LAST =3462,
-  XED_IFORMFL_VCVTSD2SI_FIRST =3619, +  XED_IFORMFL_VCOMXSH_FIRST =3463,
-  XED_IFORMFL_VCVTSD2SI_LAST =3626, +  XED_IFORMFL_VCOMXSH_LAST =3464,
-  XED_IFORMFL_VCVTSD2SS_FIRST =3627, +  XED_IFORMFL_VCOMXSS_FIRST =3465,
-  XED_IFORMFL_VCVTSD2SS_LAST =3630, +  XED_IFORMFL_VCOMXSS_LAST =3466,
-  XED_IFORMFL_VCVTSD2USI_FIRST =3631, +  XED_IFORMFL_VCVT2PS2PHX_FIRST =3467,
-  XED_IFORMFL_VCVTSD2USI_LAST =3634, +  XED_IFORMFL_VCVT2PS2PHX_LAST =3472,
-  XED_IFORMFL_VCVTSH2SD_FIRST =3635, +  XED_IFORMFL_VCVTBIASPH2BF8_FIRST =3473,
-  XED_IFORMFL_VCVTSH2SD_LAST =3636, +  XED_IFORMFL_VCVTBIASPH2BF8_LAST =3478,
-  XED_IFORMFL_VCVTSH2SI_FIRST =3637, +  XED_IFORMFL_VCVTBIASPH2BF8S_FIRST =3479,
-  XED_IFORMFL_VCVTSH2SI_LAST =3640, +  XED_IFORMFL_VCVTBIASPH2BF8S_LAST =3484,
-  XED_IFORMFL_VCVTSH2SS_FIRST =3641, +  XED_IFORMFL_VCVTBIASPH2HF8_FIRST =3485,
-  XED_IFORMFL_VCVTSH2SS_LAST =3642, +  XED_IFORMFL_VCVTBIASPH2HF8_LAST =3490,
-  XED_IFORMFL_VCVTSH2USI_FIRST =3643, +  XED_IFORMFL_VCVTBIASPH2HF8S_FIRST =3491,
-  XED_IFORMFL_VCVTSH2USI_LAST =3646, +  XED_IFORMFL_VCVTBIASPH2HF8S_LAST =3496,
-  XED_IFORMFL_VCVTSI2SD_FIRST =3647, +  XED_IFORMFL_VCVTDQ2PD_FIRST =3497,
-  XED_IFORMFL_VCVTSI2SD_LAST =3654, +  XED_IFORMFL_VCVTDQ2PD_LAST =3507,
-  XED_IFORMFL_VCVTSI2SH_FIRST =3655, +  XED_IFORMFL_VCVTDQ2PH_FIRST =3508,
-  XED_IFORMFL_VCVTSI2SH_LAST =3658, +  XED_IFORMFL_VCVTDQ2PH_LAST =3514,
-  XED_IFORMFL_VCVTSI2SS_FIRST =3659, +  XED_IFORMFL_VCVTDQ2PS_FIRST =3515,
-  XED_IFORMFL_VCVTSI2SS_LAST =3666, +  XED_IFORMFL_VCVTDQ2PS_LAST =3525,
-  XED_IFORMFL_VCVTSS2SD_FIRST =3667, +  XED_IFORMFL_VCVTHF82PH_FIRST =3526,
-  XED_IFORMFL_VCVTSS2SD_LAST =3670, +  XED_IFORMFL_VCVTHF82PH_LAST =3531,
-  XED_IFORMFL_VCVTSS2SH_FIRST =3671, +  XED_IFORMFL_VCVTNE2PH2BF8_FIRST =3532,
-  XED_IFORMFL_VCVTSS2SH_LAST =3672, +  XED_IFORMFL_VCVTNE2PH2BF8_LAST =3537,
-  XED_IFORMFL_VCVTSS2SI_FIRST =3673, +  XED_IFORMFL_VCVTNE2PH2BF8S_FIRST =3538,
-  XED_IFORMFL_VCVTSS2SI_LAST =3680, +  XED_IFORMFL_VCVTNE2PH2BF8S_LAST =3543,
-  XED_IFORMFL_VCVTSS2USI_FIRST =3681, +  XED_IFORMFL_VCVTNE2PH2HF8_FIRST =3544,
-  XED_IFORMFL_VCVTSS2USI_LAST =3684, +  XED_IFORMFL_VCVTNE2PH2HF8_LAST =3549,
-  XED_IFORMFL_VCVTTPD2DQ_FIRST =3685, +  XED_IFORMFL_VCVTNE2PH2HF8S_FIRST =3550,
-  XED_IFORMFL_VCVTTPD2DQ_LAST =3694, +  XED_IFORMFL_VCVTNE2PH2HF8S_LAST =3555,
-  XED_IFORMFL_VCVTTPD2QQ_FIRST =3695, +  XED_IFORMFL_VCVTNE2PS2BF16_FIRST =3556,
-  XED_IFORMFL_VCVTTPD2QQ_LAST =3700, +  XED_IFORMFL_VCVTNE2PS2BF16_LAST =3561,
-  XED_IFORMFL_VCVTTPD2UDQ_FIRST =3701, +  XED_IFORMFL_VCVTNEBF162IBS_FIRST =3562,
-  XED_IFORMFL_VCVTTPD2UDQ_LAST =3706, +  XED_IFORMFL_VCVTNEBF162IBS_LAST =3567,
-  XED_IFORMFL_VCVTTPD2UQQ_FIRST =3707, +  XED_IFORMFL_VCVTNEBF162IUBS_FIRST =3568,
-  XED_IFORMFL_VCVTTPD2UQQ_LAST =3712, +  XED_IFORMFL_VCVTNEBF162IUBS_LAST =3573,
-  XED_IFORMFL_VCVTTPH2DQ_FIRST =3713, +  XED_IFORMFL_VCVTNEEBF162PS_FIRST =3574,
-  XED_IFORMFL_VCVTTPH2DQ_LAST =3718, +  XED_IFORMFL_VCVTNEEBF162PS_LAST =3575,
-  XED_IFORMFL_VCVTTPH2QQ_FIRST =3719, +  XED_IFORMFL_VCVTNEEPH2PS_FIRST =3576,
-  XED_IFORMFL_VCVTTPH2QQ_LAST =3724, +  XED_IFORMFL_VCVTNEEPH2PS_LAST =3577,
-  XED_IFORMFL_VCVTTPH2UDQ_FIRST =3725, +  XED_IFORMFL_VCVTNEOBF162PS_FIRST =3578,
-  XED_IFORMFL_VCVTTPH2UDQ_LAST =3730, +  XED_IFORMFL_VCVTNEOBF162PS_LAST =3579,
-  XED_IFORMFL_VCVTTPH2UQQ_FIRST =3731, +  XED_IFORMFL_VCVTNEOPH2PS_FIRST =3580,
-  XED_IFORMFL_VCVTTPH2UQQ_LAST =3736, +  XED_IFORMFL_VCVTNEOPH2PS_LAST =3581,
-  XED_IFORMFL_VCVTTPH2UW_FIRST =3737, +  XED_IFORMFL_VCVTNEPH2BF8_FIRST =3582,
-  XED_IFORMFL_VCVTTPH2UW_LAST =3742, +  XED_IFORMFL_VCVTNEPH2BF8_LAST =3587,
-  XED_IFORMFL_VCVTTPH2W_FIRST =3743, +  XED_IFORMFL_VCVTNEPH2BF8S_FIRST =3588,
-  XED_IFORMFL_VCVTTPH2W_LAST =3748, +  XED_IFORMFL_VCVTNEPH2BF8S_LAST =3593,
-  XED_IFORMFL_VCVTTPS2DQ_FIRST =3749, +  XED_IFORMFL_VCVTNEPH2HF8_FIRST =3594,
-  XED_IFORMFL_VCVTTPS2DQ_LAST =3758, +  XED_IFORMFL_VCVTNEPH2HF8_LAST =3599,
-  XED_IFORMFL_VCVTTPS2QQ_FIRST =3759, +  XED_IFORMFL_VCVTNEPH2HF8S_FIRST =3600,
-  XED_IFORMFL_VCVTTPS2QQ_LAST =3764, +  XED_IFORMFL_VCVTNEPH2HF8S_LAST =3605,
-  XED_IFORMFL_VCVTTPS2UDQ_FIRST =3765, +  XED_IFORMFL_VCVTNEPS2BF16_FIRST =3606,
-  XED_IFORMFL_VCVTTPS2UDQ_LAST =3770, +  XED_IFORMFL_VCVTNEPS2BF16_LAST =3615,
-  XED_IFORMFL_VCVTTPS2UQQ_FIRST =3771, +  XED_IFORMFL_VCVTPD2DQ_FIRST =3616,
-  XED_IFORMFL_VCVTTPS2UQQ_LAST =3776, +  XED_IFORMFL_VCVTPD2DQ_LAST =3626,
-  XED_IFORMFL_VCVTTSD2SI_FIRST =3777, +  XED_IFORMFL_VCVTPD2PH_FIRST =3627,
-  XED_IFORMFL_VCVTTSD2SI_LAST =3784, +  XED_IFORMFL_VCVTPD2PH_LAST =3633,
-  XED_IFORMFL_VCVTTSD2USI_FIRST =3785, +  XED_IFORMFL_VCVTPD2PS_FIRST =3634,
-  XED_IFORMFL_VCVTTSD2USI_LAST =3788, +  XED_IFORMFL_VCVTPD2PS_LAST =3644,
-  XED_IFORMFL_VCVTTSH2SI_FIRST =3789, +  XED_IFORMFL_VCVTPD2QQ_FIRST =3645,
-  XED_IFORMFL_VCVTTSH2SI_LAST =3792, +  XED_IFORMFL_VCVTPD2QQ_LAST =3651,
-  XED_IFORMFL_VCVTTSH2USI_FIRST =3793, +  XED_IFORMFL_VCVTPD2UDQ_FIRST =3652,
-  XED_IFORMFL_VCVTTSH2USI_LAST =3796, +  XED_IFORMFL_VCVTPD2UDQ_LAST =3658,
-  XED_IFORMFL_VCVTTSS2SI_FIRST =3797, +  XED_IFORMFL_VCVTPD2UQQ_FIRST =3659,
-  XED_IFORMFL_VCVTTSS2SI_LAST =3804, +  XED_IFORMFL_VCVTPD2UQQ_LAST =3665,
-  XED_IFORMFL_VCVTTSS2USI_FIRST =3805, +  XED_IFORMFL_VCVTPH2DQ_FIRST =3666,
-  XED_IFORMFL_VCVTTSS2USI_LAST =3808, +  XED_IFORMFL_VCVTPH2DQ_LAST =3672,
-  XED_IFORMFL_VCVTUDQ2PD_FIRST =3809, +  XED_IFORMFL_VCVTPH2IBS_FIRST =3673,
-  XED_IFORMFL_VCVTUDQ2PD_LAST =3814, +  XED_IFORMFL_VCVTPH2IBS_LAST =3678,
-  XED_IFORMFL_VCVTUDQ2PH_FIRST =3815, +  XED_IFORMFL_VCVTPH2IUBS_FIRST =3679,
-  XED_IFORMFL_VCVTUDQ2PH_LAST =3820, +  XED_IFORMFL_VCVTPH2IUBS_LAST =3684,
-  XED_IFORMFL_VCVTUDQ2PS_FIRST =3821, +  XED_IFORMFL_VCVTPH2PD_FIRST =3685,
-  XED_IFORMFL_VCVTUDQ2PS_LAST =3826, +  XED_IFORMFL_VCVTPH2PD_LAST =3691,
-  XED_IFORMFL_VCVTUQQ2PD_FIRST =3827, +  XED_IFORMFL_VCVTPH2PS_FIRST =3692,
-  XED_IFORMFL_VCVTUQQ2PD_LAST =3832, +  XED_IFORMFL_VCVTPH2PS_LAST =3702,
-  XED_IFORMFL_VCVTUQQ2PH_FIRST =3833, +  XED_IFORMFL_VCVTPH2PSX_FIRST =3703,
-  XED_IFORMFL_VCVTUQQ2PH_LAST =3838, +  XED_IFORMFL_VCVTPH2PSX_LAST =3709,
-  XED_IFORMFL_VCVTUQQ2PS_FIRST =3839, +  XED_IFORMFL_VCVTPH2QQ_FIRST =3710,
-  XED_IFORMFL_VCVTUQQ2PS_LAST =3844, +  XED_IFORMFL_VCVTPH2QQ_LAST =3716,
-  XED_IFORMFL_VCVTUSI2SD_FIRST =3845, +  XED_IFORMFL_VCVTPH2UDQ_FIRST =3717,
-  XED_IFORMFL_VCVTUSI2SD_LAST =3848, +  XED_IFORMFL_VCVTPH2UDQ_LAST =3723,
-  XED_IFORMFL_VCVTUSI2SH_FIRST =3849, +  XED_IFORMFL_VCVTPH2UQQ_FIRST =3724,
-  XED_IFORMFL_VCVTUSI2SH_LAST =3852, +  XED_IFORMFL_VCVTPH2UQQ_LAST =3730,
-  XED_IFORMFL_VCVTUSI2SS_FIRST =3853, +  XED_IFORMFL_VCVTPH2UW_FIRST =3731,
-  XED_IFORMFL_VCVTUSI2SS_LAST =3856, +  XED_IFORMFL_VCVTPH2UW_LAST =3737,
-  XED_IFORMFL_VCVTUW2PH_FIRST =3857, +  XED_IFORMFL_VCVTPH2W_FIRST =3738,
-  XED_IFORMFL_VCVTUW2PH_LAST =3862, +  XED_IFORMFL_VCVTPH2W_LAST =3744,
-  XED_IFORMFL_VCVTW2PH_FIRST =3863, +  XED_IFORMFL_VCVTPS2DQ_FIRST =3745,
-  XED_IFORMFL_VCVTW2PH_LAST =3868, +  XED_IFORMFL_VCVTPS2DQ_LAST =3755,
-  XED_IFORMFL_VDBPSADBW_FIRST =3869, +  XED_IFORMFL_VCVTPS2IBS_FIRST =3756,
-  XED_IFORMFL_VDBPSADBW_LAST =3874, +  XED_IFORMFL_VCVTPS2IBS_LAST =3761,
-  XED_IFORMFL_VDIVPD_FIRST =3875, +  XED_IFORMFL_VCVTPS2IUBS_FIRST =3762,
-  XED_IFORMFL_VDIVPD_LAST =3884, +  XED_IFORMFL_VCVTPS2IUBS_LAST =3767,
-  XED_IFORMFL_VDIVPH_FIRST =3885, +  XED_IFORMFL_VCVTPS2PD_FIRST =3768,
-  XED_IFORMFL_VDIVPH_LAST =3890, +  XED_IFORMFL_VCVTPS2PD_LAST =3778,
-  XED_IFORMFL_VDIVPS_FIRST =3891, +  XED_IFORMFL_VCVTPS2PH_FIRST =3779,
-  XED_IFORMFL_VDIVPS_LAST =3900, +  XED_IFORMFL_VCVTPS2PH_LAST =3789,
-  XED_IFORMFL_VDIVSD_FIRST =3901, +  XED_IFORMFL_VCVTPS2PHX_FIRST =3790,
-  XED_IFORMFL_VDIVSD_LAST =3904, +  XED_IFORMFL_VCVTPS2PHX_LAST =3796,
-  XED_IFORMFL_VDIVSH_FIRST =3905, +  XED_IFORMFL_VCVTPS2QQ_FIRST =3797,
-  XED_IFORMFL_VDIVSH_LAST =3906, +  XED_IFORMFL_VCVTPS2QQ_LAST =3803,
-  XED_IFORMFL_VDIVSS_FIRST =3907, +  XED_IFORMFL_VCVTPS2UDQ_FIRST =3804,
-  XED_IFORMFL_VDIVSS_LAST =3910, +  XED_IFORMFL_VCVTPS2UDQ_LAST =3810,
-  XED_IFORMFL_VDPBF16PS_FIRST =3911, +  XED_IFORMFL_VCVTPS2UQQ_FIRST =3811,
-  XED_IFORMFL_VDPBF16PS_LAST =3916, +  XED_IFORMFL_VCVTPS2UQQ_LAST =3817,
-  XED_IFORMFL_VDPPD_FIRST =3917, +  XED_IFORMFL_VCVTQQ2PD_FIRST =3818,
-  XED_IFORMFL_VDPPD_LAST =3918, +  XED_IFORMFL_VCVTQQ2PD_LAST =3824,
-  XED_IFORMFL_VDPPS_FIRST =3919, +  XED_IFORMFL_VCVTQQ2PH_FIRST =3825,
-  XED_IFORMFL_VDPPS_LAST =3922, +  XED_IFORMFL_VCVTQQ2PH_LAST =3831,
-  XED_IFORMFL_VERR_FIRST =3923, +  XED_IFORMFL_VCVTQQ2PS_FIRST =3832,
-  XED_IFORMFL_VERR_LAST =3924, +  XED_IFORMFL_VCVTQQ2PS_LAST =3838,
-  XED_IFORMFL_VERW_FIRST =3925, +  XED_IFORMFL_VCVTSD2SH_FIRST =3839,
-  XED_IFORMFL_VERW_LAST =3926, +  XED_IFORMFL_VCVTSD2SH_LAST =3841,
-  XED_IFORMFL_VEXP2PD_FIRST =3927, +  XED_IFORMFL_VCVTSD2SI_FIRST =3842,
-  XED_IFORMFL_VEXP2PD_LAST =3928, +  XED_IFORMFL_VCVTSD2SI_LAST =3851,
-  XED_IFORMFL_VEXP2PS_FIRST =3929, +  XED_IFORMFL_VCVTSD2SS_FIRST =3852,
-  XED_IFORMFL_VEXP2PS_LAST =3930, +  XED_IFORMFL_VCVTSD2SS_LAST =3856,
-  XED_IFORMFL_VEXPANDPD_FIRST =3931, +  XED_IFORMFL_VCVTSD2USI_FIRST =3857,
-  XED_IFORMFL_VEXPANDPD_LAST =3936, +  XED_IFORMFL_VCVTSD2USI_LAST =3862,
-  XED_IFORMFL_VEXPANDPS_FIRST =3937, +  XED_IFORMFL_VCVTSH2SD_FIRST =3863,
-  XED_IFORMFL_VEXPANDPS_LAST =3942, +  XED_IFORMFL_VCVTSH2SD_LAST =3865,
-  XED_IFORMFL_VEXTRACTF128_FIRST =3943, +  XED_IFORMFL_VCVTSH2SI_FIRST =3866,
-  XED_IFORMFL_VEXTRACTF128_LAST =3944, +  XED_IFORMFL_VCVTSH2SI_LAST =3871,
-  XED_IFORMFL_VEXTRACTF32X4_FIRST =3945, +  XED_IFORMFL_VCVTSH2SS_FIRST =3872,
-  XED_IFORMFL_VEXTRACTF32X4_LAST =3948, +  XED_IFORMFL_VCVTSH2SS_LAST =3874,
-  XED_IFORMFL_VEXTRACTF32X8_FIRST =3949, +  XED_IFORMFL_VCVTSH2USI_FIRST =3875,
-  XED_IFORMFL_VEXTRACTF32X8_LAST =3950, +  XED_IFORMFL_VCVTSH2USI_LAST =3880,
-  XED_IFORMFL_VEXTRACTF64X2_FIRST =3951, +  XED_IFORMFL_VCVTSI2SD_FIRST =3881,
-  XED_IFORMFL_VEXTRACTF64X2_LAST =3954, +  XED_IFORMFL_VCVTSI2SD_LAST =3890,
-  XED_IFORMFL_VEXTRACTF64X4_FIRST =3955, +  XED_IFORMFL_VCVTSI2SH_FIRST =3891,
-  XED_IFORMFL_VEXTRACTF64X4_LAST =3956, +  XED_IFORMFL_VCVTSI2SH_LAST =3896,
-  XED_IFORMFL_VEXTRACTI128_FIRST =3957, +  XED_IFORMFL_VCVTSI2SS_FIRST =3897,
-  XED_IFORMFL_VEXTRACTI128_LAST =3958, +  XED_IFORMFL_VCVTSI2SS_LAST =3906,
-  XED_IFORMFL_VEXTRACTI32X4_FIRST =3959, +  XED_IFORMFL_VCVTSS2SD_FIRST =3907,
-  XED_IFORMFL_VEXTRACTI32X4_LAST =3962, +  XED_IFORMFL_VCVTSS2SD_LAST =3911,
-  XED_IFORMFL_VEXTRACTI32X8_FIRST =3963, +  XED_IFORMFL_VCVTSS2SH_FIRST =3912,
-  XED_IFORMFL_VEXTRACTI32X8_LAST =3964, +  XED_IFORMFL_VCVTSS2SH_LAST =3914,
-  XED_IFORMFL_VEXTRACTI64X2_FIRST =3965, +  XED_IFORMFL_VCVTSS2SI_FIRST =3915,
-  XED_IFORMFL_VEXTRACTI64X2_LAST =3968, +  XED_IFORMFL_VCVTSS2SI_LAST =3924,
-  XED_IFORMFL_VEXTRACTI64X4_FIRST =3969, +  XED_IFORMFL_VCVTSS2USI_FIRST =3925,
-  XED_IFORMFL_VEXTRACTI64X4_LAST =3970, +  XED_IFORMFL_VCVTSS2USI_LAST =3930,
-  XED_IFORMFL_VEXTRACTPS_FIRST =3971, +  XED_IFORMFL_VCVTTNEBF162IBS_FIRST =3931,
-  XED_IFORMFL_VEXTRACTPS_LAST =3974, +  XED_IFORMFL_VCVTTNEBF162IBS_LAST =3936,
-  XED_IFORMFL_VFCMADDCPH_FIRST =3975, +  XED_IFORMFL_VCVTTNEBF162IUBS_FIRST =3937,
-  XED_IFORMFL_VFCMADDCPH_LAST =3980, +  XED_IFORMFL_VCVTTNEBF162IUBS_LAST =3942,
-  XED_IFORMFL_VFCMADDCSH_FIRST =3981, +  XED_IFORMFL_VCVTTPD2DQ_FIRST =3943,
-  XED_IFORMFL_VFCMADDCSH_LAST =3982, +  XED_IFORMFL_VCVTTPD2DQ_LAST =3953,
-  XED_IFORMFL_VFCMULCPH_FIRST =3983, +  XED_IFORMFL_VCVTTPD2DQS_FIRST =3954,
-  XED_IFORMFL_VFCMULCPH_LAST =3988, +  XED_IFORMFL_VCVTTPD2DQS_LAST =3959,
-  XED_IFORMFL_VFCMULCSH_FIRST =3989, +  XED_IFORMFL_VCVTTPD2QQ_FIRST =3960,
-  XED_IFORMFL_VFCMULCSH_LAST =3990, +  XED_IFORMFL_VCVTTPD2QQ_LAST =3966,
-  XED_IFORMFL_VFIXUPIMMPD_FIRST =3991, +  XED_IFORMFL_VCVTTPD2QQS_FIRST =3967,
-  XED_IFORMFL_VFIXUPIMMPD_LAST =3996, +  XED_IFORMFL_VCVTTPD2QQS_LAST =3972,
-  XED_IFORMFL_VFIXUPIMMPS_FIRST =3997, +  XED_IFORMFL_VCVTTPD2UDQ_FIRST =3973,
-  XED_IFORMFL_VFIXUPIMMPS_LAST =4002, +  XED_IFORMFL_VCVTTPD2UDQ_LAST =3979,
-  XED_IFORMFL_VFIXUPIMMSD_FIRST =4003, +  XED_IFORMFL_VCVTTPD2UDQS_FIRST =3980,
-  XED_IFORMFL_VFIXUPIMMSD_LAST =4004, +  XED_IFORMFL_VCVTTPD2UDQS_LAST =3985,
-  XED_IFORMFL_VFIXUPIMMSS_FIRST =4005, +  XED_IFORMFL_VCVTTPD2UQQ_FIRST =3986,
-  XED_IFORMFL_VFIXUPIMMSS_LAST =4006, +  XED_IFORMFL_VCVTTPD2UQQ_LAST =3992,
-  XED_IFORMFL_VFMADD132PD_FIRST =4007, +  XED_IFORMFL_VCVTTPD2UQQS_FIRST =3993,
-  XED_IFORMFL_VFMADD132PD_LAST =4016, +  XED_IFORMFL_VCVTTPD2UQQS_LAST =3998,
-  XED_IFORMFL_VFMADD132PH_FIRST =4017, +  XED_IFORMFL_VCVTTPH2DQ_FIRST =3999,
-  XED_IFORMFL_VFMADD132PH_LAST =4022, +  XED_IFORMFL_VCVTTPH2DQ_LAST =4005,
-  XED_IFORMFL_VFMADD132PS_FIRST =4023, +  XED_IFORMFL_VCVTTPH2IBS_FIRST =4006,
-  XED_IFORMFL_VFMADD132PS_LAST =4032, +  XED_IFORMFL_VCVTTPH2IBS_LAST =4011,
-  XED_IFORMFL_VFMADD132SD_FIRST =4033, +  XED_IFORMFL_VCVTTPH2IUBS_FIRST =4012,
-  XED_IFORMFL_VFMADD132SD_LAST =4036, +  XED_IFORMFL_VCVTTPH2IUBS_LAST =4017,
-  XED_IFORMFL_VFMADD132SH_FIRST =4037, +  XED_IFORMFL_VCVTTPH2QQ_FIRST =4018,
-  XED_IFORMFL_VFMADD132SH_LAST =4038, +  XED_IFORMFL_VCVTTPH2QQ_LAST =4024,
-  XED_IFORMFL_VFMADD132SS_FIRST =4039, +  XED_IFORMFL_VCVTTPH2UDQ_FIRST =4025,
-  XED_IFORMFL_VFMADD132SS_LAST =4042, +  XED_IFORMFL_VCVTTPH2UDQ_LAST =4031,
-  XED_IFORMFL_VFMADD213PD_FIRST =4043, +  XED_IFORMFL_VCVTTPH2UQQ_FIRST =4032,
-  XED_IFORMFL_VFMADD213PD_LAST =4052, +  XED_IFORMFL_VCVTTPH2UQQ_LAST =4038,
-  XED_IFORMFL_VFMADD213PH_FIRST =4053, +  XED_IFORMFL_VCVTTPH2UW_FIRST =4039,
-  XED_IFORMFL_VFMADD213PH_LAST =4058, +  XED_IFORMFL_VCVTTPH2UW_LAST =4045,
-  XED_IFORMFL_VFMADD213PS_FIRST =4059, +  XED_IFORMFL_VCVTTPH2W_FIRST =4046,
-  XED_IFORMFL_VFMADD213PS_LAST =4068, +  XED_IFORMFL_VCVTTPH2W_LAST =4052,
-  XED_IFORMFL_VFMADD213SD_FIRST =4069, +  XED_IFORMFL_VCVTTPS2DQ_FIRST =4053,
-  XED_IFORMFL_VFMADD213SD_LAST =4072, +  XED_IFORMFL_VCVTTPS2DQ_LAST =4063,
-  XED_IFORMFL_VFMADD213SH_FIRST =4073, +  XED_IFORMFL_VCVTTPS2DQS_FIRST =4064,
-  XED_IFORMFL_VFMADD213SH_LAST =4074, +  XED_IFORMFL_VCVTTPS2DQS_LAST =4069,
-  XED_IFORMFL_VFMADD213SS_FIRST =4075, +  XED_IFORMFL_VCVTTPS2IBS_FIRST =4070,
-  XED_IFORMFL_VFMADD213SS_LAST =4078, +  XED_IFORMFL_VCVTTPS2IBS_LAST =4075,
-  XED_IFORMFL_VFMADD231PD_FIRST =4079, +  XED_IFORMFL_VCVTTPS2IUBS_FIRST =4076,
-  XED_IFORMFL_VFMADD231PD_LAST =4088, +  XED_IFORMFL_VCVTTPS2IUBS_LAST =4081,
-  XED_IFORMFL_VFMADD231PH_FIRST =4089, +  XED_IFORMFL_VCVTTPS2QQ_FIRST =4082,
-  XED_IFORMFL_VFMADD231PH_LAST =4094, +  XED_IFORMFL_VCVTTPS2QQ_LAST =4088,
-  XED_IFORMFL_VFMADD231PS_FIRST =4095, +  XED_IFORMFL_VCVTTPS2QQS_FIRST =4089,
-  XED_IFORMFL_VFMADD231PS_LAST =4104, +  XED_IFORMFL_VCVTTPS2QQS_LAST =4094,
-  XED_IFORMFL_VFMADD231SD_FIRST =4105, +  XED_IFORMFL_VCVTTPS2UDQ_FIRST =4095,
-  XED_IFORMFL_VFMADD231SD_LAST =4108, +  XED_IFORMFL_VCVTTPS2UDQ_LAST =4101,
-  XED_IFORMFL_VFMADD231SH_FIRST =4109, +  XED_IFORMFL_VCVTTPS2UDQS_FIRST =4102,
-  XED_IFORMFL_VFMADD231SH_LAST =4110, +  XED_IFORMFL_VCVTTPS2UDQS_LAST =4107,
-  XED_IFORMFL_VFMADD231SS_FIRST =4111, +  XED_IFORMFL_VCVTTPS2UQQ_FIRST =4108,
-  XED_IFORMFL_VFMADD231SS_LAST =4114, +  XED_IFORMFL_VCVTTPS2UQQ_LAST =4114,
-  XED_IFORMFL_VFMADDCPH_FIRST =4115, +  XED_IFORMFL_VCVTTPS2UQQS_FIRST =4115,
-  XED_IFORMFL_VFMADDCPH_LAST =4120, +  XED_IFORMFL_VCVTTPS2UQQS_LAST =4120,
-  XED_IFORMFL_VFMADDCSH_FIRST =4121, +  XED_IFORMFL_VCVTTSD2SI_FIRST =4121,
-  XED_IFORMFL_VFMADDCSH_LAST =4122, +  XED_IFORMFL_VCVTTSD2SI_LAST =4130,
-  XED_IFORMFL_VFMADDPD_FIRST =4123, +  XED_IFORMFL_VCVTTSD2SIS_FIRST =4131,
-  XED_IFORMFL_VFMADDPD_LAST =4128, +  XED_IFORMFL_VCVTTSD2SIS_LAST =4134,
-  XED_IFORMFL_VFMADDPS_FIRST =4129, +  XED_IFORMFL_VCVTTSD2USI_FIRST =4135,
-  XED_IFORMFL_VFMADDPS_LAST =4134, +  XED_IFORMFL_VCVTTSD2USI_LAST =4140,
-  XED_IFORMFL_VFMADDSD_FIRST =4135, +  XED_IFORMFL_VCVTTSD2USIS_FIRST =4141,
-  XED_IFORMFL_VFMADDSD_LAST =4137, +  XED_IFORMFL_VCVTTSD2USIS_LAST =4144,
-  XED_IFORMFL_VFMADDSS_FIRST =4138, +  XED_IFORMFL_VCVTTSH2SI_FIRST =4145,
-  XED_IFORMFL_VFMADDSS_LAST =4140, +  XED_IFORMFL_VCVTTSH2SI_LAST =4150,
-  XED_IFORMFL_VFMADDSUB132PD_FIRST =4141, +  XED_IFORMFL_VCVTTSH2USI_FIRST =4151,
-  XED_IFORMFL_VFMADDSUB132PD_LAST =4150, +  XED_IFORMFL_VCVTTSH2USI_LAST =4156,
-  XED_IFORMFL_VFMADDSUB132PH_FIRST =4151, +  XED_IFORMFL_VCVTTSS2SI_FIRST =4157,
-  XED_IFORMFL_VFMADDSUB132PH_LAST =4156, +  XED_IFORMFL_VCVTTSS2SI_LAST =4166,
-  XED_IFORMFL_VFMADDSUB132PS_FIRST =4157, +  XED_IFORMFL_VCVTTSS2SIS_FIRST =4167,
-  XED_IFORMFL_VFMADDSUB132PS_LAST =4166, +  XED_IFORMFL_VCVTTSS2SIS_LAST =4170,
-  XED_IFORMFL_VFMADDSUB213PD_FIRST =4167, +  XED_IFORMFL_VCVTTSS2USI_FIRST =4171,
-  XED_IFORMFL_VFMADDSUB213PD_LAST =4176, +  XED_IFORMFL_VCVTTSS2USI_LAST =4176,
-  XED_IFORMFL_VFMADDSUB213PH_FIRST =4177, +  XED_IFORMFL_VCVTTSS2USIS_FIRST =4177,
-  XED_IFORMFL_VFMADDSUB213PH_LAST =4182, +  XED_IFORMFL_VCVTTSS2USIS_LAST =4180,
-  XED_IFORMFL_VFMADDSUB213PS_FIRST =4183, +  XED_IFORMFL_VCVTUDQ2PD_FIRST =4181,
-  XED_IFORMFL_VFMADDSUB213PS_LAST =4192, +  XED_IFORMFL_VCVTUDQ2PD_LAST =4187,
-  XED_IFORMFL_VFMADDSUB231PD_FIRST =4193, +  XED_IFORMFL_VCVTUDQ2PH_FIRST =4188,
-  XED_IFORMFL_VFMADDSUB231PD_LAST =4202, +  XED_IFORMFL_VCVTUDQ2PH_LAST =4194,
-  XED_IFORMFL_VFMADDSUB231PH_FIRST =4203, +  XED_IFORMFL_VCVTUDQ2PS_FIRST =4195,
-  XED_IFORMFL_VFMADDSUB231PH_LAST =4208, +  XED_IFORMFL_VCVTUDQ2PS_LAST =4201,
-  XED_IFORMFL_VFMADDSUB231PS_FIRST =4209, +  XED_IFORMFL_VCVTUQQ2PD_FIRST =4202,
-  XED_IFORMFL_VFMADDSUB231PS_LAST =4218, +  XED_IFORMFL_VCVTUQQ2PD_LAST =4208,
-  XED_IFORMFL_VFMADDSUBPD_FIRST =4219, +  XED_IFORMFL_VCVTUQQ2PH_FIRST =4209,
-  XED_IFORMFL_VFMADDSUBPD_LAST =4224, +  XED_IFORMFL_VCVTUQQ2PH_LAST =4215,
-  XED_IFORMFL_VFMADDSUBPS_FIRST =4225, +  XED_IFORMFL_VCVTUQQ2PS_FIRST =4216,
-  XED_IFORMFL_VFMADDSUBPS_LAST =4230, +  XED_IFORMFL_VCVTUQQ2PS_LAST =4222,
-  XED_IFORMFL_VFMSUB132PD_FIRST =4231, +  XED_IFORMFL_VCVTUSI2SD_FIRST =4223,
-  XED_IFORMFL_VFMSUB132PD_LAST =4240, +  XED_IFORMFL_VCVTUSI2SD_LAST =4228,
-  XED_IFORMFL_VFMSUB132PH_FIRST =4241, +  XED_IFORMFL_VCVTUSI2SH_FIRST =4229,
-  XED_IFORMFL_VFMSUB132PH_LAST =4246, +  XED_IFORMFL_VCVTUSI2SH_LAST =4234,
-  XED_IFORMFL_VFMSUB132PS_FIRST =4247, +  XED_IFORMFL_VCVTUSI2SS_FIRST =4235,
-  XED_IFORMFL_VFMSUB132PS_LAST =4256, +  XED_IFORMFL_VCVTUSI2SS_LAST =4240,
-  XED_IFORMFL_VFMSUB132SD_FIRST =4257, +  XED_IFORMFL_VCVTUW2PH_FIRST =4241,
-  XED_IFORMFL_VFMSUB132SD_LAST =4260, +  XED_IFORMFL_VCVTUW2PH_LAST =4247,
-  XED_IFORMFL_VFMSUB132SH_FIRST =4261, +  XED_IFORMFL_VCVTW2PH_FIRST =4248,
-  XED_IFORMFL_VFMSUB132SH_LAST =4262, +  XED_IFORMFL_VCVTW2PH_LAST =4254,
-  XED_IFORMFL_VFMSUB132SS_FIRST =4263, +  XED_IFORMFL_VDBPSADBW_FIRST =4255,
-  XED_IFORMFL_VFMSUB132SS_LAST =4266, +  XED_IFORMFL_VDBPSADBW_LAST =4260,
-  XED_IFORMFL_VFMSUB213PD_FIRST =4267, +  XED_IFORMFL_VDIVNEPBF16_FIRST =4261,
-  XED_IFORMFL_VFMSUB213PD_LAST =4276, +  XED_IFORMFL_VDIVNEPBF16_LAST =4266,
-  XED_IFORMFL_VFMSUB213PH_FIRST =4277, +  XED_IFORMFL_VDIVPD_FIRST =4267,
-  XED_IFORMFL_VFMSUB213PH_LAST =4282, +  XED_IFORMFL_VDIVPD_LAST =4277,
-  XED_IFORMFL_VFMSUB213PS_FIRST =4283, +  XED_IFORMFL_VDIVPH_FIRST =4278,
-  XED_IFORMFL_VFMSUB213PS_LAST =4292, +  XED_IFORMFL_VDIVPH_LAST =4284,
-  XED_IFORMFL_VFMSUB213SD_FIRST =4293, +  XED_IFORMFL_VDIVPS_FIRST =4285,
-  XED_IFORMFL_VFMSUB213SD_LAST =4296, +  XED_IFORMFL_VDIVPS_LAST =4295,
-  XED_IFORMFL_VFMSUB213SH_FIRST =4297, +  XED_IFORMFL_VDIVSD_FIRST =4296,
-  XED_IFORMFL_VFMSUB213SH_LAST =4298, +  XED_IFORMFL_VDIVSD_LAST =4300,
-  XED_IFORMFL_VFMSUB213SS_FIRST =4299, +  XED_IFORMFL_VDIVSH_FIRST =4301,
-  XED_IFORMFL_VFMSUB213SS_LAST =4302, +  XED_IFORMFL_VDIVSH_LAST =4303,
-  XED_IFORMFL_VFMSUB231PD_FIRST =4303, +  XED_IFORMFL_VDIVSS_FIRST =4304,
-  XED_IFORMFL_VFMSUB231PD_LAST =4312, +  XED_IFORMFL_VDIVSS_LAST =4308,
-  XED_IFORMFL_VFMSUB231PH_FIRST =4313, +  XED_IFORMFL_VDPBF16PS_FIRST =4309,
-  XED_IFORMFL_VFMSUB231PH_LAST =4318, +  XED_IFORMFL_VDPBF16PS_LAST =4314,
-  XED_IFORMFL_VFMSUB231PS_FIRST =4319, +  XED_IFORMFL_VDPPD_FIRST =4315,
-  XED_IFORMFL_VFMSUB231PS_LAST =4328, +  XED_IFORMFL_VDPPD_LAST =4316,
-  XED_IFORMFL_VFMSUB231SD_FIRST =4329, +  XED_IFORMFL_VDPPHPS_FIRST =4317,
-  XED_IFORMFL_VFMSUB231SD_LAST =4332, +  XED_IFORMFL_VDPPHPS_LAST =4322,
-  XED_IFORMFL_VFMSUB231SH_FIRST =4333, +  XED_IFORMFL_VDPPS_FIRST =4323,
-  XED_IFORMFL_VFMSUB231SH_LAST =4334, +  XED_IFORMFL_VDPPS_LAST =4326,
-  XED_IFORMFL_VFMSUB231SS_FIRST =4335, +  XED_IFORMFL_VERR_FIRST =4327,
-  XED_IFORMFL_VFMSUB231SS_LAST =4338, +  XED_IFORMFL_VERR_LAST =4328,
-  XED_IFORMFL_VFMSUBADD132PD_FIRST =4339, +  XED_IFORMFL_VERW_FIRST =4329,
-  XED_IFORMFL_VFMSUBADD132PD_LAST =4348, +  XED_IFORMFL_VERW_LAST =4330,
-  XED_IFORMFL_VFMSUBADD132PH_FIRST =4349, +  XED_IFORMFL_VEXP2PD_FIRST =4331,
-  XED_IFORMFL_VFMSUBADD132PH_LAST =4354, +  XED_IFORMFL_VEXP2PD_LAST =4332,
-  XED_IFORMFL_VFMSUBADD132PS_FIRST =4355, +  XED_IFORMFL_VEXP2PS_FIRST =4333,
-  XED_IFORMFL_VFMSUBADD132PS_LAST =4364, +  XED_IFORMFL_VEXP2PS_LAST =4334,
-  XED_IFORMFL_VFMSUBADD213PD_FIRST =4365, +  XED_IFORMFL_VEXPANDPD_FIRST =4335,
-  XED_IFORMFL_VFMSUBADD213PD_LAST =4374, +  XED_IFORMFL_VEXPANDPD_LAST =4340,
-  XED_IFORMFL_VFMSUBADD213PH_FIRST =4375, +  XED_IFORMFL_VEXPANDPS_FIRST =4341,
-  XED_IFORMFL_VFMSUBADD213PH_LAST =4380, +  XED_IFORMFL_VEXPANDPS_LAST =4346,
-  XED_IFORMFL_VFMSUBADD213PS_FIRST =4381, +  XED_IFORMFL_VEXTRACTF128_FIRST =4347,
-  XED_IFORMFL_VFMSUBADD213PS_LAST =4390, +  XED_IFORMFL_VEXTRACTF128_LAST =4348,
-  XED_IFORMFL_VFMSUBADD231PD_FIRST =4391, +  XED_IFORMFL_VEXTRACTF32X4_FIRST =4349,
-  XED_IFORMFL_VFMSUBADD231PD_LAST =4400, +  XED_IFORMFL_VEXTRACTF32X4_LAST =4352,
-  XED_IFORMFL_VFMSUBADD231PH_FIRST =4401, +  XED_IFORMFL_VEXTRACTF32X8_FIRST =4353,
-  XED_IFORMFL_VFMSUBADD231PH_LAST =4406, +  XED_IFORMFL_VEXTRACTF32X8_LAST =4354,
-  XED_IFORMFL_VFMSUBADD231PS_FIRST =4407, +  XED_IFORMFL_VEXTRACTF64X2_FIRST =4355,
-  XED_IFORMFL_VFMSUBADD231PS_LAST =4416, +  XED_IFORMFL_VEXTRACTF64X2_LAST =4358,
-  XED_IFORMFL_VFMSUBADDPD_FIRST =4417, +  XED_IFORMFL_VEXTRACTF64X4_FIRST =4359,
-  XED_IFORMFL_VFMSUBADDPD_LAST =4422, +  XED_IFORMFL_VEXTRACTF64X4_LAST =4360,
-  XED_IFORMFL_VFMSUBADDPS_FIRST =4423, +  XED_IFORMFL_VEXTRACTI128_FIRST =4361,
-  XED_IFORMFL_VFMSUBADDPS_LAST =4428, +  XED_IFORMFL_VEXTRACTI128_LAST =4362,
-  XED_IFORMFL_VFMSUBPD_FIRST =4429, +  XED_IFORMFL_VEXTRACTI32X4_FIRST =4363,
-  XED_IFORMFL_VFMSUBPD_LAST =4434, +  XED_IFORMFL_VEXTRACTI32X4_LAST =4366,
-  XED_IFORMFL_VFMSUBPS_FIRST =4435, +  XED_IFORMFL_VEXTRACTI32X8_FIRST =4367,
-  XED_IFORMFL_VFMSUBPS_LAST =4440, +  XED_IFORMFL_VEXTRACTI32X8_LAST =4368,
-  XED_IFORMFL_VFMSUBSD_FIRST =4441, +  XED_IFORMFL_VEXTRACTI64X2_FIRST =4369,
-  XED_IFORMFL_VFMSUBSD_LAST =4443, +  XED_IFORMFL_VEXTRACTI64X2_LAST =4372,
-  XED_IFORMFL_VFMSUBSS_FIRST =4444, +  XED_IFORMFL_VEXTRACTI64X4_FIRST =4373,
-  XED_IFORMFL_VFMSUBSS_LAST =4446, +  XED_IFORMFL_VEXTRACTI64X4_LAST =4374,
-  XED_IFORMFL_VFMULCPH_FIRST =4447, +  XED_IFORMFL_VEXTRACTPS_FIRST =4375,
-  XED_IFORMFL_VFMULCPH_LAST =4452, +  XED_IFORMFL_VEXTRACTPS_LAST =4378,
-  XED_IFORMFL_VFMULCSH_FIRST =4453, +  XED_IFORMFL_VFCMADDCPH_FIRST =4379,
-  XED_IFORMFL_VFMULCSH_LAST =4454, +  XED_IFORMFL_VFCMADDCPH_LAST =4385,
-  XED_IFORMFL_VFNMADD132PD_FIRST =4455, +  XED_IFORMFL_VFCMADDCSH_FIRST =4386,
-  XED_IFORMFL_VFNMADD132PD_LAST =4464, +  XED_IFORMFL_VFCMADDCSH_LAST =4388,
-  XED_IFORMFL_VFNMADD132PH_FIRST =4465, +  XED_IFORMFL_VFCMULCPH_FIRST =4389,
-  XED_IFORMFL_VFNMADD132PH_LAST =4470, +  XED_IFORMFL_VFCMULCPH_LAST =4395,
-  XED_IFORMFL_VFNMADD132PS_FIRST =4471, +  XED_IFORMFL_VFCMULCSH_FIRST =4396,
-  XED_IFORMFL_VFNMADD132PS_LAST =4480, +  XED_IFORMFL_VFCMULCSH_LAST =4398,
-  XED_IFORMFL_VFNMADD132SD_FIRST =4481, +  XED_IFORMFL_VFIXUPIMMPD_FIRST =4399,
-  XED_IFORMFL_VFNMADD132SD_LAST =4484, +  XED_IFORMFL_VFIXUPIMMPD_LAST =4405,
-  XED_IFORMFL_VFNMADD132SH_FIRST =4485, +  XED_IFORMFL_VFIXUPIMMPS_FIRST =4406,
-  XED_IFORMFL_VFNMADD132SH_LAST =4486, +  XED_IFORMFL_VFIXUPIMMPS_LAST =4412,
-  XED_IFORMFL_VFNMADD132SS_FIRST =4487, +  XED_IFORMFL_VFIXUPIMMSD_FIRST =4413,
-  XED_IFORMFL_VFNMADD132SS_LAST =4490, +  XED_IFORMFL_VFIXUPIMMSD_LAST =4415,
-  XED_IFORMFL_VFNMADD213PD_FIRST =4491, +  XED_IFORMFL_VFIXUPIMMSS_FIRST =4416,
-  XED_IFORMFL_VFNMADD213PD_LAST =4500, +  XED_IFORMFL_VFIXUPIMMSS_LAST =4418,
-  XED_IFORMFL_VFNMADD213PH_FIRST =4501, +  XED_IFORMFL_VFMADD132NEPBF16_FIRST =4419,
-  XED_IFORMFL_VFNMADD213PH_LAST =4506, +  XED_IFORMFL_VFMADD132NEPBF16_LAST =4424,
-  XED_IFORMFL_VFNMADD213PS_FIRST =4507, +  XED_IFORMFL_VFMADD132PD_FIRST =4425,
-  XED_IFORMFL_VFNMADD213PS_LAST =4516, +  XED_IFORMFL_VFMADD132PD_LAST =4435,
-  XED_IFORMFL_VFNMADD213SD_FIRST =4517, +  XED_IFORMFL_VFMADD132PH_FIRST =4436,
-  XED_IFORMFL_VFNMADD213SD_LAST =4520, +  XED_IFORMFL_VFMADD132PH_LAST =4442,
-  XED_IFORMFL_VFNMADD213SH_FIRST =4521, +  XED_IFORMFL_VFMADD132PS_FIRST =4443,
-  XED_IFORMFL_VFNMADD213SH_LAST =4522, +  XED_IFORMFL_VFMADD132PS_LAST =4453,
-  XED_IFORMFL_VFNMADD213SS_FIRST =4523, +  XED_IFORMFL_VFMADD132SD_FIRST =4454,
-  XED_IFORMFL_VFNMADD213SS_LAST =4526, +  XED_IFORMFL_VFMADD132SD_LAST =4458,
-  XED_IFORMFL_VFNMADD231PD_FIRST =4527, +  XED_IFORMFL_VFMADD132SH_FIRST =4459,
-  XED_IFORMFL_VFNMADD231PD_LAST =4536, +  XED_IFORMFL_VFMADD132SH_LAST =4461,
-  XED_IFORMFL_VFNMADD231PH_FIRST =4537, +  XED_IFORMFL_VFMADD132SS_FIRST =4462,
-  XED_IFORMFL_VFNMADD231PH_LAST =4542, +  XED_IFORMFL_VFMADD132SS_LAST =4466,
-  XED_IFORMFL_VFNMADD231PS_FIRST =4543, +  XED_IFORMFL_VFMADD213NEPBF16_FIRST =4467,
-  XED_IFORMFL_VFNMADD231PS_LAST =4552, +  XED_IFORMFL_VFMADD213NEPBF16_LAST =4472,
-  XED_IFORMFL_VFNMADD231SD_FIRST =4553, +  XED_IFORMFL_VFMADD213PD_FIRST =4473,
-  XED_IFORMFL_VFNMADD231SD_LAST =4556, +  XED_IFORMFL_VFMADD213PD_LAST =4483,
-  XED_IFORMFL_VFNMADD231SH_FIRST =4557, +  XED_IFORMFL_VFMADD213PH_FIRST =4484,
-  XED_IFORMFL_VFNMADD231SH_LAST =4558, +  XED_IFORMFL_VFMADD213PH_LAST =4490,
-  XED_IFORMFL_VFNMADD231SS_FIRST =4559, +  XED_IFORMFL_VFMADD213PS_FIRST =4491,
-  XED_IFORMFL_VFNMADD231SS_LAST =4562, +  XED_IFORMFL_VFMADD213PS_LAST =4501,
-  XED_IFORMFL_VFNMADDPD_FIRST =4563, +  XED_IFORMFL_VFMADD213SD_FIRST =4502,
-  XED_IFORMFL_VFNMADDPD_LAST =4568, +  XED_IFORMFL_VFMADD213SD_LAST =4506,
-  XED_IFORMFL_VFNMADDPS_FIRST =4569, +  XED_IFORMFL_VFMADD213SH_FIRST =4507,
-  XED_IFORMFL_VFNMADDPS_LAST =4574, +  XED_IFORMFL_VFMADD213SH_LAST =4509,
-  XED_IFORMFL_VFNMADDSD_FIRST =4575, +  XED_IFORMFL_VFMADD213SS_FIRST =4510,
-  XED_IFORMFL_VFNMADDSD_LAST =4577, +  XED_IFORMFL_VFMADD213SS_LAST =4514,
-  XED_IFORMFL_VFNMADDSS_FIRST =4578, +  XED_IFORMFL_VFMADD231NEPBF16_FIRST =4515,
-  XED_IFORMFL_VFNMADDSS_LAST =4580, +  XED_IFORMFL_VFMADD231NEPBF16_LAST =4520,
-  XED_IFORMFL_VFNMSUB132PD_FIRST =4581, +  XED_IFORMFL_VFMADD231PD_FIRST =4521,
-  XED_IFORMFL_VFNMSUB132PD_LAST =4590, +  XED_IFORMFL_VFMADD231PD_LAST =4531,
-  XED_IFORMFL_VFNMSUB132PH_FIRST =4591, +  XED_IFORMFL_VFMADD231PH_FIRST =4532,
-  XED_IFORMFL_VFNMSUB132PH_LAST =4596, +  XED_IFORMFL_VFMADD231PH_LAST =4538,
-  XED_IFORMFL_VFNMSUB132PS_FIRST =4597, +  XED_IFORMFL_VFMADD231PS_FIRST =4539,
-  XED_IFORMFL_VFNMSUB132PS_LAST =4606, +  XED_IFORMFL_VFMADD231PS_LAST =4549,
-  XED_IFORMFL_VFNMSUB132SD_FIRST =4607, +  XED_IFORMFL_VFMADD231SD_FIRST =4550,
-  XED_IFORMFL_VFNMSUB132SD_LAST =4610, +  XED_IFORMFL_VFMADD231SD_LAST =4554,
-  XED_IFORMFL_VFNMSUB132SH_FIRST =4611, +  XED_IFORMFL_VFMADD231SH_FIRST =4555,
-  XED_IFORMFL_VFNMSUB132SH_LAST =4612, +  XED_IFORMFL_VFMADD231SH_LAST =4557,
-  XED_IFORMFL_VFNMSUB132SS_FIRST =4613, +  XED_IFORMFL_VFMADD231SS_FIRST =4558,
-  XED_IFORMFL_VFNMSUB132SS_LAST =4616, +  XED_IFORMFL_VFMADD231SS_LAST =4562,
-  XED_IFORMFL_VFNMSUB213PD_FIRST =4617, +  XED_IFORMFL_VFMADDCPH_FIRST =4563,
-  XED_IFORMFL_VFNMSUB213PD_LAST =4626, +  XED_IFORMFL_VFMADDCPH_LAST =4569,
-  XED_IFORMFL_VFNMSUB213PH_FIRST =4627, +  XED_IFORMFL_VFMADDCSH_FIRST =4570,
-  XED_IFORMFL_VFNMSUB213PH_LAST =4632, +  XED_IFORMFL_VFMADDCSH_LAST =4572,
-  XED_IFORMFL_VFNMSUB213PS_FIRST =4633, +  XED_IFORMFL_VFMADDPD_FIRST =4573,
-  XED_IFORMFL_VFNMSUB213PS_LAST =4642, +  XED_IFORMFL_VFMADDPD_LAST =4578,
-  XED_IFORMFL_VFNMSUB213SD_FIRST =4643, +  XED_IFORMFL_VFMADDPS_FIRST =4579,
-  XED_IFORMFL_VFNMSUB213SD_LAST =4646, +  XED_IFORMFL_VFMADDPS_LAST =4584,
-  XED_IFORMFL_VFNMSUB213SH_FIRST =4647, +  XED_IFORMFL_VFMADDSD_FIRST =4585,
-  XED_IFORMFL_VFNMSUB213SH_LAST =4648, +  XED_IFORMFL_VFMADDSD_LAST =4587,
-  XED_IFORMFL_VFNMSUB213SS_FIRST =4649, +  XED_IFORMFL_VFMADDSS_FIRST =4588,
-  XED_IFORMFL_VFNMSUB213SS_LAST =4652, +  XED_IFORMFL_VFMADDSS_LAST =4590,
-  XED_IFORMFL_VFNMSUB231PD_FIRST =4653, +  XED_IFORMFL_VFMADDSUB132PD_FIRST =4591,
-  XED_IFORMFL_VFNMSUB231PD_LAST =4662, +  XED_IFORMFL_VFMADDSUB132PD_LAST =4601,
-  XED_IFORMFL_VFNMSUB231PH_FIRST =4663, +  XED_IFORMFL_VFMADDSUB132PH_FIRST =4602,
-  XED_IFORMFL_VFNMSUB231PH_LAST =4668, +  XED_IFORMFL_VFMADDSUB132PH_LAST =4608,
-  XED_IFORMFL_VFNMSUB231PS_FIRST =4669, +  XED_IFORMFL_VFMADDSUB132PS_FIRST =4609,
-  XED_IFORMFL_VFNMSUB231PS_LAST =4678, +  XED_IFORMFL_VFMADDSUB132PS_LAST =4619,
-  XED_IFORMFL_VFNMSUB231SD_FIRST =4679, +  XED_IFORMFL_VFMADDSUB213PD_FIRST =4620,
-  XED_IFORMFL_VFNMSUB231SD_LAST =4682, +  XED_IFORMFL_VFMADDSUB213PD_LAST =4630,
-  XED_IFORMFL_VFNMSUB231SH_FIRST =4683, +  XED_IFORMFL_VFMADDSUB213PH_FIRST =4631,
-  XED_IFORMFL_VFNMSUB231SH_LAST =4684, +  XED_IFORMFL_VFMADDSUB213PH_LAST =4637,
-  XED_IFORMFL_VFNMSUB231SS_FIRST =4685, +  XED_IFORMFL_VFMADDSUB213PS_FIRST =4638,
-  XED_IFORMFL_VFNMSUB231SS_LAST =4688, +  XED_IFORMFL_VFMADDSUB213PS_LAST =4648,
-  XED_IFORMFL_VFNMSUBPD_FIRST =4689, +  XED_IFORMFL_VFMADDSUB231PD_FIRST =4649,
-  XED_IFORMFL_VFNMSUBPD_LAST =4694, +  XED_IFORMFL_VFMADDSUB231PD_LAST =4659,
-  XED_IFORMFL_VFNMSUBPS_FIRST =4695, +  XED_IFORMFL_VFMADDSUB231PH_FIRST =4660,
-  XED_IFORMFL_VFNMSUBPS_LAST =4700, +  XED_IFORMFL_VFMADDSUB231PH_LAST =4666,
-  XED_IFORMFL_VFNMSUBSD_FIRST =4701, +  XED_IFORMFL_VFMADDSUB231PS_FIRST =4667,
-  XED_IFORMFL_VFNMSUBSD_LAST =4703, +  XED_IFORMFL_VFMADDSUB231PS_LAST =4677,
-  XED_IFORMFL_VFNMSUBSS_FIRST =4704, +  XED_IFORMFL_VFMADDSUBPD_FIRST =4678,
-  XED_IFORMFL_VFNMSUBSS_LAST =4706, +  XED_IFORMFL_VFMADDSUBPD_LAST =4683,
-  XED_IFORMFL_VFPCLASSPD_FIRST =4707, +  XED_IFORMFL_VFMADDSUBPS_FIRST =4684,
-  XED_IFORMFL_VFPCLASSPD_LAST =4712, +  XED_IFORMFL_VFMADDSUBPS_LAST =4689,
-  XED_IFORMFL_VFPCLASSPH_FIRST =4713, +  XED_IFORMFL_VFMSUB132NEPBF16_FIRST =4690,
-  XED_IFORMFL_VFPCLASSPH_LAST =4718, +  XED_IFORMFL_VFMSUB132NEPBF16_LAST =4695,
-  XED_IFORMFL_VFPCLASSPS_FIRST =4719, +  XED_IFORMFL_VFMSUB132PD_FIRST =4696,
-  XED_IFORMFL_VFPCLASSPS_LAST =4724, +  XED_IFORMFL_VFMSUB132PD_LAST =4706,
-  XED_IFORMFL_VFPCLASSSD_FIRST =4725, +  XED_IFORMFL_VFMSUB132PH_FIRST =4707,
-  XED_IFORMFL_VFPCLASSSD_LAST =4726, +  XED_IFORMFL_VFMSUB132PH_LAST =4713,
-  XED_IFORMFL_VFPCLASSSH_FIRST =4727, +  XED_IFORMFL_VFMSUB132PS_FIRST =4714,
-  XED_IFORMFL_VFPCLASSSH_LAST =4728, +  XED_IFORMFL_VFMSUB132PS_LAST =4724,
-  XED_IFORMFL_VFPCLASSSS_FIRST =4729, +  XED_IFORMFL_VFMSUB132SD_FIRST =4725,
-  XED_IFORMFL_VFPCLASSSS_LAST =4730, +  XED_IFORMFL_VFMSUB132SD_LAST =4729,
-  XED_IFORMFL_VFRCZPD_FIRST =4731, +  XED_IFORMFL_VFMSUB132SH_FIRST =4730,
-  XED_IFORMFL_VFRCZPD_LAST =4734, +  XED_IFORMFL_VFMSUB132SH_LAST =4732,
-  XED_IFORMFL_VFRCZPS_FIRST =4735, +  XED_IFORMFL_VFMSUB132SS_FIRST =4733,
-  XED_IFORMFL_VFRCZPS_LAST =4738, +  XED_IFORMFL_VFMSUB132SS_LAST =4737,
-  XED_IFORMFL_VFRCZSD_FIRST =4739, +  XED_IFORMFL_VFMSUB213NEPBF16_FIRST =4738,
-  XED_IFORMFL_VFRCZSD_LAST =4740, +  XED_IFORMFL_VFMSUB213NEPBF16_LAST =4743,
-  XED_IFORMFL_VFRCZSS_FIRST =4741, +  XED_IFORMFL_VFMSUB213PD_FIRST =4744,
-  XED_IFORMFL_VFRCZSS_LAST =4742, +  XED_IFORMFL_VFMSUB213PD_LAST =4754,
-  XED_IFORMFL_VGATHERDPD_FIRST =4743, +  XED_IFORMFL_VFMSUB213PH_FIRST =4755,
-  XED_IFORMFL_VGATHERDPD_LAST =4747, +  XED_IFORMFL_VFMSUB213PH_LAST =4761,
-  XED_IFORMFL_VGATHERDPS_FIRST =4748, +  XED_IFORMFL_VFMSUB213PS_FIRST =4762,
-  XED_IFORMFL_VGATHERDPS_LAST =4752, +  XED_IFORMFL_VFMSUB213PS_LAST =4772,
-  XED_IFORMFL_VGATHERPF0DPD_FIRST =4753, +  XED_IFORMFL_VFMSUB213SD_FIRST =4773,
-  XED_IFORMFL_VGATHERPF0DPD_LAST =4753, +  XED_IFORMFL_VFMSUB213SD_LAST =4777,
-  XED_IFORMFL_VGATHERPF0DPS_FIRST =4754, +  XED_IFORMFL_VFMSUB213SH_FIRST =4778,
-  XED_IFORMFL_VGATHERPF0DPS_LAST =4754, +  XED_IFORMFL_VFMSUB213SH_LAST =4780,
-  XED_IFORMFL_VGATHERPF0QPD_FIRST =4755, +  XED_IFORMFL_VFMSUB213SS_FIRST =4781,
-  XED_IFORMFL_VGATHERPF0QPD_LAST =4755, +  XED_IFORMFL_VFMSUB213SS_LAST =4785,
-  XED_IFORMFL_VGATHERPF0QPS_FIRST =4756, +  XED_IFORMFL_VFMSUB231NEPBF16_FIRST =4786,
-  XED_IFORMFL_VGATHERPF0QPS_LAST =4756, +  XED_IFORMFL_VFMSUB231NEPBF16_LAST =4791,
-  XED_IFORMFL_VGATHERPF1DPD_FIRST =4757, +  XED_IFORMFL_VFMSUB231PD_FIRST =4792,
-  XED_IFORMFL_VGATHERPF1DPD_LAST =4757, +  XED_IFORMFL_VFMSUB231PD_LAST =4802,
-  XED_IFORMFL_VGATHERPF1DPS_FIRST =4758, +  XED_IFORMFL_VFMSUB231PH_FIRST =4803,
-  XED_IFORMFL_VGATHERPF1DPS_LAST =4758, +  XED_IFORMFL_VFMSUB231PH_LAST =4809,
-  XED_IFORMFL_VGATHERPF1QPD_FIRST =4759, +  XED_IFORMFL_VFMSUB231PS_FIRST =4810,
-  XED_IFORMFL_VGATHERPF1QPD_LAST =4759, +  XED_IFORMFL_VFMSUB231PS_LAST =4820,
-  XED_IFORMFL_VGATHERPF1QPS_FIRST =4760, +  XED_IFORMFL_VFMSUB231SD_FIRST =4821,
-  XED_IFORMFL_VGATHERPF1QPS_LAST =4760, +  XED_IFORMFL_VFMSUB231SD_LAST =4825,
-  XED_IFORMFL_VGATHERQPD_FIRST =4761, +  XED_IFORMFL_VFMSUB231SH_FIRST =4826,
-  XED_IFORMFL_VGATHERQPD_LAST =4765, +  XED_IFORMFL_VFMSUB231SH_LAST =4828,
-  XED_IFORMFL_VGATHERQPS_FIRST =4766, +  XED_IFORMFL_VFMSUB231SS_FIRST =4829,
-  XED_IFORMFL_VGATHERQPS_LAST =4770, +  XED_IFORMFL_VFMSUB231SS_LAST =4833,
-  XED_IFORMFL_VGETEXPPD_FIRST =4771, +  XED_IFORMFL_VFMSUBADD132PD_FIRST =4834,
-  XED_IFORMFL_VGETEXPPD_LAST =4776, +  XED_IFORMFL_VFMSUBADD132PD_LAST =4844,
-  XED_IFORMFL_VGETEXPPH_FIRST =4777, +  XED_IFORMFL_VFMSUBADD132PH_FIRST =4845,
-  XED_IFORMFL_VGETEXPPH_LAST =4782, +  XED_IFORMFL_VFMSUBADD132PH_LAST =4851,
-  XED_IFORMFL_VGETEXPPS_FIRST =4783, +  XED_IFORMFL_VFMSUBADD132PS_FIRST =4852,
-  XED_IFORMFL_VGETEXPPS_LAST =4788, +  XED_IFORMFL_VFMSUBADD132PS_LAST =4862,
-  XED_IFORMFL_VGETEXPSD_FIRST =4789, +  XED_IFORMFL_VFMSUBADD213PD_FIRST =4863,
-  XED_IFORMFL_VGETEXPSD_LAST =4790, +  XED_IFORMFL_VFMSUBADD213PD_LAST =4873,
-  XED_IFORMFL_VGETEXPSH_FIRST =4791, +  XED_IFORMFL_VFMSUBADD213PH_FIRST =4874,
-  XED_IFORMFL_VGETEXPSH_LAST =4792, +  XED_IFORMFL_VFMSUBADD213PH_LAST =4880,
-  XED_IFORMFL_VGETEXPSS_FIRST =4793, +  XED_IFORMFL_VFMSUBADD213PS_FIRST =4881,
-  XED_IFORMFL_VGETEXPSS_LAST =4794, +  XED_IFORMFL_VFMSUBADD213PS_LAST =4891,
-  XED_IFORMFL_VGETMANTPD_FIRST =4795, +  XED_IFORMFL_VFMSUBADD231PD_FIRST =4892,
-  XED_IFORMFL_VGETMANTPD_LAST =4800, +  XED_IFORMFL_VFMSUBADD231PD_LAST =4902,
-  XED_IFORMFL_VGETMANTPH_FIRST =4801, +  XED_IFORMFL_VFMSUBADD231PH_FIRST =4903,
-  XED_IFORMFL_VGETMANTPH_LAST =4806, +  XED_IFORMFL_VFMSUBADD231PH_LAST =4909,
-  XED_IFORMFL_VGETMANTPS_FIRST =4807, +  XED_IFORMFL_VFMSUBADD231PS_FIRST =4910,
-  XED_IFORMFL_VGETMANTPS_LAST =4812, +  XED_IFORMFL_VFMSUBADD231PS_LAST =4920,
-  XED_IFORMFL_VGETMANTSD_FIRST =4813, +  XED_IFORMFL_VFMSUBADDPD_FIRST =4921,
-  XED_IFORMFL_VGETMANTSD_LAST =4814, +  XED_IFORMFL_VFMSUBADDPD_LAST =4926,
-  XED_IFORMFL_VGETMANTSH_FIRST =4815, +  XED_IFORMFL_VFMSUBADDPS_FIRST =4927,
-  XED_IFORMFL_VGETMANTSH_LAST =4816, +  XED_IFORMFL_VFMSUBADDPS_LAST =4932,
-  XED_IFORMFL_VGETMANTSS_FIRST =4817, +  XED_IFORMFL_VFMSUBPD_FIRST =4933,
-  XED_IFORMFL_VGETMANTSS_LAST =4818, +  XED_IFORMFL_VFMSUBPD_LAST =4938,
-  XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST =4819, +  XED_IFORMFL_VFMSUBPS_FIRST =4939,
-  XED_IFORMFL_VGF2P8AFFINEINVQB_LAST =4828, +  XED_IFORMFL_VFMSUBPS_LAST =4944,
-  XED_IFORMFL_VGF2P8AFFINEQB_FIRST =4829, +  XED_IFORMFL_VFMSUBSD_FIRST =4945,
-  XED_IFORMFL_VGF2P8AFFINEQB_LAST =4838, +  XED_IFORMFL_VFMSUBSD_LAST =4947,
-  XED_IFORMFL_VGF2P8MULB_FIRST =4839, +  XED_IFORMFL_VFMSUBSS_FIRST =4948,
-  XED_IFORMFL_VGF2P8MULB_LAST =4848, +  XED_IFORMFL_VFMSUBSS_LAST =4950,
-  XED_IFORMFL_VHADDPD_FIRST =4849, +  XED_IFORMFL_VFMULCPH_FIRST =4951,
-  XED_IFORMFL_VHADDPD_LAST =4852, +  XED_IFORMFL_VFMULCPH_LAST =4957,
-  XED_IFORMFL_VHADDPS_FIRST =4853, +  XED_IFORMFL_VFMULCSH_FIRST =4958,
-  XED_IFORMFL_VHADDPS_LAST =4856, +  XED_IFORMFL_VFMULCSH_LAST =4960,
-  XED_IFORMFL_VHSUBPD_FIRST =4857, +  XED_IFORMFL_VFNMADD132NEPBF16_FIRST =4961,
-  XED_IFORMFL_VHSUBPD_LAST =4860, +  XED_IFORMFL_VFNMADD132NEPBF16_LAST =4966,
-  XED_IFORMFL_VHSUBPS_FIRST =4861, +  XED_IFORMFL_VFNMADD132PD_FIRST =4967,
-  XED_IFORMFL_VHSUBPS_LAST =4864, +  XED_IFORMFL_VFNMADD132PD_LAST =4977,
-  XED_IFORMFL_VINSERTF128_FIRST =4865, +  XED_IFORMFL_VFNMADD132PH_FIRST =4978,
-  XED_IFORMFL_VINSERTF128_LAST =4866, +  XED_IFORMFL_VFNMADD132PH_LAST =4984,
-  XED_IFORMFL_VINSERTF32X4_FIRST =4867, +  XED_IFORMFL_VFNMADD132PS_FIRST =4985,
-  XED_IFORMFL_VINSERTF32X4_LAST =4870, +  XED_IFORMFL_VFNMADD132PS_LAST =4995,
-  XED_IFORMFL_VINSERTF32X8_FIRST =4871, +  XED_IFORMFL_VFNMADD132SD_FIRST =4996,
-  XED_IFORMFL_VINSERTF32X8_LAST =4872, +  XED_IFORMFL_VFNMADD132SD_LAST =5000,
-  XED_IFORMFL_VINSERTF64X2_FIRST =4873, +  XED_IFORMFL_VFNMADD132SH_FIRST =5001,
-  XED_IFORMFL_VINSERTF64X2_LAST =4876, +  XED_IFORMFL_VFNMADD132SH_LAST =5003,
-  XED_IFORMFL_VINSERTF64X4_FIRST =4877, +  XED_IFORMFL_VFNMADD132SS_FIRST =5004,
-  XED_IFORMFL_VINSERTF64X4_LAST =4878, +  XED_IFORMFL_VFNMADD132SS_LAST =5008,
-  XED_IFORMFL_VINSERTI128_FIRST =4879, +  XED_IFORMFL_VFNMADD213NEPBF16_FIRST =5009,
-  XED_IFORMFL_VINSERTI128_LAST =4880, +  XED_IFORMFL_VFNMADD213NEPBF16_LAST =5014,
-  XED_IFORMFL_VINSERTI32X4_FIRST =4881, +  XED_IFORMFL_VFNMADD213PD_FIRST =5015,
-  XED_IFORMFL_VINSERTI32X4_LAST =4884, +  XED_IFORMFL_VFNMADD213PD_LAST =5025,
-  XED_IFORMFL_VINSERTI32X8_FIRST =4885, +  XED_IFORMFL_VFNMADD213PH_FIRST =5026,
-  XED_IFORMFL_VINSERTI32X8_LAST =4886, +  XED_IFORMFL_VFNMADD213PH_LAST =5032,
-  XED_IFORMFL_VINSERTI64X2_FIRST =4887, +  XED_IFORMFL_VFNMADD213PS_FIRST =5033,
-  XED_IFORMFL_VINSERTI64X2_LAST =4890, +  XED_IFORMFL_VFNMADD213PS_LAST =5043,
-  XED_IFORMFL_VINSERTI64X4_FIRST =4891, +  XED_IFORMFL_VFNMADD213SD_FIRST =5044,
-  XED_IFORMFL_VINSERTI64X4_LAST =4892, +  XED_IFORMFL_VFNMADD213SD_LAST =5048,
-  XED_IFORMFL_VINSERTPS_FIRST =4893, +  XED_IFORMFL_VFNMADD213SH_FIRST =5049,
-  XED_IFORMFL_VINSERTPS_LAST =4896, +  XED_IFORMFL_VFNMADD213SH_LAST =5051,
-  XED_IFORMFL_VLDDQU_FIRST =4897, +  XED_IFORMFL_VFNMADD213SS_FIRST =5052,
-  XED_IFORMFL_VLDDQU_LAST =4898, +  XED_IFORMFL_VFNMADD213SS_LAST =5056,
-  XED_IFORMFL_VLDMXCSR_FIRST =4899, +  XED_IFORMFL_VFNMADD231NEPBF16_FIRST =5057,
-  XED_IFORMFL_VLDMXCSR_LAST =4899, +  XED_IFORMFL_VFNMADD231NEPBF16_LAST =5062,
-  XED_IFORMFL_VMASKMOVDQU_FIRST =4900, +  XED_IFORMFL_VFNMADD231PD_FIRST =5063,
-  XED_IFORMFL_VMASKMOVDQU_LAST =4900, +  XED_IFORMFL_VFNMADD231PD_LAST =5073,
-  XED_IFORMFL_VMASKMOVPD_FIRST =4901, +  XED_IFORMFL_VFNMADD231PH_FIRST =5074,
-  XED_IFORMFL_VMASKMOVPD_LAST =4904, +  XED_IFORMFL_VFNMADD231PH_LAST =5080,
-  XED_IFORMFL_VMASKMOVPS_FIRST =4905, +  XED_IFORMFL_VFNMADD231PS_FIRST =5081,
-  XED_IFORMFL_VMASKMOVPS_LAST =4908, +  XED_IFORMFL_VFNMADD231PS_LAST =5091,
-  XED_IFORMFL_VMAXPD_FIRST =4909, +  XED_IFORMFL_VFNMADD231SD_FIRST =5092,
-  XED_IFORMFL_VMAXPD_LAST =4918, +  XED_IFORMFL_VFNMADD231SD_LAST =5096,
-  XED_IFORMFL_VMAXPH_FIRST =4919, +  XED_IFORMFL_VFNMADD231SH_FIRST =5097,
-  XED_IFORMFL_VMAXPH_LAST =4924, +  XED_IFORMFL_VFNMADD231SH_LAST =5099,
-  XED_IFORMFL_VMAXPS_FIRST =4925, +  XED_IFORMFL_VFNMADD231SS_FIRST =5100,
-  XED_IFORMFL_VMAXPS_LAST =4934, +  XED_IFORMFL_VFNMADD231SS_LAST =5104,
-  XED_IFORMFL_VMAXSD_FIRST =4935, +  XED_IFORMFL_VFNMADDPD_FIRST =5105,
-  XED_IFORMFL_VMAXSD_LAST =4938, +  XED_IFORMFL_VFNMADDPD_LAST =5110,
-  XED_IFORMFL_VMAXSH_FIRST =4939, +  XED_IFORMFL_VFNMADDPS_FIRST =5111,
-  XED_IFORMFL_VMAXSH_LAST =4940, +  XED_IFORMFL_VFNMADDPS_LAST =5116,
-  XED_IFORMFL_VMAXSS_FIRST =4941, +  XED_IFORMFL_VFNMADDSD_FIRST =5117,
-  XED_IFORMFL_VMAXSS_LAST =4944, +  XED_IFORMFL_VFNMADDSD_LAST =5119,
-  XED_IFORMFL_VMCALL_FIRST =4945, +  XED_IFORMFL_VFNMADDSS_FIRST =5120,
-  XED_IFORMFL_VMCALL_LAST =4945, +  XED_IFORMFL_VFNMADDSS_LAST =5122,
-  XED_IFORMFL_VMCLEAR_FIRST =4946, +  XED_IFORMFL_VFNMSUB132NEPBF16_FIRST =5123,
-  XED_IFORMFL_VMCLEAR_LAST =4946, +  XED_IFORMFL_VFNMSUB132NEPBF16_LAST =5128,
-  XED_IFORMFL_VMFUNC_FIRST =4947, +  XED_IFORMFL_VFNMSUB132PD_FIRST =5129,
-  XED_IFORMFL_VMFUNC_LAST =4947, +  XED_IFORMFL_VFNMSUB132PD_LAST =5139,
-  XED_IFORMFL_VMINPD_FIRST =4948, +  XED_IFORMFL_VFNMSUB132PH_FIRST =5140,
-  XED_IFORMFL_VMINPD_LAST =4957, +  XED_IFORMFL_VFNMSUB132PH_LAST =5146,
-  XED_IFORMFL_VMINPH_FIRST =4958, +  XED_IFORMFL_VFNMSUB132PS_FIRST =5147,
-  XED_IFORMFL_VMINPH_LAST =4963, +  XED_IFORMFL_VFNMSUB132PS_LAST =5157,
-  XED_IFORMFL_VMINPS_FIRST =4964, +  XED_IFORMFL_VFNMSUB132SD_FIRST =5158,
-  XED_IFORMFL_VMINPS_LAST =4973, +  XED_IFORMFL_VFNMSUB132SD_LAST =5162,
-  XED_IFORMFL_VMINSD_FIRST =4974, +  XED_IFORMFL_VFNMSUB132SH_FIRST =5163,
-  XED_IFORMFL_VMINSD_LAST =4977, +  XED_IFORMFL_VFNMSUB132SH_LAST =5165,
-  XED_IFORMFL_VMINSH_FIRST =4978, +  XED_IFORMFL_VFNMSUB132SS_FIRST =5166,
-  XED_IFORMFL_VMINSH_LAST =4979, +  XED_IFORMFL_VFNMSUB132SS_LAST =5170,
-  XED_IFORMFL_VMINSS_FIRST =4980, +  XED_IFORMFL_VFNMSUB213NEPBF16_FIRST =5171,
-  XED_IFORMFL_VMINSS_LAST =4983, +  XED_IFORMFL_VFNMSUB213NEPBF16_LAST =5176,
-  XED_IFORMFL_VMLAUNCH_FIRST =4984, +  XED_IFORMFL_VFNMSUB213PD_FIRST =5177,
-  XED_IFORMFL_VMLAUNCH_LAST =4984, +  XED_IFORMFL_VFNMSUB213PD_LAST =5187,
-  XED_IFORMFL_VMLOAD_FIRST =4985, +  XED_IFORMFL_VFNMSUB213PH_FIRST =5188,
-  XED_IFORMFL_VMLOAD_LAST =4985, +  XED_IFORMFL_VFNMSUB213PH_LAST =5194,
-  XED_IFORMFL_VMMCALL_FIRST =4986, +  XED_IFORMFL_VFNMSUB213PS_FIRST =5195,
-  XED_IFORMFL_VMMCALL_LAST =4986, +  XED_IFORMFL_VFNMSUB213PS_LAST =5205,
-  XED_IFORMFL_VMOVAPD_FIRST =4987, +  XED_IFORMFL_VFNMSUB213SD_FIRST =5206,
-  XED_IFORMFL_VMOVAPD_LAST =5003, +  XED_IFORMFL_VFNMSUB213SD_LAST =5210,
-  XED_IFORMFL_VMOVAPS_FIRST =5004, +  XED_IFORMFL_VFNMSUB213SH_FIRST =5211,
-  XED_IFORMFL_VMOVAPS_LAST =5020, +  XED_IFORMFL_VFNMSUB213SH_LAST =5213,
-  XED_IFORMFL_VMOVD_FIRST =5021, +  XED_IFORMFL_VFNMSUB213SS_FIRST =5214,
-  XED_IFORMFL_VMOVD_LAST =5028, +  XED_IFORMFL_VFNMSUB213SS_LAST =5218,
-  XED_IFORMFL_VMOVDDUP_FIRST =5029, +  XED_IFORMFL_VFNMSUB231NEPBF16_FIRST =5219,
-  XED_IFORMFL_VMOVDDUP_LAST =5038, +  XED_IFORMFL_VFNMSUB231NEPBF16_LAST =5224,
-  XED_IFORMFL_VMOVDQA_FIRST =5039, +  XED_IFORMFL_VFNMSUB231PD_FIRST =5225,
-  XED_IFORMFL_VMOVDQA_LAST =5046, +  XED_IFORMFL_VFNMSUB231PD_LAST =5235,
-  XED_IFORMFL_VMOVDQA32_FIRST =5047, +  XED_IFORMFL_VFNMSUB231PH_FIRST =5236,
-  XED_IFORMFL_VMOVDQA32_LAST =5055, +  XED_IFORMFL_VFNMSUB231PH_LAST =5242,
-  XED_IFORMFL_VMOVDQA64_FIRST =5056, +  XED_IFORMFL_VFNMSUB231PS_FIRST =5243,
-  XED_IFORMFL_VMOVDQA64_LAST =5064, +  XED_IFORMFL_VFNMSUB231PS_LAST =5253,
-  XED_IFORMFL_VMOVDQU_FIRST =5065, +  XED_IFORMFL_VFNMSUB231SD_FIRST =5254,
-  XED_IFORMFL_VMOVDQU_LAST =5072, +  XED_IFORMFL_VFNMSUB231SD_LAST =5258,
-  XED_IFORMFL_VMOVDQU16_FIRST =5073, +  XED_IFORMFL_VFNMSUB231SH_FIRST =5259,
-  XED_IFORMFL_VMOVDQU16_LAST =5081, +  XED_IFORMFL_VFNMSUB231SH_LAST =5261,
-  XED_IFORMFL_VMOVDQU32_FIRST =5082, +  XED_IFORMFL_VFNMSUB231SS_FIRST =5262,
-  XED_IFORMFL_VMOVDQU32_LAST =5090, +  XED_IFORMFL_VFNMSUB231SS_LAST =5266,
-  XED_IFORMFL_VMOVDQU64_FIRST =5091, +  XED_IFORMFL_VFNMSUBPD_FIRST =5267,
-  XED_IFORMFL_VMOVDQU64_LAST =5099, +  XED_IFORMFL_VFNMSUBPD_LAST =5272,
-  XED_IFORMFL_VMOVDQU8_FIRST =5100, +  XED_IFORMFL_VFNMSUBPS_FIRST =5273,
-  XED_IFORMFL_VMOVDQU8_LAST =5108, +  XED_IFORMFL_VFNMSUBPS_LAST =5278,
-  XED_IFORMFL_VMOVHLPS_FIRST =5109, +  XED_IFORMFL_VFNMSUBSD_FIRST =5279,
-  XED_IFORMFL_VMOVHLPS_LAST =5110, +  XED_IFORMFL_VFNMSUBSD_LAST =5281,
-  XED_IFORMFL_VMOVHPD_FIRST =5111, +  XED_IFORMFL_VFNMSUBSS_FIRST =5282,
-  XED_IFORMFL_VMOVHPD_LAST =5114, +  XED_IFORMFL_VFNMSUBSS_LAST =5284,
-  XED_IFORMFL_VMOVHPS_FIRST =5115, +  XED_IFORMFL_VFPCLASSPBF16_FIRST =5285,
-  XED_IFORMFL_VMOVHPS_LAST =5118, +  XED_IFORMFL_VFPCLASSPBF16_LAST =5290,
-  XED_IFORMFL_VMOVLHPS_FIRST =5119, +  XED_IFORMFL_VFPCLASSPD_FIRST =5291,
-  XED_IFORMFL_VMOVLHPS_LAST =5120, +  XED_IFORMFL_VFPCLASSPD_LAST =5296,
-  XED_IFORMFL_VMOVLPD_FIRST =5121, +  XED_IFORMFL_VFPCLASSPH_FIRST =5297,
-  XED_IFORMFL_VMOVLPD_LAST =5124, +  XED_IFORMFL_VFPCLASSPH_LAST =5302,
-  XED_IFORMFL_VMOVLPS_FIRST =5125, +  XED_IFORMFL_VFPCLASSPS_FIRST =5303,
-  XED_IFORMFL_VMOVLPS_LAST =5128, +  XED_IFORMFL_VFPCLASSPS_LAST =5308,
-  XED_IFORMFL_VMOVMSKPD_FIRST =5129, +  XED_IFORMFL_VFPCLASSSD_FIRST =5309,
-  XED_IFORMFL_VMOVMSKPD_LAST =5130, +  XED_IFORMFL_VFPCLASSSD_LAST =5310,
-  XED_IFORMFL_VMOVMSKPS_FIRST =5131, +  XED_IFORMFL_VFPCLASSSH_FIRST =5311,
-  XED_IFORMFL_VMOVMSKPS_LAST =5132, +  XED_IFORMFL_VFPCLASSSH_LAST =5312,
-  XED_IFORMFL_VMOVNTDQ_FIRST =5133, +  XED_IFORMFL_VFPCLASSSS_FIRST =5313,
-  XED_IFORMFL_VMOVNTDQ_LAST =5137, +  XED_IFORMFL_VFPCLASSSS_LAST =5314,
-  XED_IFORMFL_VMOVNTDQA_FIRST =5138, +  XED_IFORMFL_VFRCZPD_FIRST =5315,
-  XED_IFORMFL_VMOVNTDQA_LAST =5142, +  XED_IFORMFL_VFRCZPD_LAST =5318,
-  XED_IFORMFL_VMOVNTPD_FIRST =5143, +  XED_IFORMFL_VFRCZPS_FIRST =5319,
-  XED_IFORMFL_VMOVNTPD_LAST =5147, +  XED_IFORMFL_VFRCZPS_LAST =5322,
-  XED_IFORMFL_VMOVNTPS_FIRST =5148, +  XED_IFORMFL_VFRCZSD_FIRST =5323,
-  XED_IFORMFL_VMOVNTPS_LAST =5152, +  XED_IFORMFL_VFRCZSD_LAST =5324,
-  XED_IFORMFL_VMOVQ_FIRST =5153, +  XED_IFORMFL_VFRCZSS_FIRST =5325,
-  XED_IFORMFL_VMOVQ_LAST =5165, +  XED_IFORMFL_VFRCZSS_LAST =5326,
-  XED_IFORMFL_VMOVSD_FIRST =5166, +  XED_IFORMFL_VGATHERDPD_FIRST =5327,
-  XED_IFORMFL_VMOVSD_LAST =5172, +  XED_IFORMFL_VGATHERDPD_LAST =5331,
-  XED_IFORMFL_VMOVSH_FIRST =5173, +  XED_IFORMFL_VGATHERDPS_FIRST =5332,
-  XED_IFORMFL_VMOVSH_LAST =5175, +  XED_IFORMFL_VGATHERDPS_LAST =5336,
-  XED_IFORMFL_VMOVSHDUP_FIRST =5176, +  XED_IFORMFL_VGATHERPF0DPD_FIRST =5337,
-  XED_IFORMFL_VMOVSHDUP_LAST =5185, +  XED_IFORMFL_VGATHERPF0DPD_LAST =5337,
-  XED_IFORMFL_VMOVSLDUP_FIRST =5186, +  XED_IFORMFL_VGATHERPF0DPS_FIRST =5338,
-  XED_IFORMFL_VMOVSLDUP_LAST =5195, +  XED_IFORMFL_VGATHERPF0DPS_LAST =5338,
-  XED_IFORMFL_VMOVSS_FIRST =5196, +  XED_IFORMFL_VGATHERPF0QPD_FIRST =5339,
-  XED_IFORMFL_VMOVSS_LAST =5202, +  XED_IFORMFL_VGATHERPF0QPD_LAST =5339,
-  XED_IFORMFL_VMOVUPD_FIRST =5203, +  XED_IFORMFL_VGATHERPF0QPS_FIRST =5340,
-  XED_IFORMFL_VMOVUPD_LAST =5219, +  XED_IFORMFL_VGATHERPF0QPS_LAST =5340,
-  XED_IFORMFL_VMOVUPS_FIRST =5220, +  XED_IFORMFL_VGATHERPF1DPD_FIRST =5341,
-  XED_IFORMFL_VMOVUPS_LAST =5236, +  XED_IFORMFL_VGATHERPF1DPD_LAST =5341,
-  XED_IFORMFL_VMOVW_FIRST =5237, +  XED_IFORMFL_VGATHERPF1DPS_FIRST =5342,
-  XED_IFORMFL_VMOVW_LAST =5240, +  XED_IFORMFL_VGATHERPF1DPS_LAST =5342,
-  XED_IFORMFL_VMPSADBW_FIRST =5241, +  XED_IFORMFL_VGATHERPF1QPD_FIRST =5343,
-  XED_IFORMFL_VMPSADBW_LAST =5244, +  XED_IFORMFL_VGATHERPF1QPD_LAST =5343,
-  XED_IFORMFL_VMPTRLD_FIRST =5245, +  XED_IFORMFL_VGATHERPF1QPS_FIRST =5344,
-  XED_IFORMFL_VMPTRLD_LAST =5245, +  XED_IFORMFL_VGATHERPF1QPS_LAST =5344,
-  XED_IFORMFL_VMPTRST_FIRST =5246, +  XED_IFORMFL_VGATHERQPD_FIRST =5345,
-  XED_IFORMFL_VMPTRST_LAST =5246, +  XED_IFORMFL_VGATHERQPD_LAST =5349,
-  XED_IFORMFL_VMREAD_FIRST =5247, +  XED_IFORMFL_VGATHERQPS_FIRST =5350,
-  XED_IFORMFL_VMREAD_LAST =5250, +  XED_IFORMFL_VGATHERQPS_LAST =5354,
-  XED_IFORMFL_VMRESUME_FIRST =5251, +  XED_IFORMFL_VGETEXPPBF16_FIRST =5355,
-  XED_IFORMFL_VMRESUME_LAST =5251, +  XED_IFORMFL_VGETEXPPBF16_LAST =5360,
-  XED_IFORMFL_VMRUN_FIRST =5252, +  XED_IFORMFL_VGETEXPPD_FIRST =5361,
-  XED_IFORMFL_VMRUN_LAST =5252, +  XED_IFORMFL_VGETEXPPD_LAST =5367,
-  XED_IFORMFL_VMSAVE_FIRST =5253, +  XED_IFORMFL_VGETEXPPH_FIRST =5368,
-  XED_IFORMFL_VMSAVE_LAST =5253, +  XED_IFORMFL_VGETEXPPH_LAST =5374,
-  XED_IFORMFL_VMULPD_FIRST =5254, +  XED_IFORMFL_VGETEXPPS_FIRST =5375,
-  XED_IFORMFL_VMULPD_LAST =5263, +  XED_IFORMFL_VGETEXPPS_LAST =5381,
-  XED_IFORMFL_VMULPH_FIRST =5264, +  XED_IFORMFL_VGETEXPSD_FIRST =5382,
-  XED_IFORMFL_VMULPH_LAST =5269, +  XED_IFORMFL_VGETEXPSD_LAST =5384,
-  XED_IFORMFL_VMULPS_FIRST =5270, +  XED_IFORMFL_VGETEXPSH_FIRST =5385,
-  XED_IFORMFL_VMULPS_LAST =5279, +  XED_IFORMFL_VGETEXPSH_LAST =5387,
-  XED_IFORMFL_VMULSD_FIRST =5280, +  XED_IFORMFL_VGETEXPSS_FIRST =5388,
-  XED_IFORMFL_VMULSD_LAST =5283, +  XED_IFORMFL_VGETEXPSS_LAST =5390,
-  XED_IFORMFL_VMULSH_FIRST =5284, +  XED_IFORMFL_VGETMANTPBF16_FIRST =5391,
-  XED_IFORMFL_VMULSH_LAST =5285, +  XED_IFORMFL_VGETMANTPBF16_LAST =5396,
-  XED_IFORMFL_VMULSS_FIRST =5286, +  XED_IFORMFL_VGETMANTPD_FIRST =5397,
-  XED_IFORMFL_VMULSS_LAST =5289, +  XED_IFORMFL_VGETMANTPD_LAST =5403,
-  XED_IFORMFL_VMWRITE_FIRST =5290, +  XED_IFORMFL_VGETMANTPH_FIRST =5404,
-  XED_IFORMFL_VMWRITE_LAST =5293, +  XED_IFORMFL_VGETMANTPH_LAST =5410,
-  XED_IFORMFL_VMXOFF_FIRST =5294, +  XED_IFORMFL_VGETMANTPS_FIRST =5411,
-  XED_IFORMFL_VMXOFF_LAST =5294, +  XED_IFORMFL_VGETMANTPS_LAST =5417,
-  XED_IFORMFL_VMXON_FIRST =5295, +  XED_IFORMFL_VGETMANTSD_FIRST =5418,
-  XED_IFORMFL_VMXON_LAST =5295, +  XED_IFORMFL_VGETMANTSD_LAST =5420,
-  XED_IFORMFL_VORPD_FIRST =5296, +  XED_IFORMFL_VGETMANTSH_FIRST =5421,
-  XED_IFORMFL_VORPD_LAST =5305, +  XED_IFORMFL_VGETMANTSH_LAST =5423,
-  XED_IFORMFL_VORPS_FIRST =5306, +  XED_IFORMFL_VGETMANTSS_FIRST =5424,
-  XED_IFORMFL_VORPS_LAST =5315, +  XED_IFORMFL_VGETMANTSS_LAST =5426,
-  XED_IFORMFL_VP2INTERSECTD_FIRST =5316, +  XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST =5427,
-  XED_IFORMFL_VP2INTERSECTD_LAST =5321, +  XED_IFORMFL_VGF2P8AFFINEINVQB_LAST =5436,
-  XED_IFORMFL_VP2INTERSECTQ_FIRST =5322, +  XED_IFORMFL_VGF2P8AFFINEQB_FIRST =5437,
-  XED_IFORMFL_VP2INTERSECTQ_LAST =5327, +  XED_IFORMFL_VGF2P8AFFINEQB_LAST =5446,
-  XED_IFORMFL_VP4DPWSSD_FIRST =5328, +  XED_IFORMFL_VGF2P8MULB_FIRST =5447,
-  XED_IFORMFL_VP4DPWSSD_LAST =5328, +  XED_IFORMFL_VGF2P8MULB_LAST =5456,
-  XED_IFORMFL_VP4DPWSSDS_FIRST =5329, +  XED_IFORMFL_VHADDPD_FIRST =5457,
-  XED_IFORMFL_VP4DPWSSDS_LAST =5329, +  XED_IFORMFL_VHADDPD_LAST =5460,
-  XED_IFORMFL_VPABSB_FIRST =5330, +  XED_IFORMFL_VHADDPS_FIRST =5461,
-  XED_IFORMFL_VPABSB_LAST =5339, +  XED_IFORMFL_VHADDPS_LAST =5464,
-  XED_IFORMFL_VPABSD_FIRST =5340, +  XED_IFORMFL_VHSUBPD_FIRST =5465,
-  XED_IFORMFL_VPABSD_LAST =5349, +  XED_IFORMFL_VHSUBPD_LAST =5468,
-  XED_IFORMFL_VPABSQ_FIRST =5350, +  XED_IFORMFL_VHSUBPS_FIRST =5469,
-  XED_IFORMFL_VPABSQ_LAST =5355, +  XED_IFORMFL_VHSUBPS_LAST =5472,
-  XED_IFORMFL_VPABSW_FIRST =5356, +  XED_IFORMFL_VINSERTF128_FIRST =5473,
-  XED_IFORMFL_VPABSW_LAST =5365, +  XED_IFORMFL_VINSERTF128_LAST =5474,
-  XED_IFORMFL_VPACKSSDW_FIRST =5366, +  XED_IFORMFL_VINSERTF32X4_FIRST =5475,
-  XED_IFORMFL_VPACKSSDW_LAST =5375, +  XED_IFORMFL_VINSERTF32X4_LAST =5478,
-  XED_IFORMFL_VPACKSSWB_FIRST =5376, +  XED_IFORMFL_VINSERTF32X8_FIRST =5479,
-  XED_IFORMFL_VPACKSSWB_LAST =5385, +  XED_IFORMFL_VINSERTF32X8_LAST =5480,
-  XED_IFORMFL_VPACKUSDW_FIRST =5386, +  XED_IFORMFL_VINSERTF64X2_FIRST =5481,
-  XED_IFORMFL_VPACKUSDW_LAST =5395, +  XED_IFORMFL_VINSERTF64X2_LAST =5484,
-  XED_IFORMFL_VPACKUSWB_FIRST =5396, +  XED_IFORMFL_VINSERTF64X4_FIRST =5485,
-  XED_IFORMFL_VPACKUSWB_LAST =5405, +  XED_IFORMFL_VINSERTF64X4_LAST =5486,
-  XED_IFORMFL_VPADDB_FIRST =5406, +  XED_IFORMFL_VINSERTI128_FIRST =5487,
-  XED_IFORMFL_VPADDB_LAST =5415, +  XED_IFORMFL_VINSERTI128_LAST =5488,
-  XED_IFORMFL_VPADDD_FIRST =5416, +  XED_IFORMFL_VINSERTI32X4_FIRST =5489,
-  XED_IFORMFL_VPADDD_LAST =5425, +  XED_IFORMFL_VINSERTI32X4_LAST =5492,
-  XED_IFORMFL_VPADDQ_FIRST =5426, +  XED_IFORMFL_VINSERTI32X8_FIRST =5493,
-  XED_IFORMFL_VPADDQ_LAST =5435, +  XED_IFORMFL_VINSERTI32X8_LAST =5494,
-  XED_IFORMFL_VPADDSB_FIRST =5436, +  XED_IFORMFL_VINSERTI64X2_FIRST =5495,
-  XED_IFORMFL_VPADDSB_LAST =5445, +  XED_IFORMFL_VINSERTI64X2_LAST =5498,
-  XED_IFORMFL_VPADDSW_FIRST =5446, +  XED_IFORMFL_VINSERTI64X4_FIRST =5499,
-  XED_IFORMFL_VPADDSW_LAST =5455, +  XED_IFORMFL_VINSERTI64X4_LAST =5500,
-  XED_IFORMFL_VPADDUSB_FIRST =5456, +  XED_IFORMFL_VINSERTPS_FIRST =5501,
-  XED_IFORMFL_VPADDUSB_LAST =5465, +  XED_IFORMFL_VINSERTPS_LAST =5504,
-  XED_IFORMFL_VPADDUSW_FIRST =5466, +  XED_IFORMFL_VLDDQU_FIRST =5505,
-  XED_IFORMFL_VPADDUSW_LAST =5475, +  XED_IFORMFL_VLDDQU_LAST =5506,
-  XED_IFORMFL_VPADDW_FIRST =5476, +  XED_IFORMFL_VLDMXCSR_FIRST =5507,
-  XED_IFORMFL_VPADDW_LAST =5485, +  XED_IFORMFL_VLDMXCSR_LAST =5507,
-  XED_IFORMFL_VPALIGNR_FIRST =5486, +  XED_IFORMFL_VMASKMOVDQU_FIRST =5508,
-  XED_IFORMFL_VPALIGNR_LAST =5495, +  XED_IFORMFL_VMASKMOVDQU_LAST =5508,
-  XED_IFORMFL_VPAND_FIRST =5496, +  XED_IFORMFL_VMASKMOVPD_FIRST =5509,
-  XED_IFORMFL_VPAND_LAST =5499, +  XED_IFORMFL_VMASKMOVPD_LAST =5512,
-  XED_IFORMFL_VPANDD_FIRST =5500, +  XED_IFORMFL_VMASKMOVPS_FIRST =5513,
-  XED_IFORMFL_VPANDD_LAST =5505, +  XED_IFORMFL_VMASKMOVPS_LAST =5516,
-  XED_IFORMFL_VPANDN_FIRST =5506, +  XED_IFORMFL_VMAXPBF16_FIRST =5517,
-  XED_IFORMFL_VPANDN_LAST =5509, +  XED_IFORMFL_VMAXPBF16_LAST =5522,
-  XED_IFORMFL_VPANDND_FIRST =5510, +  XED_IFORMFL_VMAXPD_FIRST =5523,
-  XED_IFORMFL_VPANDND_LAST =5515, +  XED_IFORMFL_VMAXPD_LAST =5533,
-  XED_IFORMFL_VPANDNQ_FIRST =5516, +  XED_IFORMFL_VMAXPH_FIRST =5534,
-  XED_IFORMFL_VPANDNQ_LAST =5521, +  XED_IFORMFL_VMAXPH_LAST =5540,
-  XED_IFORMFL_VPANDQ_FIRST =5522, +  XED_IFORMFL_VMAXPS_FIRST =5541,
-  XED_IFORMFL_VPANDQ_LAST =5527, +  XED_IFORMFL_VMAXPS_LAST =5551,
-  XED_IFORMFL_VPAVGB_FIRST =5528, +  XED_IFORMFL_VMAXSD_FIRST =5552,
-  XED_IFORMFL_VPAVGB_LAST =5537, +  XED_IFORMFL_VMAXSD_LAST =5556,
-  XED_IFORMFL_VPAVGW_FIRST =5538, +  XED_IFORMFL_VMAXSH_FIRST =5557,
-  XED_IFORMFL_VPAVGW_LAST =5547, +  XED_IFORMFL_VMAXSH_LAST =5559,
-  XED_IFORMFL_VPBLENDD_FIRST =5548, +  XED_IFORMFL_VMAXSS_FIRST =5560,
-  XED_IFORMFL_VPBLENDD_LAST =5551, +  XED_IFORMFL_VMAXSS_LAST =5564,
-  XED_IFORMFL_VPBLENDMB_FIRST =5552, +  XED_IFORMFL_VMCALL_FIRST =5565,
-  XED_IFORMFL_VPBLENDMB_LAST =5557, +  XED_IFORMFL_VMCALL_LAST =5565,
-  XED_IFORMFL_VPBLENDMD_FIRST =5558, +  XED_IFORMFL_VMCLEAR_FIRST =5566,
-  XED_IFORMFL_VPBLENDMD_LAST =5563, +  XED_IFORMFL_VMCLEAR_LAST =5566,
-  XED_IFORMFL_VPBLENDMQ_FIRST =5564, +  XED_IFORMFL_VMFUNC_FIRST =5567,
-  XED_IFORMFL_VPBLENDMQ_LAST =5569, +  XED_IFORMFL_VMFUNC_LAST =5567,
-  XED_IFORMFL_VPBLENDMW_FIRST =5570, +  XED_IFORMFL_VMINMAXNEPBF16_FIRST =5568,
-  XED_IFORMFL_VPBLENDMW_LAST =5575, +  XED_IFORMFL_VMINMAXNEPBF16_LAST =5573,
-  XED_IFORMFL_VPBLENDVB_FIRST =5576, +  XED_IFORMFL_VMINMAXPD_FIRST =5574,
-  XED_IFORMFL_VPBLENDVB_LAST =5579, +  XED_IFORMFL_VMINMAXPD_LAST =5579,
-  XED_IFORMFL_VPBLENDW_FIRST =5580, +  XED_IFORMFL_VMINMAXPH_FIRST =5580,
-  XED_IFORMFL_VPBLENDW_LAST =5583, +  XED_IFORMFL_VMINMAXPH_LAST =5585,
-  XED_IFORMFL_VPBROADCASTB_FIRST =5584, +  XED_IFORMFL_VMINMAXPS_FIRST =5586,
-  XED_IFORMFL_VPBROADCASTB_LAST =5596, +  XED_IFORMFL_VMINMAXPS_LAST =5591,
-  XED_IFORMFL_VPBROADCASTD_FIRST =5597, +  XED_IFORMFL_VMINMAXSD_FIRST =5592,
-  XED_IFORMFL_VPBROADCASTD_LAST =5609, +  XED_IFORMFL_VMINMAXSD_LAST =5593,
-  XED_IFORMFL_VPBROADCASTMB2Q_FIRST =5610, +  XED_IFORMFL_VMINMAXSH_FIRST =5594,
-  XED_IFORMFL_VPBROADCASTMB2Q_LAST =5612, +  XED_IFORMFL_VMINMAXSH_LAST =5595,
-  XED_IFORMFL_VPBROADCASTMW2D_FIRST =5613, +  XED_IFORMFL_VMINMAXSS_FIRST =5596,
-  XED_IFORMFL_VPBROADCASTMW2D_LAST =5615, +  XED_IFORMFL_VMINMAXSS_LAST =5597,
-  XED_IFORMFL_VPBROADCASTQ_FIRST =5616, +  XED_IFORMFL_VMINPBF16_FIRST =5598,
-  XED_IFORMFL_VPBROADCASTQ_LAST =5628, +  XED_IFORMFL_VMINPBF16_LAST =5603,
-  XED_IFORMFL_VPBROADCASTW_FIRST =5629, +  XED_IFORMFL_VMINPD_FIRST =5604,
-  XED_IFORMFL_VPBROADCASTW_LAST =5641, +  XED_IFORMFL_VMINPD_LAST =5614,
-  XED_IFORMFL_VPCLMULQDQ_FIRST =5642, +  XED_IFORMFL_VMINPH_FIRST =5615,
-  XED_IFORMFL_VPCLMULQDQ_LAST =5651, +  XED_IFORMFL_VMINPH_LAST =5621,
-  XED_IFORMFL_VPCMOV_FIRST =5652, +  XED_IFORMFL_VMINPS_FIRST =5622,
-  XED_IFORMFL_VPCMOV_LAST =5657, +  XED_IFORMFL_VMINPS_LAST =5632,
-  XED_IFORMFL_VPCMPB_FIRST =5658, +  XED_IFORMFL_VMINSD_FIRST =5633,
-  XED_IFORMFL_VPCMPB_LAST =5663, +  XED_IFORMFL_VMINSD_LAST =5637,
-  XED_IFORMFL_VPCMPD_FIRST =5664, +  XED_IFORMFL_VMINSH_FIRST =5638,
-  XED_IFORMFL_VPCMPD_LAST =5669, +  XED_IFORMFL_VMINSH_LAST =5640,
-  XED_IFORMFL_VPCMPEQB_FIRST =5670, +  XED_IFORMFL_VMINSS_FIRST =5641,
-  XED_IFORMFL_VPCMPEQB_LAST =5679, +  XED_IFORMFL_VMINSS_LAST =5645,
-  XED_IFORMFL_VPCMPEQD_FIRST =5680, +  XED_IFORMFL_VMLAUNCH_FIRST =5646,
-  XED_IFORMFL_VPCMPEQD_LAST =5689, +  XED_IFORMFL_VMLAUNCH_LAST =5646,
-  XED_IFORMFL_VPCMPEQQ_FIRST =5690, +  XED_IFORMFL_VMLOAD_FIRST =5647,
-  XED_IFORMFL_VPCMPEQQ_LAST =5699, +  XED_IFORMFL_VMLOAD_LAST =5647,
-  XED_IFORMFL_VPCMPEQW_FIRST =5700, +  XED_IFORMFL_VMMCALL_FIRST =5648,
-  XED_IFORMFL_VPCMPEQW_LAST =5709, +  XED_IFORMFL_VMMCALL_LAST =5648,
-  XED_IFORMFL_VPCMPESTRI_FIRST =5710, +  XED_IFORMFL_VMOVAPD_FIRST =5649,
-  XED_IFORMFL_VPCMPESTRI_LAST =5711, +  XED_IFORMFL_VMOVAPD_LAST =5665,
-  XED_IFORMFL_VPCMPESTRI64_FIRST =5712, +  XED_IFORMFL_VMOVAPS_FIRST =5666,
-  XED_IFORMFL_VPCMPESTRI64_LAST =5713, +  XED_IFORMFL_VMOVAPS_LAST =5682,
-  XED_IFORMFL_VPCMPESTRM_FIRST =5714, +  XED_IFORMFL_VMOVD_FIRST =5683,
-  XED_IFORMFL_VPCMPESTRM_LAST =5715, +  XED_IFORMFL_VMOVD_LAST =5693,
-  XED_IFORMFL_VPCMPESTRM64_FIRST =5716, +  XED_IFORMFL_VMOVDDUP_FIRST =5694,
-  XED_IFORMFL_VPCMPESTRM64_LAST =5717, +  XED_IFORMFL_VMOVDDUP_LAST =5703,
-  XED_IFORMFL_VPCMPGTB_FIRST =5718, +  XED_IFORMFL_VMOVDQA_FIRST =5704,
-  XED_IFORMFL_VPCMPGTB_LAST =5727, +  XED_IFORMFL_VMOVDQA_LAST =5711,
-  XED_IFORMFL_VPCMPGTD_FIRST =5728, +  XED_IFORMFL_VMOVDQA32_FIRST =5712,
-  XED_IFORMFL_VPCMPGTD_LAST =5737, +  XED_IFORMFL_VMOVDQA32_LAST =5720,
-  XED_IFORMFL_VPCMPGTQ_FIRST =5738, +  XED_IFORMFL_VMOVDQA64_FIRST =5721,
-  XED_IFORMFL_VPCMPGTQ_LAST =5747, +  XED_IFORMFL_VMOVDQA64_LAST =5729,
-  XED_IFORMFL_VPCMPGTW_FIRST =5748, +  XED_IFORMFL_VMOVDQU_FIRST =5730,
-  XED_IFORMFL_VPCMPGTW_LAST =5757, +  XED_IFORMFL_VMOVDQU_LAST =5737,
-  XED_IFORMFL_VPCMPISTRI_FIRST =5758, +  XED_IFORMFL_VMOVDQU16_FIRST =5738,
-  XED_IFORMFL_VPCMPISTRI_LAST =5759, +  XED_IFORMFL_VMOVDQU16_LAST =5746,
-  XED_IFORMFL_VPCMPISTRI64_FIRST =5760, +  XED_IFORMFL_VMOVDQU32_FIRST =5747,
-  XED_IFORMFL_VPCMPISTRI64_LAST =5761, +  XED_IFORMFL_VMOVDQU32_LAST =5755,
-  XED_IFORMFL_VPCMPISTRM_FIRST =5762, +  XED_IFORMFL_VMOVDQU64_FIRST =5756,
-  XED_IFORMFL_VPCMPISTRM_LAST =5763, +  XED_IFORMFL_VMOVDQU64_LAST =5764,
-  XED_IFORMFL_VPCMPQ_FIRST =5764, +  XED_IFORMFL_VMOVDQU8_FIRST =5765,
-  XED_IFORMFL_VPCMPQ_LAST =5769, +  XED_IFORMFL_VMOVDQU8_LAST =5773,
-  XED_IFORMFL_VPCMPUB_FIRST =5770, +  XED_IFORMFL_VMOVHLPS_FIRST =5774,
-  XED_IFORMFL_VPCMPUB_LAST =5775, +  XED_IFORMFL_VMOVHLPS_LAST =5775,
-  XED_IFORMFL_VPCMPUD_FIRST =5776, +  XED_IFORMFL_VMOVHPD_FIRST =5776,
-  XED_IFORMFL_VPCMPUD_LAST =5781, +  XED_IFORMFL_VMOVHPD_LAST =5779,
-  XED_IFORMFL_VPCMPUQ_FIRST =5782, +  XED_IFORMFL_VMOVHPS_FIRST =5780,
-  XED_IFORMFL_VPCMPUQ_LAST =5787, +  XED_IFORMFL_VMOVHPS_LAST =5783,
-  XED_IFORMFL_VPCMPUW_FIRST =5788, +  XED_IFORMFL_VMOVLHPS_FIRST =5784,
-  XED_IFORMFL_VPCMPUW_LAST =5793, +  XED_IFORMFL_VMOVLHPS_LAST =5785,
-  XED_IFORMFL_VPCMPW_FIRST =5794, +  XED_IFORMFL_VMOVLPD_FIRST =5786,
-  XED_IFORMFL_VPCMPW_LAST =5799, +  XED_IFORMFL_VMOVLPD_LAST =5789,
-  XED_IFORMFL_VPCOMB_FIRST =5800, +  XED_IFORMFL_VMOVLPS_FIRST =5790,
-  XED_IFORMFL_VPCOMB_LAST =5801, +  XED_IFORMFL_VMOVLPS_LAST =5793,
-  XED_IFORMFL_VPCOMD_FIRST =5802, +  XED_IFORMFL_VMOVMSKPD_FIRST =5794,
-  XED_IFORMFL_VPCOMD_LAST =5803, +  XED_IFORMFL_VMOVMSKPD_LAST =5795,
-  XED_IFORMFL_VPCOMPRESSB_FIRST =5804, +  XED_IFORMFL_VMOVMSKPS_FIRST =5796,
-  XED_IFORMFL_VPCOMPRESSB_LAST =5809, +  XED_IFORMFL_VMOVMSKPS_LAST =5797,
-  XED_IFORMFL_VPCOMPRESSD_FIRST =5810, +  XED_IFORMFL_VMOVNTDQ_FIRST =5798,
-  XED_IFORMFL_VPCOMPRESSD_LAST =5815, +  XED_IFORMFL_VMOVNTDQ_LAST =5802,
-  XED_IFORMFL_VPCOMPRESSQ_FIRST =5816, +  XED_IFORMFL_VMOVNTDQA_FIRST =5803,
-  XED_IFORMFL_VPCOMPRESSQ_LAST =5821, +  XED_IFORMFL_VMOVNTDQA_LAST =5807,
-  XED_IFORMFL_VPCOMPRESSW_FIRST =5822, +  XED_IFORMFL_VMOVNTPD_FIRST =5808,
-  XED_IFORMFL_VPCOMPRESSW_LAST =5827, +  XED_IFORMFL_VMOVNTPD_LAST =5812,
-  XED_IFORMFL_VPCOMQ_FIRST =5828, +  XED_IFORMFL_VMOVNTPS_FIRST =5813,
-  XED_IFORMFL_VPCOMQ_LAST =5829, +  XED_IFORMFL_VMOVNTPS_LAST =5817,
-  XED_IFORMFL_VPCOMUB_FIRST =5830, +  XED_IFORMFL_VMOVQ_FIRST =5818,
-  XED_IFORMFL_VPCOMUB_LAST =5831, +  XED_IFORMFL_VMOVQ_LAST =5830,
-  XED_IFORMFL_VPCOMUD_FIRST =5832, +  XED_IFORMFL_VMOVRSB_FIRST =5831,
-  XED_IFORMFL_VPCOMUD_LAST =5833, +  XED_IFORMFL_VMOVRSB_LAST =5833,
-  XED_IFORMFL_VPCOMUQ_FIRST =5834, +  XED_IFORMFL_VMOVRSD_FIRST =5834,
-  XED_IFORMFL_VPCOMUQ_LAST =5835, +  XED_IFORMFL_VMOVRSD_LAST =5836,
-  XED_IFORMFL_VPCOMUW_FIRST =5836, +  XED_IFORMFL_VMOVRSQ_FIRST =5837,
-  XED_IFORMFL_VPCOMUW_LAST =5837, +  XED_IFORMFL_VMOVRSQ_LAST =5839,
-  XED_IFORMFL_VPCOMW_FIRST =5838, +  XED_IFORMFL_VMOVRSW_FIRST =5840,
-  XED_IFORMFL_VPCOMW_LAST =5839, +  XED_IFORMFL_VMOVRSW_LAST =5842,
-  XED_IFORMFL_VPCONFLICTD_FIRST =5840, +  XED_IFORMFL_VMOVSD_FIRST =5843,
-  XED_IFORMFL_VPCONFLICTD_LAST =5845, +  XED_IFORMFL_VMOVSD_LAST =5849,
-  XED_IFORMFL_VPCONFLICTQ_FIRST =5846, +  XED_IFORMFL_VMOVSH_FIRST =5850,
-  XED_IFORMFL_VPCONFLICTQ_LAST =5851, +  XED_IFORMFL_VMOVSH_LAST =5852,
-  XED_IFORMFL_VPDPBSSD_FIRST =5852, +  XED_IFORMFL_VMOVSHDUP_FIRST =5853,
-  XED_IFORMFL_VPDPBSSD_LAST =5855, +  XED_IFORMFL_VMOVSHDUP_LAST =5862,
-  XED_IFORMFL_VPDPBSSDS_FIRST =5856, +  XED_IFORMFL_VMOVSLDUP_FIRST =5863,
-  XED_IFORMFL_VPDPBSSDS_LAST =5859, +  XED_IFORMFL_VMOVSLDUP_LAST =5872,
-  XED_IFORMFL_VPDPBSUD_FIRST =5860, +  XED_IFORMFL_VMOVSS_FIRST =5873,
-  XED_IFORMFL_VPDPBSUD_LAST =5863, +  XED_IFORMFL_VMOVSS_LAST =5879,
-  XED_IFORMFL_VPDPBSUDS_FIRST =5864, +  XED_IFORMFL_VMOVUPD_FIRST =5880,
-  XED_IFORMFL_VPDPBSUDS_LAST =5867, +  XED_IFORMFL_VMOVUPD_LAST =5896,
-  XED_IFORMFL_VPDPBUSD_FIRST =5868, +  XED_IFORMFL_VMOVUPS_FIRST =5897,
-  XED_IFORMFL_VPDPBUSD_LAST =5877, +  XED_IFORMFL_VMOVUPS_LAST =5913,
-  XED_IFORMFL_VPDPBUSDS_FIRST =5878, +  XED_IFORMFL_VMOVW_FIRST =5914,
-  XED_IFORMFL_VPDPBUSDS_LAST =5887, +  XED_IFORMFL_VMOVW_LAST =5920,
-  XED_IFORMFL_VPDPBUUD_FIRST =5888, +  XED_IFORMFL_VMPSADBW_FIRST =5921,
-  XED_IFORMFL_VPDPBUUD_LAST =5891, +  XED_IFORMFL_VMPSADBW_LAST =5930,
-  XED_IFORMFL_VPDPBUUDS_FIRST =5892, +  XED_IFORMFL_VMPTRLD_FIRST =5931,
-  XED_IFORMFL_VPDPBUUDS_LAST =5895, +  XED_IFORMFL_VMPTRLD_LAST =5931,
-  XED_IFORMFL_VPDPWSSD_FIRST =5896, +  XED_IFORMFL_VMPTRST_FIRST =5932,
-  XED_IFORMFL_VPDPWSSD_LAST =5905, +  XED_IFORMFL_VMPTRST_LAST =5932,
-  XED_IFORMFL_VPDPWSSDS_FIRST =5906, +  XED_IFORMFL_VMREAD_FIRST =5933,
-  XED_IFORMFL_VPDPWSSDS_LAST =5915, +  XED_IFORMFL_VMREAD_LAST =5936,
-  XED_IFORMFL_VPDPWSUD_FIRST =5916, +  XED_IFORMFL_VMRESUME_FIRST =5937,
-  XED_IFORMFL_VPDPWSUD_LAST =5919, +  XED_IFORMFL_VMRESUME_LAST =5937,
-  XED_IFORMFL_VPDPWSUDS_FIRST =5920, +  XED_IFORMFL_VMRUN_FIRST =5938,
-  XED_IFORMFL_VPDPWSUDS_LAST =5923, +  XED_IFORMFL_VMRUN_LAST =5938,
-  XED_IFORMFL_VPDPWUSD_FIRST =5924, +  XED_IFORMFL_VMSAVE_FIRST =5939,
-  XED_IFORMFL_VPDPWUSD_LAST =5927, +  XED_IFORMFL_VMSAVE_LAST =5939,
-  XED_IFORMFL_VPDPWUSDS_FIRST =5928, +  XED_IFORMFL_VMULNEPBF16_FIRST =5940,
-  XED_IFORMFL_VPDPWUSDS_LAST =5931, +  XED_IFORMFL_VMULNEPBF16_LAST =5945,
-  XED_IFORMFL_VPDPWUUD_FIRST =5932, +  XED_IFORMFL_VMULPD_FIRST =5946,
-  XED_IFORMFL_VPDPWUUD_LAST =5935, +  XED_IFORMFL_VMULPD_LAST =5956,
-  XED_IFORMFL_VPDPWUUDS_FIRST =5936, +  XED_IFORMFL_VMULPH_FIRST =5957,
-  XED_IFORMFL_VPDPWUUDS_LAST =5939, +  XED_IFORMFL_VMULPH_LAST =5963,
-  XED_IFORMFL_VPERM2F128_FIRST =5940, +  XED_IFORMFL_VMULPS_FIRST =5964,
-  XED_IFORMFL_VPERM2F128_LAST =5941, +  XED_IFORMFL_VMULPS_LAST =5974,
-  XED_IFORMFL_VPERM2I128_FIRST =5942, +  XED_IFORMFL_VMULSD_FIRST =5975,
-  XED_IFORMFL_VPERM2I128_LAST =5943, +  XED_IFORMFL_VMULSD_LAST =5979,
-  XED_IFORMFL_VPERMB_FIRST =5944, +  XED_IFORMFL_VMULSH_FIRST =5980,
-  XED_IFORMFL_VPERMB_LAST =5949, +  XED_IFORMFL_VMULSH_LAST =5982,
-  XED_IFORMFL_VPERMD_FIRST =5950, +  XED_IFORMFL_VMULSS_FIRST =5983,
-  XED_IFORMFL_VPERMD_LAST =5955, +  XED_IFORMFL_VMULSS_LAST =5987,
-  XED_IFORMFL_VPERMI2B_FIRST =5956, +  XED_IFORMFL_VMWRITE_FIRST =5988,
-  XED_IFORMFL_VPERMI2B_LAST =5961, +  XED_IFORMFL_VMWRITE_LAST =5991,
-  XED_IFORMFL_VPERMI2D_FIRST =5962, +  XED_IFORMFL_VMXOFF_FIRST =5992,
-  XED_IFORMFL_VPERMI2D_LAST =5967, +  XED_IFORMFL_VMXOFF_LAST =5992,
-  XED_IFORMFL_VPERMI2PD_FIRST =5968, +  XED_IFORMFL_VMXON_FIRST =5993,
-  XED_IFORMFL_VPERMI2PD_LAST =5973, +  XED_IFORMFL_VMXON_LAST =5993,
-  XED_IFORMFL_VPERMI2PS_FIRST =5974, +  XED_IFORMFL_VORPD_FIRST =5994,
-  XED_IFORMFL_VPERMI2PS_LAST =5979, +  XED_IFORMFL_VORPD_LAST =6003,
-  XED_IFORMFL_VPERMI2Q_FIRST =5980, +  XED_IFORMFL_VORPS_FIRST =6004,
-  XED_IFORMFL_VPERMI2Q_LAST =5985, +  XED_IFORMFL_VORPS_LAST =6013,
-  XED_IFORMFL_VPERMI2W_FIRST =5986, +  XED_IFORMFL_VP2INTERSECTD_FIRST =6014,
-  XED_IFORMFL_VPERMI2W_LAST =5991, +  XED_IFORMFL_VP2INTERSECTD_LAST =6019,
-  XED_IFORMFL_VPERMIL2PD_FIRST =5992, +  XED_IFORMFL_VP2INTERSECTQ_FIRST =6020,
-  XED_IFORMFL_VPERMIL2PD_LAST =5997, +  XED_IFORMFL_VP2INTERSECTQ_LAST =6025,
-  XED_IFORMFL_VPERMIL2PS_FIRST =5998, +  XED_IFORMFL_VP4DPWSSD_FIRST =6026,
-  XED_IFORMFL_VPERMIL2PS_LAST =6003, +  XED_IFORMFL_VP4DPWSSD_LAST =6026,
-  XED_IFORMFL_VPERMILPD_FIRST =6004, +  XED_IFORMFL_VP4DPWSSDS_FIRST =6027,
-  XED_IFORMFL_VPERMILPD_LAST =6023, +  XED_IFORMFL_VP4DPWSSDS_LAST =6027,
-  XED_IFORMFL_VPERMILPS_FIRST =6024, +  XED_IFORMFL_VPABSB_FIRST =6028,
-  XED_IFORMFL_VPERMILPS_LAST =6043, +  XED_IFORMFL_VPABSB_LAST =6037,
-  XED_IFORMFL_VPERMPD_FIRST =6044, +  XED_IFORMFL_VPABSD_FIRST =6038,
-  XED_IFORMFL_VPERMPD_LAST =6053, +  XED_IFORMFL_VPABSD_LAST =6047,
-  XED_IFORMFL_VPERMPS_FIRST =6054, +  XED_IFORMFL_VPABSQ_FIRST =6048,
-  XED_IFORMFL_VPERMPS_LAST =6059, +  XED_IFORMFL_VPABSQ_LAST =6053,
-  XED_IFORMFL_VPERMQ_FIRST =6060, +  XED_IFORMFL_VPABSW_FIRST =6054,
-  XED_IFORMFL_VPERMQ_LAST =6069, +  XED_IFORMFL_VPABSW_LAST =6063,
-  XED_IFORMFL_VPERMT2B_FIRST =6070, +  XED_IFORMFL_VPACKSSDW_FIRST =6064,
-  XED_IFORMFL_VPERMT2B_LAST =6075, +  XED_IFORMFL_VPACKSSDW_LAST =6073,
-  XED_IFORMFL_VPERMT2D_FIRST =6076, +  XED_IFORMFL_VPACKSSWB_FIRST =6074,
-  XED_IFORMFL_VPERMT2D_LAST =6081, +  XED_IFORMFL_VPACKSSWB_LAST =6083,
-  XED_IFORMFL_VPERMT2PD_FIRST =6082, +  XED_IFORMFL_VPACKUSDW_FIRST =6084,
-  XED_IFORMFL_VPERMT2PD_LAST =6087, +  XED_IFORMFL_VPACKUSDW_LAST =6093,
-  XED_IFORMFL_VPERMT2PS_FIRST =6088, +  XED_IFORMFL_VPACKUSWB_FIRST =6094,
-  XED_IFORMFL_VPERMT2PS_LAST =6093, +  XED_IFORMFL_VPACKUSWB_LAST =6103,
-  XED_IFORMFL_VPERMT2Q_FIRST =6094, +  XED_IFORMFL_VPADDB_FIRST =6104,
-  XED_IFORMFL_VPERMT2Q_LAST =6099, +  XED_IFORMFL_VPADDB_LAST =6113,
-  XED_IFORMFL_VPERMT2W_FIRST =6100, +  XED_IFORMFL_VPADDD_FIRST =6114,
-  XED_IFORMFL_VPERMT2W_LAST =6105, +  XED_IFORMFL_VPADDD_LAST =6123,
-  XED_IFORMFL_VPERMW_FIRST =6106, +  XED_IFORMFL_VPADDQ_FIRST =6124,
-  XED_IFORMFL_VPERMW_LAST =6111, +  XED_IFORMFL_VPADDQ_LAST =6133,
-  XED_IFORMFL_VPEXPANDB_FIRST =6112, +  XED_IFORMFL_VPADDSB_FIRST =6134,
-  XED_IFORMFL_VPEXPANDB_LAST =6117, +  XED_IFORMFL_VPADDSB_LAST =6143,
-  XED_IFORMFL_VPEXPANDD_FIRST =6118, +  XED_IFORMFL_VPADDSW_FIRST =6144,
-  XED_IFORMFL_VPEXPANDD_LAST =6123, +  XED_IFORMFL_VPADDSW_LAST =6153,
-  XED_IFORMFL_VPEXPANDQ_FIRST =6124, +  XED_IFORMFL_VPADDUSB_FIRST =6154,
-  XED_IFORMFL_VPEXPANDQ_LAST =6129, +  XED_IFORMFL_VPADDUSB_LAST =6163,
-  XED_IFORMFL_VPEXPANDW_FIRST =6130, +  XED_IFORMFL_VPADDUSW_FIRST =6164,
-  XED_IFORMFL_VPEXPANDW_LAST =6135, +  XED_IFORMFL_VPADDUSW_LAST =6173,
-  XED_IFORMFL_VPEXTRB_FIRST =6136, +  XED_IFORMFL_VPADDW_FIRST =6174,
-  XED_IFORMFL_VPEXTRB_LAST =6139, +  XED_IFORMFL_VPADDW_LAST =6183,
-  XED_IFORMFL_VPEXTRD_FIRST =6140, +  XED_IFORMFL_VPALIGNR_FIRST =6184,
-  XED_IFORMFL_VPEXTRD_LAST =6143, +  XED_IFORMFL_VPALIGNR_LAST =6193,
-  XED_IFORMFL_VPEXTRQ_FIRST =6144, +  XED_IFORMFL_VPAND_FIRST =6194,
-  XED_IFORMFL_VPEXTRQ_LAST =6147, +  XED_IFORMFL_VPAND_LAST =6197,
-  XED_IFORMFL_VPEXTRW_FIRST =6148, +  XED_IFORMFL_VPANDD_FIRST =6198,
-  XED_IFORMFL_VPEXTRW_LAST =6152, +  XED_IFORMFL_VPANDD_LAST =6203,
-  XED_IFORMFL_VPEXTRW_C5_FIRST =6153, +  XED_IFORMFL_VPANDN_FIRST =6204,
-  XED_IFORMFL_VPEXTRW_C5_LAST =6153, +  XED_IFORMFL_VPANDN_LAST =6207,
-  XED_IFORMFL_VPGATHERDD_FIRST =6154, +  XED_IFORMFL_VPANDND_FIRST =6208,
-  XED_IFORMFL_VPGATHERDD_LAST =6158, +  XED_IFORMFL_VPANDND_LAST =6213,
-  XED_IFORMFL_VPGATHERDQ_FIRST =6159, +  XED_IFORMFL_VPANDNQ_FIRST =6214,
-  XED_IFORMFL_VPGATHERDQ_LAST =6163, +  XED_IFORMFL_VPANDNQ_LAST =6219,
-  XED_IFORMFL_VPGATHERQD_FIRST =6164, +  XED_IFORMFL_VPANDQ_FIRST =6220,
-  XED_IFORMFL_VPGATHERQD_LAST =6168, +  XED_IFORMFL_VPANDQ_LAST =6225,
-  XED_IFORMFL_VPGATHERQQ_FIRST =6169, +  XED_IFORMFL_VPAVGB_FIRST =6226,
-  XED_IFORMFL_VPGATHERQQ_LAST =6173, +  XED_IFORMFL_VPAVGB_LAST =6235,
-  XED_IFORMFL_VPHADDBD_FIRST =6174, +  XED_IFORMFL_VPAVGW_FIRST =6236,
-  XED_IFORMFL_VPHADDBD_LAST =6175, +  XED_IFORMFL_VPAVGW_LAST =6245,
-  XED_IFORMFL_VPHADDBQ_FIRST =6176, +  XED_IFORMFL_VPBLENDD_FIRST =6246,
-  XED_IFORMFL_VPHADDBQ_LAST =6177, +  XED_IFORMFL_VPBLENDD_LAST =6249,
-  XED_IFORMFL_VPHADDBW_FIRST =6178, +  XED_IFORMFL_VPBLENDMB_FIRST =6250,
-  XED_IFORMFL_VPHADDBW_LAST =6179, +  XED_IFORMFL_VPBLENDMB_LAST =6255,
-  XED_IFORMFL_VPHADDD_FIRST =6180, +  XED_IFORMFL_VPBLENDMD_FIRST =6256,
-  XED_IFORMFL_VPHADDD_LAST =6183, +  XED_IFORMFL_VPBLENDMD_LAST =6261,
-  XED_IFORMFL_VPHADDDQ_FIRST =6184, +  XED_IFORMFL_VPBLENDMQ_FIRST =6262,
-  XED_IFORMFL_VPHADDDQ_LAST =6185, +  XED_IFORMFL_VPBLENDMQ_LAST =6267,
-  XED_IFORMFL_VPHADDSW_FIRST =6186, +  XED_IFORMFL_VPBLENDMW_FIRST =6268,
-  XED_IFORMFL_VPHADDSW_LAST =6189, +  XED_IFORMFL_VPBLENDMW_LAST =6273,
-  XED_IFORMFL_VPHADDUBD_FIRST =6190, +  XED_IFORMFL_VPBLENDVB_FIRST =6274,
-  XED_IFORMFL_VPHADDUBD_LAST =6191, +  XED_IFORMFL_VPBLENDVB_LAST =6277,
-  XED_IFORMFL_VPHADDUBQ_FIRST =6192, +  XED_IFORMFL_VPBLENDW_FIRST =6278,
-  XED_IFORMFL_VPHADDUBQ_LAST =6193, +  XED_IFORMFL_VPBLENDW_LAST =6281,
-  XED_IFORMFL_VPHADDUBW_FIRST =6194, +  XED_IFORMFL_VPBROADCASTB_FIRST =6282,
-  XED_IFORMFL_VPHADDUBW_LAST =6195, +  XED_IFORMFL_VPBROADCASTB_LAST =6294,
-  XED_IFORMFL_VPHADDUDQ_FIRST =6196, +  XED_IFORMFL_VPBROADCASTD_FIRST =6295,
-  XED_IFORMFL_VPHADDUDQ_LAST =6197, +  XED_IFORMFL_VPBROADCASTD_LAST =6307,
-  XED_IFORMFL_VPHADDUWD_FIRST =6198, +  XED_IFORMFL_VPBROADCASTMB2Q_FIRST =6308,
-  XED_IFORMFL_VPHADDUWD_LAST =6199, +  XED_IFORMFL_VPBROADCASTMB2Q_LAST =6310,
-  XED_IFORMFL_VPHADDUWQ_FIRST =6200, +  XED_IFORMFL_VPBROADCASTMW2D_FIRST =6311,
-  XED_IFORMFL_VPHADDUWQ_LAST =6201, +  XED_IFORMFL_VPBROADCASTMW2D_LAST =6313,
-  XED_IFORMFL_VPHADDW_FIRST =6202, +  XED_IFORMFL_VPBROADCASTQ_FIRST =6314,
-  XED_IFORMFL_VPHADDW_LAST =6205, +  XED_IFORMFL_VPBROADCASTQ_LAST =6326,
-  XED_IFORMFL_VPHADDWD_FIRST =6206, +  XED_IFORMFL_VPBROADCASTW_FIRST =6327,
-  XED_IFORMFL_VPHADDWD_LAST =6207, +  XED_IFORMFL_VPBROADCASTW_LAST =6339,
-  XED_IFORMFL_VPHADDWQ_FIRST =6208, +  XED_IFORMFL_VPCLMULQDQ_FIRST =6340,
-  XED_IFORMFL_VPHADDWQ_LAST =6209, +  XED_IFORMFL_VPCLMULQDQ_LAST =6349,
-  XED_IFORMFL_VPHMINPOSUW_FIRST =6210, +  XED_IFORMFL_VPCMOV_FIRST =6350,
-  XED_IFORMFL_VPHMINPOSUW_LAST =6211, +  XED_IFORMFL_VPCMOV_LAST =6355,
-  XED_IFORMFL_VPHSUBBW_FIRST =6212, +  XED_IFORMFL_VPCMPB_FIRST =6356,
-  XED_IFORMFL_VPHSUBBW_LAST =6213, +  XED_IFORMFL_VPCMPB_LAST =6361,
-  XED_IFORMFL_VPHSUBD_FIRST =6214, +  XED_IFORMFL_VPCMPD_FIRST =6362,
-  XED_IFORMFL_VPHSUBD_LAST =6217, +  XED_IFORMFL_VPCMPD_LAST =6367,
-  XED_IFORMFL_VPHSUBDQ_FIRST =6218, +  XED_IFORMFL_VPCMPEQB_FIRST =6368,
-  XED_IFORMFL_VPHSUBDQ_LAST =6219, +  XED_IFORMFL_VPCMPEQB_LAST =6377,
-  XED_IFORMFL_VPHSUBSW_FIRST =6220, +  XED_IFORMFL_VPCMPEQD_FIRST =6378,
-  XED_IFORMFL_VPHSUBSW_LAST =6223, +  XED_IFORMFL_VPCMPEQD_LAST =6387,
-  XED_IFORMFL_VPHSUBW_FIRST =6224, +  XED_IFORMFL_VPCMPEQQ_FIRST =6388,
-  XED_IFORMFL_VPHSUBW_LAST =6227, +  XED_IFORMFL_VPCMPEQQ_LAST =6397,
-  XED_IFORMFL_VPHSUBWD_FIRST =6228, +  XED_IFORMFL_VPCMPEQW_FIRST =6398,
-  XED_IFORMFL_VPHSUBWD_LAST =6229, +  XED_IFORMFL_VPCMPEQW_LAST =6407,
-  XED_IFORMFL_VPINSRB_FIRST =6230, +  XED_IFORMFL_VPCMPESTRI_FIRST =6408,
-  XED_IFORMFL_VPINSRB_LAST =6233, +  XED_IFORMFL_VPCMPESTRI_LAST =6409,
-  XED_IFORMFL_VPINSRD_FIRST =6234, +  XED_IFORMFL_VPCMPESTRI64_FIRST =6410,
-  XED_IFORMFL_VPINSRD_LAST =6237, +  XED_IFORMFL_VPCMPESTRI64_LAST =6411,
-  XED_IFORMFL_VPINSRQ_FIRST =6238, +  XED_IFORMFL_VPCMPESTRM_FIRST =6412,
-  XED_IFORMFL_VPINSRQ_LAST =6241, +  XED_IFORMFL_VPCMPESTRM_LAST =6413,
-  XED_IFORMFL_VPINSRW_FIRST =6242, +  XED_IFORMFL_VPCMPESTRM64_FIRST =6414,
-  XED_IFORMFL_VPINSRW_LAST =6245, +  XED_IFORMFL_VPCMPESTRM64_LAST =6415,
-  XED_IFORMFL_VPLZCNTD_FIRST =6246, +  XED_IFORMFL_VPCMPGTB_FIRST =6416,
-  XED_IFORMFL_VPLZCNTD_LAST =6251, +  XED_IFORMFL_VPCMPGTB_LAST =6425,
-  XED_IFORMFL_VPLZCNTQ_FIRST =6252, +  XED_IFORMFL_VPCMPGTD_FIRST =6426,
-  XED_IFORMFL_VPLZCNTQ_LAST =6257, +  XED_IFORMFL_VPCMPGTD_LAST =6435,
-  XED_IFORMFL_VPMACSDD_FIRST =6258, +  XED_IFORMFL_VPCMPGTQ_FIRST =6436,
-  XED_IFORMFL_VPMACSDD_LAST =6259, +  XED_IFORMFL_VPCMPGTQ_LAST =6445,
-  XED_IFORMFL_VPMACSDQH_FIRST =6260, +  XED_IFORMFL_VPCMPGTW_FIRST =6446,
-  XED_IFORMFL_VPMACSDQH_LAST =6261, +  XED_IFORMFL_VPCMPGTW_LAST =6455,
-  XED_IFORMFL_VPMACSDQL_FIRST =6262, +  XED_IFORMFL_VPCMPISTRI_FIRST =6456,
-  XED_IFORMFL_VPMACSDQL_LAST =6263, +  XED_IFORMFL_VPCMPISTRI_LAST =6457,
-  XED_IFORMFL_VPMACSSDD_FIRST =6264, +  XED_IFORMFL_VPCMPISTRI64_FIRST =6458,
-  XED_IFORMFL_VPMACSSDD_LAST =6265, +  XED_IFORMFL_VPCMPISTRI64_LAST =6459,
-  XED_IFORMFL_VPMACSSDQH_FIRST =6266, +  XED_IFORMFL_VPCMPISTRM_FIRST =6460,
-  XED_IFORMFL_VPMACSSDQH_LAST =6267, +  XED_IFORMFL_VPCMPISTRM_LAST =6461,
-  XED_IFORMFL_VPMACSSDQL_FIRST =6268, +  XED_IFORMFL_VPCMPQ_FIRST =6462,
-  XED_IFORMFL_VPMACSSDQL_LAST =6269, +  XED_IFORMFL_VPCMPQ_LAST =6467,
-  XED_IFORMFL_VPMACSSWD_FIRST =6270, +  XED_IFORMFL_VPCMPUB_FIRST =6468,
-  XED_IFORMFL_VPMACSSWD_LAST =6271, +  XED_IFORMFL_VPCMPUB_LAST =6473,
-  XED_IFORMFL_VPMACSSWW_FIRST =6272, +  XED_IFORMFL_VPCMPUD_FIRST =6474,
-  XED_IFORMFL_VPMACSSWW_LAST =6273, +  XED_IFORMFL_VPCMPUD_LAST =6479,
-  XED_IFORMFL_VPMACSWD_FIRST =6274, +  XED_IFORMFL_VPCMPUQ_FIRST =6480,
-  XED_IFORMFL_VPMACSWD_LAST =6275, +  XED_IFORMFL_VPCMPUQ_LAST =6485,
-  XED_IFORMFL_VPMACSWW_FIRST =6276, +  XED_IFORMFL_VPCMPUW_FIRST =6486,
-  XED_IFORMFL_VPMACSWW_LAST =6277, +  XED_IFORMFL_VPCMPUW_LAST =6491,
-  XED_IFORMFL_VPMADCSSWD_FIRST =6278, +  XED_IFORMFL_VPCMPW_FIRST =6492,
-  XED_IFORMFL_VPMADCSSWD_LAST =6279, +  XED_IFORMFL_VPCMPW_LAST =6497,
-  XED_IFORMFL_VPMADCSWD_FIRST =6280, +  XED_IFORMFL_VPCOMB_FIRST =6498,
-  XED_IFORMFL_VPMADCSWD_LAST =6281, +  XED_IFORMFL_VPCOMB_LAST =6499,
-  XED_IFORMFL_VPMADD52HUQ_FIRST =6282, +  XED_IFORMFL_VPCOMD_FIRST =6500,
-  XED_IFORMFL_VPMADD52HUQ_LAST =6291, +  XED_IFORMFL_VPCOMD_LAST =6501,
-  XED_IFORMFL_VPMADD52LUQ_FIRST =6292, +  XED_IFORMFL_VPCOMPRESSB_FIRST =6502,
-  XED_IFORMFL_VPMADD52LUQ_LAST =6301, +  XED_IFORMFL_VPCOMPRESSB_LAST =6507,
-  XED_IFORMFL_VPMADDUBSW_FIRST =6302, +  XED_IFORMFL_VPCOMPRESSD_FIRST =6508,
-  XED_IFORMFL_VPMADDUBSW_LAST =6311, +  XED_IFORMFL_VPCOMPRESSD_LAST =6513,
-  XED_IFORMFL_VPMADDWD_FIRST =6312, +  XED_IFORMFL_VPCOMPRESSQ_FIRST =6514,
-  XED_IFORMFL_VPMADDWD_LAST =6321, +  XED_IFORMFL_VPCOMPRESSQ_LAST =6519,
-  XED_IFORMFL_VPMASKMOVD_FIRST =6322, +  XED_IFORMFL_VPCOMPRESSW_FIRST =6520,
-  XED_IFORMFL_VPMASKMOVD_LAST =6325, +  XED_IFORMFL_VPCOMPRESSW_LAST =6525,
-  XED_IFORMFL_VPMASKMOVQ_FIRST =6326, +  XED_IFORMFL_VPCOMQ_FIRST =6526,
-  XED_IFORMFL_VPMASKMOVQ_LAST =6329, +  XED_IFORMFL_VPCOMQ_LAST =6527,
-  XED_IFORMFL_VPMAXSB_FIRST =6330, +  XED_IFORMFL_VPCOMUB_FIRST =6528,
-  XED_IFORMFL_VPMAXSB_LAST =6339, +  XED_IFORMFL_VPCOMUB_LAST =6529,
-  XED_IFORMFL_VPMAXSD_FIRST =6340, +  XED_IFORMFL_VPCOMUD_FIRST =6530,
-  XED_IFORMFL_VPMAXSD_LAST =6349, +  XED_IFORMFL_VPCOMUD_LAST =6531,
-  XED_IFORMFL_VPMAXSQ_FIRST =6350, +  XED_IFORMFL_VPCOMUQ_FIRST =6532,
-  XED_IFORMFL_VPMAXSQ_LAST =6355, +  XED_IFORMFL_VPCOMUQ_LAST =6533,
-  XED_IFORMFL_VPMAXSW_FIRST =6356, +  XED_IFORMFL_VPCOMUW_FIRST =6534,
-  XED_IFORMFL_VPMAXSW_LAST =6365, +  XED_IFORMFL_VPCOMUW_LAST =6535,
-  XED_IFORMFL_VPMAXUB_FIRST =6366, +  XED_IFORMFL_VPCOMW_FIRST =6536,
-  XED_IFORMFL_VPMAXUB_LAST =6375, +  XED_IFORMFL_VPCOMW_LAST =6537,
-  XED_IFORMFL_VPMAXUD_FIRST =6376, +  XED_IFORMFL_VPCONFLICTD_FIRST =6538,
-  XED_IFORMFL_VPMAXUD_LAST =6385, +  XED_IFORMFL_VPCONFLICTD_LAST =6543,
-  XED_IFORMFL_VPMAXUQ_FIRST =6386, +  XED_IFORMFL_VPCONFLICTQ_FIRST =6544,
-  XED_IFORMFL_VPMAXUQ_LAST =6391, +  XED_IFORMFL_VPCONFLICTQ_LAST =6549,
-  XED_IFORMFL_VPMAXUW_FIRST =6392, +  XED_IFORMFL_VPDPBSSD_FIRST =6550,
-  XED_IFORMFL_VPMAXUW_LAST =6401, +  XED_IFORMFL_VPDPBSSD_LAST =6559,
-  XED_IFORMFL_VPMINSB_FIRST =6402, +  XED_IFORMFL_VPDPBSSDS_FIRST =6560,
-  XED_IFORMFL_VPMINSB_LAST =6411, +  XED_IFORMFL_VPDPBSSDS_LAST =6569,
-  XED_IFORMFL_VPMINSD_FIRST =6412, +  XED_IFORMFL_VPDPBSUD_FIRST =6570,
-  XED_IFORMFL_VPMINSD_LAST =6421, +  XED_IFORMFL_VPDPBSUD_LAST =6579,
-  XED_IFORMFL_VPMINSQ_FIRST =6422, +  XED_IFORMFL_VPDPBSUDS_FIRST =6580,
-  XED_IFORMFL_VPMINSQ_LAST =6427, +  XED_IFORMFL_VPDPBSUDS_LAST =6589,
-  XED_IFORMFL_VPMINSW_FIRST =6428, +  XED_IFORMFL_VPDPBUSD_FIRST =6590,
-  XED_IFORMFL_VPMINSW_LAST =6437, +  XED_IFORMFL_VPDPBUSD_LAST =6599,
-  XED_IFORMFL_VPMINUB_FIRST =6438, +  XED_IFORMFL_VPDPBUSDS_FIRST =6600,
-  XED_IFORMFL_VPMINUB_LAST =6447, +  XED_IFORMFL_VPDPBUSDS_LAST =6609,
-  XED_IFORMFL_VPMINUD_FIRST =6448, +  XED_IFORMFL_VPDPBUUD_FIRST =6610,
-  XED_IFORMFL_VPMINUD_LAST =6457, +  XED_IFORMFL_VPDPBUUD_LAST =6619,
-  XED_IFORMFL_VPMINUQ_FIRST =6458, +  XED_IFORMFL_VPDPBUUDS_FIRST =6620,
-  XED_IFORMFL_VPMINUQ_LAST =6463, +  XED_IFORMFL_VPDPBUUDS_LAST =6629,
-  XED_IFORMFL_VPMINUW_FIRST =6464, +  XED_IFORMFL_VPDPWSSD_FIRST =6630,
-  XED_IFORMFL_VPMINUW_LAST =6473, +  XED_IFORMFL_VPDPWSSD_LAST =6639,
-  XED_IFORMFL_VPMOVB2M_FIRST =6474, +  XED_IFORMFL_VPDPWSSDS_FIRST =6640,
-  XED_IFORMFL_VPMOVB2M_LAST =6476, +  XED_IFORMFL_VPDPWSSDS_LAST =6649,
-  XED_IFORMFL_VPMOVD2M_FIRST =6477, +  XED_IFORMFL_VPDPWSUD_FIRST =6650,
-  XED_IFORMFL_VPMOVD2M_LAST =6479, +  XED_IFORMFL_VPDPWSUD_LAST =6659,
-  XED_IFORMFL_VPMOVDB_FIRST =6480, +  XED_IFORMFL_VPDPWSUDS_FIRST =6660,
-  XED_IFORMFL_VPMOVDB_LAST =6485, +  XED_IFORMFL_VPDPWSUDS_LAST =6669,
-  XED_IFORMFL_VPMOVDW_FIRST =6486, +  XED_IFORMFL_VPDPWUSD_FIRST =6670,
-  XED_IFORMFL_VPMOVDW_LAST =6491, +  XED_IFORMFL_VPDPWUSD_LAST =6679,
-  XED_IFORMFL_VPMOVM2B_FIRST =6492, +  XED_IFORMFL_VPDPWUSDS_FIRST =6680,
-  XED_IFORMFL_VPMOVM2B_LAST =6494, +  XED_IFORMFL_VPDPWUSDS_LAST =6689,
-  XED_IFORMFL_VPMOVM2D_FIRST =6495, +  XED_IFORMFL_VPDPWUUD_FIRST =6690,
-  XED_IFORMFL_VPMOVM2D_LAST =6497, +  XED_IFORMFL_VPDPWUUD_LAST =6699,
-  XED_IFORMFL_VPMOVM2Q_FIRST =6498, +  XED_IFORMFL_VPDPWUUDS_FIRST =6700,
-  XED_IFORMFL_VPMOVM2Q_LAST =6500, +  XED_IFORMFL_VPDPWUUDS_LAST =6709,
-  XED_IFORMFL_VPMOVM2W_FIRST =6501, +  XED_IFORMFL_VPERM2F128_FIRST =6710,
-  XED_IFORMFL_VPMOVM2W_LAST =6503, +  XED_IFORMFL_VPERM2F128_LAST =6711,
-  XED_IFORMFL_VPMOVMSKB_FIRST =6504, +  XED_IFORMFL_VPERM2I128_FIRST =6712,
-  XED_IFORMFL_VPMOVMSKB_LAST =6505, +  XED_IFORMFL_VPERM2I128_LAST =6713,
-  XED_IFORMFL_VPMOVQ2M_FIRST =6506, +  XED_IFORMFL_VPERMB_FIRST =6714,
-  XED_IFORMFL_VPMOVQ2M_LAST =6508, +  XED_IFORMFL_VPERMB_LAST =6719,
-  XED_IFORMFL_VPMOVQB_FIRST =6509, +  XED_IFORMFL_VPERMD_FIRST =6720,
-  XED_IFORMFL_VPMOVQB_LAST =6514, +  XED_IFORMFL_VPERMD_LAST =6725,
-  XED_IFORMFL_VPMOVQD_FIRST =6515, +  XED_IFORMFL_VPERMI2B_FIRST =6726,
-  XED_IFORMFL_VPMOVQD_LAST =6520, +  XED_IFORMFL_VPERMI2B_LAST =6731,
-  XED_IFORMFL_VPMOVQW_FIRST =6521, +  XED_IFORMFL_VPERMI2D_FIRST =6732,
-  XED_IFORMFL_VPMOVQW_LAST =6526, +  XED_IFORMFL_VPERMI2D_LAST =6737,
-  XED_IFORMFL_VPMOVSDB_FIRST =6527, +  XED_IFORMFL_VPERMI2PD_FIRST =6738,
-  XED_IFORMFL_VPMOVSDB_LAST =6532, +  XED_IFORMFL_VPERMI2PD_LAST =6743,
-  XED_IFORMFL_VPMOVSDW_FIRST =6533, +  XED_IFORMFL_VPERMI2PS_FIRST =6744,
-  XED_IFORMFL_VPMOVSDW_LAST =6538, +  XED_IFORMFL_VPERMI2PS_LAST =6749,
-  XED_IFORMFL_VPMOVSQB_FIRST =6539, +  XED_IFORMFL_VPERMI2Q_FIRST =6750,
-  XED_IFORMFL_VPMOVSQB_LAST =6544, +  XED_IFORMFL_VPERMI2Q_LAST =6755,
-  XED_IFORMFL_VPMOVSQD_FIRST =6545, +  XED_IFORMFL_VPERMI2W_FIRST =6756,
-  XED_IFORMFL_VPMOVSQD_LAST =6550, +  XED_IFORMFL_VPERMI2W_LAST =6761,
-  XED_IFORMFL_VPMOVSQW_FIRST =6551, +  XED_IFORMFL_VPERMIL2PD_FIRST =6762,
-  XED_IFORMFL_VPMOVSQW_LAST =6556, +  XED_IFORMFL_VPERMIL2PD_LAST =6767,
-  XED_IFORMFL_VPMOVSWB_FIRST =6557, +  XED_IFORMFL_VPERMIL2PS_FIRST =6768,
-  XED_IFORMFL_VPMOVSWB_LAST =6562, +  XED_IFORMFL_VPERMIL2PS_LAST =6773,
-  XED_IFORMFL_VPMOVSXBD_FIRST =6563, +  XED_IFORMFL_VPERMILPD_FIRST =6774,
-  XED_IFORMFL_VPMOVSXBD_LAST =6572, +  XED_IFORMFL_VPERMILPD_LAST =6793,
-  XED_IFORMFL_VPMOVSXBQ_FIRST =6573, +  XED_IFORMFL_VPERMILPS_FIRST =6794,
-  XED_IFORMFL_VPMOVSXBQ_LAST =6582, +  XED_IFORMFL_VPERMILPS_LAST =6813,
-  XED_IFORMFL_VPMOVSXBW_FIRST =6583, +  XED_IFORMFL_VPERMPD_FIRST =6814,
-  XED_IFORMFL_VPMOVSXBW_LAST =6592, +  XED_IFORMFL_VPERMPD_LAST =6823,
-  XED_IFORMFL_VPMOVSXDQ_FIRST =6593, +  XED_IFORMFL_VPERMPS_FIRST =6824,
-  XED_IFORMFL_VPMOVSXDQ_LAST =6602, +  XED_IFORMFL_VPERMPS_LAST =6829,
-  XED_IFORMFL_VPMOVSXWD_FIRST =6603, +  XED_IFORMFL_VPERMQ_FIRST =6830,
-  XED_IFORMFL_VPMOVSXWD_LAST =6612, +  XED_IFORMFL_VPERMQ_LAST =6839,
-  XED_IFORMFL_VPMOVSXWQ_FIRST =6613, +  XED_IFORMFL_VPERMT2B_FIRST =6840,
-  XED_IFORMFL_VPMOVSXWQ_LAST =6622, +  XED_IFORMFL_VPERMT2B_LAST =6845,
-  XED_IFORMFL_VPMOVUSDB_FIRST =6623, +  XED_IFORMFL_VPERMT2D_FIRST =6846,
-  XED_IFORMFL_VPMOVUSDB_LAST =6628, +  XED_IFORMFL_VPERMT2D_LAST =6851,
-  XED_IFORMFL_VPMOVUSDW_FIRST =6629, +  XED_IFORMFL_VPERMT2PD_FIRST =6852,
-  XED_IFORMFL_VPMOVUSDW_LAST =6634, +  XED_IFORMFL_VPERMT2PD_LAST =6857,
-  XED_IFORMFL_VPMOVUSQB_FIRST =6635, +  XED_IFORMFL_VPERMT2PS_FIRST =6858,
-  XED_IFORMFL_VPMOVUSQB_LAST =6640, +  XED_IFORMFL_VPERMT2PS_LAST =6863,
-  XED_IFORMFL_VPMOVUSQD_FIRST =6641, +  XED_IFORMFL_VPERMT2Q_FIRST =6864,
-  XED_IFORMFL_VPMOVUSQD_LAST =6646, +  XED_IFORMFL_VPERMT2Q_LAST =6869,
-  XED_IFORMFL_VPMOVUSQW_FIRST =6647, +  XED_IFORMFL_VPERMT2W_FIRST =6870,
-  XED_IFORMFL_VPMOVUSQW_LAST =6652, +  XED_IFORMFL_VPERMT2W_LAST =6875,
-  XED_IFORMFL_VPMOVUSWB_FIRST =6653, +  XED_IFORMFL_VPERMW_FIRST =6876,
-  XED_IFORMFL_VPMOVUSWB_LAST =6658, +  XED_IFORMFL_VPERMW_LAST =6881,
-  XED_IFORMFL_VPMOVW2M_FIRST =6659, +  XED_IFORMFL_VPEXPANDB_FIRST =6882,
-  XED_IFORMFL_VPMOVW2M_LAST =6661, +  XED_IFORMFL_VPEXPANDB_LAST =6887,
-  XED_IFORMFL_VPMOVWB_FIRST =6662, +  XED_IFORMFL_VPEXPANDD_FIRST =6888,
-  XED_IFORMFL_VPMOVWB_LAST =6667, +  XED_IFORMFL_VPEXPANDD_LAST =6893,
-  XED_IFORMFL_VPMOVZXBD_FIRST =6668, +  XED_IFORMFL_VPEXPANDQ_FIRST =6894,
-  XED_IFORMFL_VPMOVZXBD_LAST =6677, +  XED_IFORMFL_VPEXPANDQ_LAST =6899,
-  XED_IFORMFL_VPMOVZXBQ_FIRST =6678, +  XED_IFORMFL_VPEXPANDW_FIRST =6900,
-  XED_IFORMFL_VPMOVZXBQ_LAST =6687, +  XED_IFORMFL_VPEXPANDW_LAST =6905,
-  XED_IFORMFL_VPMOVZXBW_FIRST =6688, +  XED_IFORMFL_VPEXTRB_FIRST =6906,
-  XED_IFORMFL_VPMOVZXBW_LAST =6697, +  XED_IFORMFL_VPEXTRB_LAST =6909,
-  XED_IFORMFL_VPMOVZXDQ_FIRST =6698, +  XED_IFORMFL_VPEXTRD_FIRST =6910,
-  XED_IFORMFL_VPMOVZXDQ_LAST =6707, +  XED_IFORMFL_VPEXTRD_LAST =6913,
-  XED_IFORMFL_VPMOVZXWD_FIRST =6708, +  XED_IFORMFL_VPEXTRQ_FIRST =6914,
-  XED_IFORMFL_VPMOVZXWD_LAST =6717, +  XED_IFORMFL_VPEXTRQ_LAST =6917,
-  XED_IFORMFL_VPMOVZXWQ_FIRST =6718, +  XED_IFORMFL_VPEXTRW_FIRST =6918,
-  XED_IFORMFL_VPMOVZXWQ_LAST =6727, +  XED_IFORMFL_VPEXTRW_LAST =6922,
-  XED_IFORMFL_VPMULDQ_FIRST =6728, +  XED_IFORMFL_VPEXTRW_C5_FIRST =6923,
-  XED_IFORMFL_VPMULDQ_LAST =6737, +  XED_IFORMFL_VPEXTRW_C5_LAST =6923,
-  XED_IFORMFL_VPMULHRSW_FIRST =6738, +  XED_IFORMFL_VPGATHERDD_FIRST =6924,
-  XED_IFORMFL_VPMULHRSW_LAST =6747, +  XED_IFORMFL_VPGATHERDD_LAST =6928,
-  XED_IFORMFL_VPMULHUW_FIRST =6748, +  XED_IFORMFL_VPGATHERDQ_FIRST =6929,
-  XED_IFORMFL_VPMULHUW_LAST =6757, +  XED_IFORMFL_VPGATHERDQ_LAST =6933,
-  XED_IFORMFL_VPMULHW_FIRST =6758, +  XED_IFORMFL_VPGATHERQD_FIRST =6934,
-  XED_IFORMFL_VPMULHW_LAST =6767, +  XED_IFORMFL_VPGATHERQD_LAST =6938,
-  XED_IFORMFL_VPMULLD_FIRST =6768, +  XED_IFORMFL_VPGATHERQQ_FIRST =6939,
-  XED_IFORMFL_VPMULLD_LAST =6777, +  XED_IFORMFL_VPGATHERQQ_LAST =6943,
-  XED_IFORMFL_VPMULLQ_FIRST =6778, +  XED_IFORMFL_VPHADDBD_FIRST =6944,
-  XED_IFORMFL_VPMULLQ_LAST =6783, +  XED_IFORMFL_VPHADDBD_LAST =6945,
-  XED_IFORMFL_VPMULLW_FIRST =6784, +  XED_IFORMFL_VPHADDBQ_FIRST =6946,
-  XED_IFORMFL_VPMULLW_LAST =6793, +  XED_IFORMFL_VPHADDBQ_LAST =6947,
-  XED_IFORMFL_VPMULTISHIFTQB_FIRST =6794, +  XED_IFORMFL_VPHADDBW_FIRST =6948,
-  XED_IFORMFL_VPMULTISHIFTQB_LAST =6799, +  XED_IFORMFL_VPHADDBW_LAST =6949,
-  XED_IFORMFL_VPMULUDQ_FIRST =6800, +  XED_IFORMFL_VPHADDD_FIRST =6950,
-  XED_IFORMFL_VPMULUDQ_LAST =6809, +  XED_IFORMFL_VPHADDD_LAST =6953,
-  XED_IFORMFL_VPOPCNTB_FIRST =6810, +  XED_IFORMFL_VPHADDDQ_FIRST =6954,
-  XED_IFORMFL_VPOPCNTB_LAST =6815, +  XED_IFORMFL_VPHADDDQ_LAST =6955,
-  XED_IFORMFL_VPOPCNTD_FIRST =6816, +  XED_IFORMFL_VPHADDSW_FIRST =6956,
-  XED_IFORMFL_VPOPCNTD_LAST =6821, +  XED_IFORMFL_VPHADDSW_LAST =6959,
-  XED_IFORMFL_VPOPCNTQ_FIRST =6822, +  XED_IFORMFL_VPHADDUBD_FIRST =6960,
-  XED_IFORMFL_VPOPCNTQ_LAST =6827, +  XED_IFORMFL_VPHADDUBD_LAST =6961,
-  XED_IFORMFL_VPOPCNTW_FIRST =6828, +  XED_IFORMFL_VPHADDUBQ_FIRST =6962,
-  XED_IFORMFL_VPOPCNTW_LAST =6833, +  XED_IFORMFL_VPHADDUBQ_LAST =6963,
-  XED_IFORMFL_VPOR_FIRST =6834, +  XED_IFORMFL_VPHADDUBW_FIRST =6964,
-  XED_IFORMFL_VPOR_LAST =6837, +  XED_IFORMFL_VPHADDUBW_LAST =6965,
-  XED_IFORMFL_VPORD_FIRST =6838, +  XED_IFORMFL_VPHADDUDQ_FIRST =6966,
-  XED_IFORMFL_VPORD_LAST =6843, +  XED_IFORMFL_VPHADDUDQ_LAST =6967,
-  XED_IFORMFL_VPORQ_FIRST =6844, +  XED_IFORMFL_VPHADDUWD_FIRST =6968,
-  XED_IFORMFL_VPORQ_LAST =6849, +  XED_IFORMFL_VPHADDUWD_LAST =6969,
-  XED_IFORMFL_VPPERM_FIRST =6850, +  XED_IFORMFL_VPHADDUWQ_FIRST =6970,
-  XED_IFORMFL_VPPERM_LAST =6852, +  XED_IFORMFL_VPHADDUWQ_LAST =6971,
-  XED_IFORMFL_VPROLD_FIRST =6853, +  XED_IFORMFL_VPHADDW_FIRST =6972,
-  XED_IFORMFL_VPROLD_LAST =6858, +  XED_IFORMFL_VPHADDW_LAST =6975,
-  XED_IFORMFL_VPROLQ_FIRST =6859, +  XED_IFORMFL_VPHADDWD_FIRST =6976,
-  XED_IFORMFL_VPROLQ_LAST =6864, +  XED_IFORMFL_VPHADDWD_LAST =6977,
-  XED_IFORMFL_VPROLVD_FIRST =6865, +  XED_IFORMFL_VPHADDWQ_FIRST =6978,
-  XED_IFORMFL_VPROLVD_LAST =6870, +  XED_IFORMFL_VPHADDWQ_LAST =6979,
-  XED_IFORMFL_VPROLVQ_FIRST =6871, +  XED_IFORMFL_VPHMINPOSUW_FIRST =6980,
-  XED_IFORMFL_VPROLVQ_LAST =6876, +  XED_IFORMFL_VPHMINPOSUW_LAST =6981,
-  XED_IFORMFL_VPRORD_FIRST =6877, +  XED_IFORMFL_VPHSUBBW_FIRST =6982,
-  XED_IFORMFL_VPRORD_LAST =6882, +  XED_IFORMFL_VPHSUBBW_LAST =6983,
-  XED_IFORMFL_VPRORQ_FIRST =6883, +  XED_IFORMFL_VPHSUBD_FIRST =6984,
-  XED_IFORMFL_VPRORQ_LAST =6888, +  XED_IFORMFL_VPHSUBD_LAST =6987,
-  XED_IFORMFL_VPRORVD_FIRST =6889, +  XED_IFORMFL_VPHSUBDQ_FIRST =6988,
-  XED_IFORMFL_VPRORVD_LAST =6894, +  XED_IFORMFL_VPHSUBDQ_LAST =6989,
-  XED_IFORMFL_VPRORVQ_FIRST =6895, +  XED_IFORMFL_VPHSUBSW_FIRST =6990,
-  XED_IFORMFL_VPRORVQ_LAST =6900, +  XED_IFORMFL_VPHSUBSW_LAST =6993,
-  XED_IFORMFL_VPROTB_FIRST =6901, +  XED_IFORMFL_VPHSUBW_FIRST =6994,
-  XED_IFORMFL_VPROTB_LAST =6905, +  XED_IFORMFL_VPHSUBW_LAST =6997,
-  XED_IFORMFL_VPROTD_FIRST =6906, +  XED_IFORMFL_VPHSUBWD_FIRST =6998,
-  XED_IFORMFL_VPROTD_LAST =6910, +  XED_IFORMFL_VPHSUBWD_LAST =6999,
-  XED_IFORMFL_VPROTQ_FIRST =6911, +  XED_IFORMFL_VPINSRB_FIRST =7000,
-  XED_IFORMFL_VPROTQ_LAST =6915, +  XED_IFORMFL_VPINSRB_LAST =7003,
-  XED_IFORMFL_VPROTW_FIRST =6916, +  XED_IFORMFL_VPINSRD_FIRST =7004,
-  XED_IFORMFL_VPROTW_LAST =6920, +  XED_IFORMFL_VPINSRD_LAST =7007,
-  XED_IFORMFL_VPSADBW_FIRST =6921, +  XED_IFORMFL_VPINSRQ_FIRST =7008,
-  XED_IFORMFL_VPSADBW_LAST =6930, +  XED_IFORMFL_VPINSRQ_LAST =7011,
-  XED_IFORMFL_VPSCATTERDD_FIRST =6931, +  XED_IFORMFL_VPINSRW_FIRST =7012,
-  XED_IFORMFL_VPSCATTERDD_LAST =6933, +  XED_IFORMFL_VPINSRW_LAST =7015,
-  XED_IFORMFL_VPSCATTERDQ_FIRST =6934, +  XED_IFORMFL_VPLZCNTD_FIRST =7016,
-  XED_IFORMFL_VPSCATTERDQ_LAST =6936, +  XED_IFORMFL_VPLZCNTD_LAST =7021,
-  XED_IFORMFL_VPSCATTERQD_FIRST =6937, +  XED_IFORMFL_VPLZCNTQ_FIRST =7022,
-  XED_IFORMFL_VPSCATTERQD_LAST =6939, +  XED_IFORMFL_VPLZCNTQ_LAST =7027,
-  XED_IFORMFL_VPSCATTERQQ_FIRST =6940, +  XED_IFORMFL_VPMACSDD_FIRST =7028,
-  XED_IFORMFL_VPSCATTERQQ_LAST =6942, +  XED_IFORMFL_VPMACSDD_LAST =7029,
-  XED_IFORMFL_VPSHAB_FIRST =6943, +  XED_IFORMFL_VPMACSDQH_FIRST =7030,
-  XED_IFORMFL_VPSHAB_LAST =6945, +  XED_IFORMFL_VPMACSDQH_LAST =7031,
-  XED_IFORMFL_VPSHAD_FIRST =6946, +  XED_IFORMFL_VPMACSDQL_FIRST =7032,
-  XED_IFORMFL_VPSHAD_LAST =6948, +  XED_IFORMFL_VPMACSDQL_LAST =7033,
-  XED_IFORMFL_VPSHAQ_FIRST =6949, +  XED_IFORMFL_VPMACSSDD_FIRST =7034,
-  XED_IFORMFL_VPSHAQ_LAST =6951, +  XED_IFORMFL_VPMACSSDD_LAST =7035,
-  XED_IFORMFL_VPSHAW_FIRST =6952, +  XED_IFORMFL_VPMACSSDQH_FIRST =7036,
-  XED_IFORMFL_VPSHAW_LAST =6954, +  XED_IFORMFL_VPMACSSDQH_LAST =7037,
-  XED_IFORMFL_VPSHLB_FIRST =6955, +  XED_IFORMFL_VPMACSSDQL_FIRST =7038,
-  XED_IFORMFL_VPSHLB_LAST =6957, +  XED_IFORMFL_VPMACSSDQL_LAST =7039,
-  XED_IFORMFL_VPSHLD_FIRST =6958, +  XED_IFORMFL_VPMACSSWD_FIRST =7040,
-  XED_IFORMFL_VPSHLD_LAST =6960, +  XED_IFORMFL_VPMACSSWD_LAST =7041,
-  XED_IFORMFL_VPSHLDD_FIRST =6961, +  XED_IFORMFL_VPMACSSWW_FIRST =7042,
-  XED_IFORMFL_VPSHLDD_LAST =6966, +  XED_IFORMFL_VPMACSSWW_LAST =7043,
-  XED_IFORMFL_VPSHLDQ_FIRST =6967, +  XED_IFORMFL_VPMACSWD_FIRST =7044,
-  XED_IFORMFL_VPSHLDQ_LAST =6972, +  XED_IFORMFL_VPMACSWD_LAST =7045,
-  XED_IFORMFL_VPSHLDVD_FIRST =6973, +  XED_IFORMFL_VPMACSWW_FIRST =7046,
-  XED_IFORMFL_VPSHLDVD_LAST =6978, +  XED_IFORMFL_VPMACSWW_LAST =7047,
-  XED_IFORMFL_VPSHLDVQ_FIRST =6979, +  XED_IFORMFL_VPMADCSSWD_FIRST =7048,
-  XED_IFORMFL_VPSHLDVQ_LAST =6984, +  XED_IFORMFL_VPMADCSSWD_LAST =7049,
-  XED_IFORMFL_VPSHLDVW_FIRST =6985, +  XED_IFORMFL_VPMADCSWD_FIRST =7050,
-  XED_IFORMFL_VPSHLDVW_LAST =6990, +  XED_IFORMFL_VPMADCSWD_LAST =7051,
-  XED_IFORMFL_VPSHLDW_FIRST =6991, +  XED_IFORMFL_VPMADD52HUQ_FIRST =7052,
-  XED_IFORMFL_VPSHLDW_LAST =6996, +  XED_IFORMFL_VPMADD52HUQ_LAST =7061,
-  XED_IFORMFL_VPSHLQ_FIRST =6997, +  XED_IFORMFL_VPMADD52LUQ_FIRST =7062,
-  XED_IFORMFL_VPSHLQ_LAST =6999, +  XED_IFORMFL_VPMADD52LUQ_LAST =7071,
-  XED_IFORMFL_VPSHLW_FIRST =7000, +  XED_IFORMFL_VPMADDUBSW_FIRST =7072,
-  XED_IFORMFL_VPSHLW_LAST =7002, +  XED_IFORMFL_VPMADDUBSW_LAST =7081,
-  XED_IFORMFL_VPSHRDD_FIRST =7003, +  XED_IFORMFL_VPMADDWD_FIRST =7082,
-  XED_IFORMFL_VPSHRDD_LAST =7008, +  XED_IFORMFL_VPMADDWD_LAST =7091,
-  XED_IFORMFL_VPSHRDQ_FIRST =7009, +  XED_IFORMFL_VPMASKMOVD_FIRST =7092,
-  XED_IFORMFL_VPSHRDQ_LAST =7014, +  XED_IFORMFL_VPMASKMOVD_LAST =7095,
-  XED_IFORMFL_VPSHRDVD_FIRST =7015, +  XED_IFORMFL_VPMASKMOVQ_FIRST =7096,
-  XED_IFORMFL_VPSHRDVD_LAST =7020, +  XED_IFORMFL_VPMASKMOVQ_LAST =7099,
-  XED_IFORMFL_VPSHRDVQ_FIRST =7021, +  XED_IFORMFL_VPMAXSB_FIRST =7100,
-  XED_IFORMFL_VPSHRDVQ_LAST =7026, +  XED_IFORMFL_VPMAXSB_LAST =7109,
-  XED_IFORMFL_VPSHRDVW_FIRST =7027, +  XED_IFORMFL_VPMAXSD_FIRST =7110,
-  XED_IFORMFL_VPSHRDVW_LAST =7032, +  XED_IFORMFL_VPMAXSD_LAST =7119,
-  XED_IFORMFL_VPSHRDW_FIRST =7033, +  XED_IFORMFL_VPMAXSQ_FIRST =7120,
-  XED_IFORMFL_VPSHRDW_LAST =7038, +  XED_IFORMFL_VPMAXSQ_LAST =7125,
-  XED_IFORMFL_VPSHUFB_FIRST =7039, +  XED_IFORMFL_VPMAXSW_FIRST =7126,
-  XED_IFORMFL_VPSHUFB_LAST =7048, +  XED_IFORMFL_VPMAXSW_LAST =7135,
-  XED_IFORMFL_VPSHUFBITQMB_FIRST =7049, +  XED_IFORMFL_VPMAXUB_FIRST =7136,
-  XED_IFORMFL_VPSHUFBITQMB_LAST =7054, +  XED_IFORMFL_VPMAXUB_LAST =7145,
-  XED_IFORMFL_VPSHUFD_FIRST =7055, +  XED_IFORMFL_VPMAXUD_FIRST =7146,
-  XED_IFORMFL_VPSHUFD_LAST =7064, +  XED_IFORMFL_VPMAXUD_LAST =7155,
-  XED_IFORMFL_VPSHUFHW_FIRST =7065, +  XED_IFORMFL_VPMAXUQ_FIRST =7156,
-  XED_IFORMFL_VPSHUFHW_LAST =7074, +  XED_IFORMFL_VPMAXUQ_LAST =7161,
-  XED_IFORMFL_VPSHUFLW_FIRST =7075, +  XED_IFORMFL_VPMAXUW_FIRST =7162,
-  XED_IFORMFL_VPSHUFLW_LAST =7084, +  XED_IFORMFL_VPMAXUW_LAST =7171,
-  XED_IFORMFL_VPSIGNB_FIRST =7085, +  XED_IFORMFL_VPMINSB_FIRST =7172,
-  XED_IFORMFL_VPSIGNB_LAST =7088, +  XED_IFORMFL_VPMINSB_LAST =7181,
-  XED_IFORMFL_VPSIGND_FIRST =7089, +  XED_IFORMFL_VPMINSD_FIRST =7182,
-  XED_IFORMFL_VPSIGND_LAST =7092, +  XED_IFORMFL_VPMINSD_LAST =7191,
-  XED_IFORMFL_VPSIGNW_FIRST =7093, +  XED_IFORMFL_VPMINSQ_FIRST =7192,
-  XED_IFORMFL_VPSIGNW_LAST =7096, +  XED_IFORMFL_VPMINSQ_LAST =7197,
-  XED_IFORMFL_VPSLLD_FIRST =7097, +  XED_IFORMFL_VPMINSW_FIRST =7198,
-  XED_IFORMFL_VPSLLD_LAST =7114, +  XED_IFORMFL_VPMINSW_LAST =7207,
-  XED_IFORMFL_VPSLLDQ_FIRST =7115, +  XED_IFORMFL_VPMINUB_FIRST =7208,
-  XED_IFORMFL_VPSLLDQ_LAST =7122, +  XED_IFORMFL_VPMINUB_LAST =7217,
-  XED_IFORMFL_VPSLLQ_FIRST =7123, +  XED_IFORMFL_VPMINUD_FIRST =7218,
-  XED_IFORMFL_VPSLLQ_LAST =7140, +  XED_IFORMFL_VPMINUD_LAST =7227,
-  XED_IFORMFL_VPSLLVD_FIRST =7141, +  XED_IFORMFL_VPMINUQ_FIRST =7228,
-  XED_IFORMFL_VPSLLVD_LAST =7150, +  XED_IFORMFL_VPMINUQ_LAST =7233,
-  XED_IFORMFL_VPSLLVQ_FIRST =7151, +  XED_IFORMFL_VPMINUW_FIRST =7234,
-  XED_IFORMFL_VPSLLVQ_LAST =7160, +  XED_IFORMFL_VPMINUW_LAST =7243,
-  XED_IFORMFL_VPSLLVW_FIRST =7161, +  XED_IFORMFL_VPMOVB2M_FIRST =7244,
-  XED_IFORMFL_VPSLLVW_LAST =7166, +  XED_IFORMFL_VPMOVB2M_LAST =7246,
-  XED_IFORMFL_VPSLLW_FIRST =7167, +  XED_IFORMFL_VPMOVD2M_FIRST =7247,
-  XED_IFORMFL_VPSLLW_LAST =7184, +  XED_IFORMFL_VPMOVD2M_LAST =7249,
-  XED_IFORMFL_VPSRAD_FIRST =7185, +  XED_IFORMFL_VPMOVDB_FIRST =7250,
-  XED_IFORMFL_VPSRAD_LAST =7202, +  XED_IFORMFL_VPMOVDB_LAST =7255,
-  XED_IFORMFL_VPSRAQ_FIRST =7203, +  XED_IFORMFL_VPMOVDW_FIRST =7256,
-  XED_IFORMFL_VPSRAQ_LAST =7214, +  XED_IFORMFL_VPMOVDW_LAST =7261,
-  XED_IFORMFL_VPSRAVD_FIRST =7215, +  XED_IFORMFL_VPMOVM2B_FIRST =7262,
-  XED_IFORMFL_VPSRAVD_LAST =7224, +  XED_IFORMFL_VPMOVM2B_LAST =7264,
-  XED_IFORMFL_VPSRAVQ_FIRST =7225, +  XED_IFORMFL_VPMOVM2D_FIRST =7265,
-  XED_IFORMFL_VPSRAVQ_LAST =7230, +  XED_IFORMFL_VPMOVM2D_LAST =7267,
-  XED_IFORMFL_VPSRAVW_FIRST =7231, +  XED_IFORMFL_VPMOVM2Q_FIRST =7268,
-  XED_IFORMFL_VPSRAVW_LAST =7236, +  XED_IFORMFL_VPMOVM2Q_LAST =7270,
-  XED_IFORMFL_VPSRAW_FIRST =7237, +  XED_IFORMFL_VPMOVM2W_FIRST =7271,
-  XED_IFORMFL_VPSRAW_LAST =7254, +  XED_IFORMFL_VPMOVM2W_LAST =7273,
-  XED_IFORMFL_VPSRLD_FIRST =7255, +  XED_IFORMFL_VPMOVMSKB_FIRST =7274,
-  XED_IFORMFL_VPSRLD_LAST =7272, +  XED_IFORMFL_VPMOVMSKB_LAST =7275,
-  XED_IFORMFL_VPSRLDQ_FIRST =7273, +  XED_IFORMFL_VPMOVQ2M_FIRST =7276,
-  XED_IFORMFL_VPSRLDQ_LAST =7280, +  XED_IFORMFL_VPMOVQ2M_LAST =7278,
-  XED_IFORMFL_VPSRLQ_FIRST =7281, +  XED_IFORMFL_VPMOVQB_FIRST =7279,
-  XED_IFORMFL_VPSRLQ_LAST =7298, +  XED_IFORMFL_VPMOVQB_LAST =7284,
-  XED_IFORMFL_VPSRLVD_FIRST =7299, +  XED_IFORMFL_VPMOVQD_FIRST =7285,
-  XED_IFORMFL_VPSRLVD_LAST =7308, +  XED_IFORMFL_VPMOVQD_LAST =7290,
-  XED_IFORMFL_VPSRLVQ_FIRST =7309, +  XED_IFORMFL_VPMOVQW_FIRST =7291,
-  XED_IFORMFL_VPSRLVQ_LAST =7318, +  XED_IFORMFL_VPMOVQW_LAST =7296,
-  XED_IFORMFL_VPSRLVW_FIRST =7319, +  XED_IFORMFL_VPMOVSDB_FIRST =7297,
-  XED_IFORMFL_VPSRLVW_LAST =7324, +  XED_IFORMFL_VPMOVSDB_LAST =7302,
-  XED_IFORMFL_VPSRLW_FIRST =7325, +  XED_IFORMFL_VPMOVSDW_FIRST =7303,
-  XED_IFORMFL_VPSRLW_LAST =7342, +  XED_IFORMFL_VPMOVSDW_LAST =7308,
-  XED_IFORMFL_VPSUBB_FIRST =7343, +  XED_IFORMFL_VPMOVSQB_FIRST =7309,
-  XED_IFORMFL_VPSUBB_LAST =7352, +  XED_IFORMFL_VPMOVSQB_LAST =7314,
-  XED_IFORMFL_VPSUBD_FIRST =7353, +  XED_IFORMFL_VPMOVSQD_FIRST =7315,
-  XED_IFORMFL_VPSUBD_LAST =7362, +  XED_IFORMFL_VPMOVSQD_LAST =7320,
-  XED_IFORMFL_VPSUBQ_FIRST =7363, +  XED_IFORMFL_VPMOVSQW_FIRST =7321,
-  XED_IFORMFL_VPSUBQ_LAST =7372, +  XED_IFORMFL_VPMOVSQW_LAST =7326,
-  XED_IFORMFL_VPSUBSB_FIRST =7373, +  XED_IFORMFL_VPMOVSWB_FIRST =7327,
-  XED_IFORMFL_VPSUBSB_LAST =7382, +  XED_IFORMFL_VPMOVSWB_LAST =7332,
-  XED_IFORMFL_VPSUBSW_FIRST =7383, +  XED_IFORMFL_VPMOVSXBD_FIRST =7333,
-  XED_IFORMFL_VPSUBSW_LAST =7392, +  XED_IFORMFL_VPMOVSXBD_LAST =7342,
-  XED_IFORMFL_VPSUBUSB_FIRST =7393, +  XED_IFORMFL_VPMOVSXBQ_FIRST =7343,
-  XED_IFORMFL_VPSUBUSB_LAST =7402, +  XED_IFORMFL_VPMOVSXBQ_LAST =7352,
-  XED_IFORMFL_VPSUBUSW_FIRST =7403, +  XED_IFORMFL_VPMOVSXBW_FIRST =7353,
-  XED_IFORMFL_VPSUBUSW_LAST =7412, +  XED_IFORMFL_VPMOVSXBW_LAST =7362,
-  XED_IFORMFL_VPSUBW_FIRST =7413, +  XED_IFORMFL_VPMOVSXDQ_FIRST =7363,
-  XED_IFORMFL_VPSUBW_LAST =7422, +  XED_IFORMFL_VPMOVSXDQ_LAST =7372,
-  XED_IFORMFL_VPTERNLOGD_FIRST =7423, +  XED_IFORMFL_VPMOVSXWD_FIRST =7373,
-  XED_IFORMFL_VPTERNLOGD_LAST =7428, +  XED_IFORMFL_VPMOVSXWD_LAST =7382,
-  XED_IFORMFL_VPTERNLOGQ_FIRST =7429, +  XED_IFORMFL_VPMOVSXWQ_FIRST =7383,
-  XED_IFORMFL_VPTERNLOGQ_LAST =7434, +  XED_IFORMFL_VPMOVSXWQ_LAST =7392,
-  XED_IFORMFL_VPTEST_FIRST =7435, +  XED_IFORMFL_VPMOVUSDB_FIRST =7393,
-  XED_IFORMFL_VPTEST_LAST =7438, +  XED_IFORMFL_VPMOVUSDB_LAST =7398,
-  XED_IFORMFL_VPTESTMB_FIRST =7439, +  XED_IFORMFL_VPMOVUSDW_FIRST =7399,
-  XED_IFORMFL_VPTESTMB_LAST =7444, +  XED_IFORMFL_VPMOVUSDW_LAST =7404,
-  XED_IFORMFL_VPTESTMD_FIRST =7445, +  XED_IFORMFL_VPMOVUSQB_FIRST =7405,
-  XED_IFORMFL_VPTESTMD_LAST =7450, +  XED_IFORMFL_VPMOVUSQB_LAST =7410,
-  XED_IFORMFL_VPTESTMQ_FIRST =7451, +  XED_IFORMFL_VPMOVUSQD_FIRST =7411,
-  XED_IFORMFL_VPTESTMQ_LAST =7456, +  XED_IFORMFL_VPMOVUSQD_LAST =7416,
-  XED_IFORMFL_VPTESTMW_FIRST =7457, +  XED_IFORMFL_VPMOVUSQW_FIRST =7417,
-  XED_IFORMFL_VPTESTMW_LAST =7462, +  XED_IFORMFL_VPMOVUSQW_LAST =7422,
-  XED_IFORMFL_VPTESTNMB_FIRST =7463, +  XED_IFORMFL_VPMOVUSWB_FIRST =7423,
-  XED_IFORMFL_VPTESTNMB_LAST =7468, +  XED_IFORMFL_VPMOVUSWB_LAST =7428,
-  XED_IFORMFL_VPTESTNMD_FIRST =7469, +  XED_IFORMFL_VPMOVW2M_FIRST =7429,
-  XED_IFORMFL_VPTESTNMD_LAST =7474, +  XED_IFORMFL_VPMOVW2M_LAST =7431,
-  XED_IFORMFL_VPTESTNMQ_FIRST =7475, +  XED_IFORMFL_VPMOVWB_FIRST =7432,
-  XED_IFORMFL_VPTESTNMQ_LAST =7480, +  XED_IFORMFL_VPMOVWB_LAST =7437,
-  XED_IFORMFL_VPTESTNMW_FIRST =7481, +  XED_IFORMFL_VPMOVZXBD_FIRST =7438,
-  XED_IFORMFL_VPTESTNMW_LAST =7486, +  XED_IFORMFL_VPMOVZXBD_LAST =7447,
-  XED_IFORMFL_VPUNPCKHBW_FIRST =7487, +  XED_IFORMFL_VPMOVZXBQ_FIRST =7448,
-  XED_IFORMFL_VPUNPCKHBW_LAST =7496, +  XED_IFORMFL_VPMOVZXBQ_LAST =7457,
-  XED_IFORMFL_VPUNPCKHDQ_FIRST =7497, +  XED_IFORMFL_VPMOVZXBW_FIRST =7458,
-  XED_IFORMFL_VPUNPCKHDQ_LAST =7506, +  XED_IFORMFL_VPMOVZXBW_LAST =7467,
-  XED_IFORMFL_VPUNPCKHQDQ_FIRST =7507, +  XED_IFORMFL_VPMOVZXDQ_FIRST =7468,
-  XED_IFORMFL_VPUNPCKHQDQ_LAST =7516, +  XED_IFORMFL_VPMOVZXDQ_LAST =7477,
-  XED_IFORMFL_VPUNPCKHWD_FIRST =7517, +  XED_IFORMFL_VPMOVZXWD_FIRST =7478,
-  XED_IFORMFL_VPUNPCKHWD_LAST =7526, +  XED_IFORMFL_VPMOVZXWD_LAST =7487,
-  XED_IFORMFL_VPUNPCKLBW_FIRST =7527, +  XED_IFORMFL_VPMOVZXWQ_FIRST =7488,
-  XED_IFORMFL_VPUNPCKLBW_LAST =7536, +  XED_IFORMFL_VPMOVZXWQ_LAST =7497,
-  XED_IFORMFL_VPUNPCKLDQ_FIRST =7537, +  XED_IFORMFL_VPMULDQ_FIRST =7498,
-  XED_IFORMFL_VPUNPCKLDQ_LAST =7546, +  XED_IFORMFL_VPMULDQ_LAST =7507,
-  XED_IFORMFL_VPUNPCKLQDQ_FIRST =7547, +  XED_IFORMFL_VPMULHRSW_FIRST =7508,
-  XED_IFORMFL_VPUNPCKLQDQ_LAST =7556, +  XED_IFORMFL_VPMULHRSW_LAST =7517,
-  XED_IFORMFL_VPUNPCKLWD_FIRST =7557, +  XED_IFORMFL_VPMULHUW_FIRST =7518,
-  XED_IFORMFL_VPUNPCKLWD_LAST =7566, +  XED_IFORMFL_VPMULHUW_LAST =7527,
-  XED_IFORMFL_VPXOR_FIRST =7567, +  XED_IFORMFL_VPMULHW_FIRST =7528,
-  XED_IFORMFL_VPXOR_LAST =7570, +  XED_IFORMFL_VPMULHW_LAST =7537,
-  XED_IFORMFL_VPXORD_FIRST =7571, +  XED_IFORMFL_VPMULLD_FIRST =7538,
-  XED_IFORMFL_VPXORD_LAST =7576, +  XED_IFORMFL_VPMULLD_LAST =7547,
-  XED_IFORMFL_VPXORQ_FIRST =7577, +  XED_IFORMFL_VPMULLQ_FIRST =7548,
-  XED_IFORMFL_VPXORQ_LAST =7582, +  XED_IFORMFL_VPMULLQ_LAST =7553,
-  XED_IFORMFL_VRANGEPD_FIRST =7583, +  XED_IFORMFL_VPMULLW_FIRST =7554,
-  XED_IFORMFL_VRANGEPD_LAST =7588, +  XED_IFORMFL_VPMULLW_LAST =7563,
-  XED_IFORMFL_VRANGEPS_FIRST =7589, +  XED_IFORMFL_VPMULTISHIFTQB_FIRST =7564,
-  XED_IFORMFL_VRANGEPS_LAST =7594, +  XED_IFORMFL_VPMULTISHIFTQB_LAST =7569,
-  XED_IFORMFL_VRANGESD_FIRST =7595, +  XED_IFORMFL_VPMULUDQ_FIRST =7570,
-  XED_IFORMFL_VRANGESD_LAST =7596, +  XED_IFORMFL_VPMULUDQ_LAST =7579,
-  XED_IFORMFL_VRANGESS_FIRST =7597, +  XED_IFORMFL_VPOPCNTB_FIRST =7580,
-  XED_IFORMFL_VRANGESS_LAST =7598, +  XED_IFORMFL_VPOPCNTB_LAST =7585,
-  XED_IFORMFL_VRCP14PD_FIRST =7599, +  XED_IFORMFL_VPOPCNTD_FIRST =7586,
-  XED_IFORMFL_VRCP14PD_LAST =7604, +  XED_IFORMFL_VPOPCNTD_LAST =7591,
-  XED_IFORMFL_VRCP14PS_FIRST =7605, +  XED_IFORMFL_VPOPCNTQ_FIRST =7592,
-  XED_IFORMFL_VRCP14PS_LAST =7610, +  XED_IFORMFL_VPOPCNTQ_LAST =7597,
-  XED_IFORMFL_VRCP14SD_FIRST =7611, +  XED_IFORMFL_VPOPCNTW_FIRST =7598,
-  XED_IFORMFL_VRCP14SD_LAST =7612, +  XED_IFORMFL_VPOPCNTW_LAST =7603,
-  XED_IFORMFL_VRCP14SS_FIRST =7613, +  XED_IFORMFL_VPOR_FIRST =7604,
-  XED_IFORMFL_VRCP14SS_LAST =7614, +  XED_IFORMFL_VPOR_LAST =7607,
-  XED_IFORMFL_VRCP28PD_FIRST =7615, +  XED_IFORMFL_VPORD_FIRST =7608,
-  XED_IFORMFL_VRCP28PD_LAST =7616, +  XED_IFORMFL_VPORD_LAST =7613,
-  XED_IFORMFL_VRCP28PS_FIRST =7617, +  XED_IFORMFL_VPORQ_FIRST =7614,
-  XED_IFORMFL_VRCP28PS_LAST =7618, +  XED_IFORMFL_VPORQ_LAST =7619,
-  XED_IFORMFL_VRCP28SD_FIRST =7619, +  XED_IFORMFL_VPPERM_FIRST =7620,
-  XED_IFORMFL_VRCP28SD_LAST =7620, +  XED_IFORMFL_VPPERM_LAST =7622,
-  XED_IFORMFL_VRCP28SS_FIRST =7621, +  XED_IFORMFL_VPROLD_FIRST =7623,
-  XED_IFORMFL_VRCP28SS_LAST =7622, +  XED_IFORMFL_VPROLD_LAST =7628,
-  XED_IFORMFL_VRCPPH_FIRST =7623, +  XED_IFORMFL_VPROLQ_FIRST =7629,
-  XED_IFORMFL_VRCPPH_LAST =7628, +  XED_IFORMFL_VPROLQ_LAST =7634,
-  XED_IFORMFL_VRCPPS_FIRST =7629, +  XED_IFORMFL_VPROLVD_FIRST =7635,
-  XED_IFORMFL_VRCPPS_LAST =7632, +  XED_IFORMFL_VPROLVD_LAST =7640,
-  XED_IFORMFL_VRCPSH_FIRST =7633, +  XED_IFORMFL_VPROLVQ_FIRST =7641,
-  XED_IFORMFL_VRCPSH_LAST =7634, +  XED_IFORMFL_VPROLVQ_LAST =7646,
-  XED_IFORMFL_VRCPSS_FIRST =7635, +  XED_IFORMFL_VPRORD_FIRST =7647,
-  XED_IFORMFL_VRCPSS_LAST =7636, +  XED_IFORMFL_VPRORD_LAST =7652,
-  XED_IFORMFL_VREDUCEPD_FIRST =7637, +  XED_IFORMFL_VPRORQ_FIRST =7653,
-  XED_IFORMFL_VREDUCEPD_LAST =7642, +  XED_IFORMFL_VPRORQ_LAST =7658,
-  XED_IFORMFL_VREDUCEPH_FIRST =7643, +  XED_IFORMFL_VPRORVD_FIRST =7659,
-  XED_IFORMFL_VREDUCEPH_LAST =7648, +  XED_IFORMFL_VPRORVD_LAST =7664,
-  XED_IFORMFL_VREDUCEPS_FIRST =7649, +  XED_IFORMFL_VPRORVQ_FIRST =7665,
-  XED_IFORMFL_VREDUCEPS_LAST =7654, +  XED_IFORMFL_VPRORVQ_LAST =7670,
-  XED_IFORMFL_VREDUCESD_FIRST =7655, +  XED_IFORMFL_VPROTB_FIRST =7671,
-  XED_IFORMFL_VREDUCESD_LAST =7656, +  XED_IFORMFL_VPROTB_LAST =7675,
-  XED_IFORMFL_VREDUCESH_FIRST =7657, +  XED_IFORMFL_VPROTD_FIRST =7676,
-  XED_IFORMFL_VREDUCESH_LAST =7658, +  XED_IFORMFL_VPROTD_LAST =7680,
-  XED_IFORMFL_VREDUCESS_FIRST =7659, +  XED_IFORMFL_VPROTQ_FIRST =7681,
-  XED_IFORMFL_VREDUCESS_LAST =7660, +  XED_IFORMFL_VPROTQ_LAST =7685,
-  XED_IFORMFL_VRNDSCALEPD_FIRST =7661, +  XED_IFORMFL_VPROTW_FIRST =7686,
-  XED_IFORMFL_VRNDSCALEPD_LAST =7666, +  XED_IFORMFL_VPROTW_LAST =7690,
-  XED_IFORMFL_VRNDSCALEPH_FIRST =7667, +  XED_IFORMFL_VPSADBW_FIRST =7691,
-  XED_IFORMFL_VRNDSCALEPH_LAST =7672, +  XED_IFORMFL_VPSADBW_LAST =7700,
-  XED_IFORMFL_VRNDSCALEPS_FIRST =7673, +  XED_IFORMFL_VPSCATTERDD_FIRST =7701,
-  XED_IFORMFL_VRNDSCALEPS_LAST =7678, +  XED_IFORMFL_VPSCATTERDD_LAST =7703,
-  XED_IFORMFL_VRNDSCALESD_FIRST =7679, +  XED_IFORMFL_VPSCATTERDQ_FIRST =7704,
-  XED_IFORMFL_VRNDSCALESD_LAST =7680, +  XED_IFORMFL_VPSCATTERDQ_LAST =7706,
-  XED_IFORMFL_VRNDSCALESH_FIRST =7681, +  XED_IFORMFL_VPSCATTERQD_FIRST =7707,
-  XED_IFORMFL_VRNDSCALESH_LAST =7682, +  XED_IFORMFL_VPSCATTERQD_LAST =7709,
-  XED_IFORMFL_VRNDSCALESS_FIRST =7683, +  XED_IFORMFL_VPSCATTERQQ_FIRST =7710,
-  XED_IFORMFL_VRNDSCALESS_LAST =7684, +  XED_IFORMFL_VPSCATTERQQ_LAST =7712,
-  XED_IFORMFL_VROUNDPD_FIRST =7685, +  XED_IFORMFL_VPSHAB_FIRST =7713,
-  XED_IFORMFL_VROUNDPD_LAST =7688, +  XED_IFORMFL_VPSHAB_LAST =7715,
-  XED_IFORMFL_VROUNDPS_FIRST =7689, +  XED_IFORMFL_VPSHAD_FIRST =7716,
-  XED_IFORMFL_VROUNDPS_LAST =7692, +  XED_IFORMFL_VPSHAD_LAST =7718,
-  XED_IFORMFL_VROUNDSD_FIRST =7693, +  XED_IFORMFL_VPSHAQ_FIRST =7719,
-  XED_IFORMFL_VROUNDSD_LAST =7694, +  XED_IFORMFL_VPSHAQ_LAST =7721,
-  XED_IFORMFL_VROUNDSS_FIRST =7695, +  XED_IFORMFL_VPSHAW_FIRST =7722,
-  XED_IFORMFL_VROUNDSS_LAST =7696, +  XED_IFORMFL_VPSHAW_LAST =7724,
-  XED_IFORMFL_VRSQRT14PD_FIRST =7697, +  XED_IFORMFL_VPSHLB_FIRST =7725,
-  XED_IFORMFL_VRSQRT14PD_LAST =7702, +  XED_IFORMFL_VPSHLB_LAST =7727,
-  XED_IFORMFL_VRSQRT14PS_FIRST =7703, +  XED_IFORMFL_VPSHLD_FIRST =7728,
-  XED_IFORMFL_VRSQRT14PS_LAST =7708, +  XED_IFORMFL_VPSHLD_LAST =7730,
-  XED_IFORMFL_VRSQRT14SD_FIRST =7709, +  XED_IFORMFL_VPSHLDD_FIRST =7731,
-  XED_IFORMFL_VRSQRT14SD_LAST =7710, +  XED_IFORMFL_VPSHLDD_LAST =7736,
-  XED_IFORMFL_VRSQRT14SS_FIRST =7711, +  XED_IFORMFL_VPSHLDQ_FIRST =7737,
-  XED_IFORMFL_VRSQRT14SS_LAST =7712, +  XED_IFORMFL_VPSHLDQ_LAST =7742,
-  XED_IFORMFL_VRSQRT28PD_FIRST =7713, +  XED_IFORMFL_VPSHLDVD_FIRST =7743,
-  XED_IFORMFL_VRSQRT28PD_LAST =7714, +  XED_IFORMFL_VPSHLDVD_LAST =7748,
-  XED_IFORMFL_VRSQRT28PS_FIRST =7715, +  XED_IFORMFL_VPSHLDVQ_FIRST =7749,
-  XED_IFORMFL_VRSQRT28PS_LAST =7716, +  XED_IFORMFL_VPSHLDVQ_LAST =7754,
-  XED_IFORMFL_VRSQRT28SD_FIRST =7717, +  XED_IFORMFL_VPSHLDVW_FIRST =7755,
-  XED_IFORMFL_VRSQRT28SD_LAST =7718, +  XED_IFORMFL_VPSHLDVW_LAST =7760,
-  XED_IFORMFL_VRSQRT28SS_FIRST =7719, +  XED_IFORMFL_VPSHLDW_FIRST =7761,
-  XED_IFORMFL_VRSQRT28SS_LAST =7720, +  XED_IFORMFL_VPSHLDW_LAST =7766,
-  XED_IFORMFL_VRSQRTPH_FIRST =7721, +  XED_IFORMFL_VPSHLQ_FIRST =7767,
-  XED_IFORMFL_VRSQRTPH_LAST =7726, +  XED_IFORMFL_VPSHLQ_LAST =7769,
-  XED_IFORMFL_VRSQRTPS_FIRST =7727, +  XED_IFORMFL_VPSHLW_FIRST =7770,
-  XED_IFORMFL_VRSQRTPS_LAST =7730, +  XED_IFORMFL_VPSHLW_LAST =7772,
-  XED_IFORMFL_VRSQRTSH_FIRST =7731, +  XED_IFORMFL_VPSHRDD_FIRST =7773,
-  XED_IFORMFL_VRSQRTSH_LAST =7732, +  XED_IFORMFL_VPSHRDD_LAST =7778,
-  XED_IFORMFL_VRSQRTSS_FIRST =7733, +  XED_IFORMFL_VPSHRDQ_FIRST =7779,
-  XED_IFORMFL_VRSQRTSS_LAST =7734, +  XED_IFORMFL_VPSHRDQ_LAST =7784,
-  XED_IFORMFL_VSCALEFPD_FIRST =7735, +  XED_IFORMFL_VPSHRDVD_FIRST =7785,
-  XED_IFORMFL_VSCALEFPD_LAST =7740, +  XED_IFORMFL_VPSHRDVD_LAST =7790,
-  XED_IFORMFL_VSCALEFPH_FIRST =7741, +  XED_IFORMFL_VPSHRDVQ_FIRST =7791,
-  XED_IFORMFL_VSCALEFPH_LAST =7746, +  XED_IFORMFL_VPSHRDVQ_LAST =7796,
-  XED_IFORMFL_VSCALEFPS_FIRST =7747, +  XED_IFORMFL_VPSHRDVW_FIRST =7797,
-  XED_IFORMFL_VSCALEFPS_LAST =7752, +  XED_IFORMFL_VPSHRDVW_LAST =7802,
-  XED_IFORMFL_VSCALEFSD_FIRST =7753, +  XED_IFORMFL_VPSHRDW_FIRST =7803,
-  XED_IFORMFL_VSCALEFSD_LAST =7754, +  XED_IFORMFL_VPSHRDW_LAST =7808,
-  XED_IFORMFL_VSCALEFSH_FIRST =7755, +  XED_IFORMFL_VPSHUFB_FIRST =7809,
-  XED_IFORMFL_VSCALEFSH_LAST =7756, +  XED_IFORMFL_VPSHUFB_LAST =7818,
-  XED_IFORMFL_VSCALEFSS_FIRST =7757, +  XED_IFORMFL_VPSHUFBITQMB_FIRST =7819,
-  XED_IFORMFL_VSCALEFSS_LAST =7758, +  XED_IFORMFL_VPSHUFBITQMB_LAST =7824,
-  XED_IFORMFL_VSCATTERDPD_FIRST =7759, +  XED_IFORMFL_VPSHUFD_FIRST =7825,
-  XED_IFORMFL_VSCATTERDPD_LAST =7761, +  XED_IFORMFL_VPSHUFD_LAST =7834,
-  XED_IFORMFL_VSCATTERDPS_FIRST =7762, +  XED_IFORMFL_VPSHUFHW_FIRST =7835,
-  XED_IFORMFL_VSCATTERDPS_LAST =7764, +  XED_IFORMFL_VPSHUFHW_LAST =7844,
-  XED_IFORMFL_VSCATTERPF0DPD_FIRST =7765, +  XED_IFORMFL_VPSHUFLW_FIRST =7845,
-  XED_IFORMFL_VSCATTERPF0DPD_LAST =7765, +  XED_IFORMFL_VPSHUFLW_LAST =7854,
-  XED_IFORMFL_VSCATTERPF0DPS_FIRST =7766, +  XED_IFORMFL_VPSIGNB_FIRST =7855,
-  XED_IFORMFL_VSCATTERPF0DPS_LAST =7766, +  XED_IFORMFL_VPSIGNB_LAST =7858,
-  XED_IFORMFL_VSCATTERPF0QPD_FIRST =7767, +  XED_IFORMFL_VPSIGND_FIRST =7859,
-  XED_IFORMFL_VSCATTERPF0QPD_LAST =7767, +  XED_IFORMFL_VPSIGND_LAST =7862,
-  XED_IFORMFL_VSCATTERPF0QPS_FIRST =7768, +  XED_IFORMFL_VPSIGNW_FIRST =7863,
-  XED_IFORMFL_VSCATTERPF0QPS_LAST =7768, +  XED_IFORMFL_VPSIGNW_LAST =7866,
-  XED_IFORMFL_VSCATTERPF1DPD_FIRST =7769, +  XED_IFORMFL_VPSLLD_FIRST =7867,
-  XED_IFORMFL_VSCATTERPF1DPD_LAST =7769, +  XED_IFORMFL_VPSLLD_LAST =7884,
-  XED_IFORMFL_VSCATTERPF1DPS_FIRST =7770, +  XED_IFORMFL_VPSLLDQ_FIRST =7885,
-  XED_IFORMFL_VSCATTERPF1DPS_LAST =7770, +  XED_IFORMFL_VPSLLDQ_LAST =7892,
-  XED_IFORMFL_VSCATTERPF1QPD_FIRST =7771, +  XED_IFORMFL_VPSLLQ_FIRST =7893,
-  XED_IFORMFL_VSCATTERPF1QPD_LAST =7771, +  XED_IFORMFL_VPSLLQ_LAST =7910,
-  XED_IFORMFL_VSCATTERPF1QPS_FIRST =7772, +  XED_IFORMFL_VPSLLVD_FIRST =7911,
-  XED_IFORMFL_VSCATTERPF1QPS_LAST =7772, +  XED_IFORMFL_VPSLLVD_LAST =7920,
-  XED_IFORMFL_VSCATTERQPD_FIRST =7773, +  XED_IFORMFL_VPSLLVQ_FIRST =7921,
-  XED_IFORMFL_VSCATTERQPD_LAST =7775, +  XED_IFORMFL_VPSLLVQ_LAST =7930,
-  XED_IFORMFL_VSCATTERQPS_FIRST =7776, +  XED_IFORMFL_VPSLLVW_FIRST =7931,
-  XED_IFORMFL_VSCATTERQPS_LAST =7778, +  XED_IFORMFL_VPSLLVW_LAST =7936,
-  XED_IFORMFL_VSHA512MSG1_FIRST =7779, +  XED_IFORMFL_VPSLLW_FIRST =7937,
-  XED_IFORMFL_VSHA512MSG1_LAST =7779, +  XED_IFORMFL_VPSLLW_LAST =7954,
-  XED_IFORMFL_VSHA512MSG2_FIRST =7780, +  XED_IFORMFL_VPSRAD_FIRST =7955,
-  XED_IFORMFL_VSHA512MSG2_LAST =7780, +  XED_IFORMFL_VPSRAD_LAST =7972,
-  XED_IFORMFL_VSHA512RNDS2_FIRST =7781, +  XED_IFORMFL_VPSRAQ_FIRST =7973,
-  XED_IFORMFL_VSHA512RNDS2_LAST =7781, +  XED_IFORMFL_VPSRAQ_LAST =7984,
-  XED_IFORMFL_VSHUFF32X4_FIRST =7782, +  XED_IFORMFL_VPSRAVD_FIRST =7985,
-  XED_IFORMFL_VSHUFF32X4_LAST =7785, +  XED_IFORMFL_VPSRAVD_LAST =7994,
-  XED_IFORMFL_VSHUFF64X2_FIRST =7786, +  XED_IFORMFL_VPSRAVQ_FIRST =7995,
-  XED_IFORMFL_VSHUFF64X2_LAST =7789, +  XED_IFORMFL_VPSRAVQ_LAST =8000,
-  XED_IFORMFL_VSHUFI32X4_FIRST =7790, +  XED_IFORMFL_VPSRAVW_FIRST =8001,
-  XED_IFORMFL_VSHUFI32X4_LAST =7793, +  XED_IFORMFL_VPSRAVW_LAST =8006,
-  XED_IFORMFL_VSHUFI64X2_FIRST =7794, +  XED_IFORMFL_VPSRAW_FIRST =8007,
-  XED_IFORMFL_VSHUFI64X2_LAST =7797, +  XED_IFORMFL_VPSRAW_LAST =8024,
-  XED_IFORMFL_VSHUFPD_FIRST =7798, +  XED_IFORMFL_VPSRLD_FIRST =8025,
-  XED_IFORMFL_VSHUFPD_LAST =7807, +  XED_IFORMFL_VPSRLD_LAST =8042,
-  XED_IFORMFL_VSHUFPS_FIRST =7808, +  XED_IFORMFL_VPSRLDQ_FIRST =8043,
-  XED_IFORMFL_VSHUFPS_LAST =7817, +  XED_IFORMFL_VPSRLDQ_LAST =8050,
-  XED_IFORMFL_VSM3MSG1_FIRST =7818, +  XED_IFORMFL_VPSRLQ_FIRST =8051,
-  XED_IFORMFL_VSM3MSG1_LAST =7819, +  XED_IFORMFL_VPSRLQ_LAST =8068,
-  XED_IFORMFL_VSM3MSG2_FIRST =7820, +  XED_IFORMFL_VPSRLVD_FIRST =8069,
-  XED_IFORMFL_VSM3MSG2_LAST =7821, +  XED_IFORMFL_VPSRLVD_LAST =8078,
-  XED_IFORMFL_VSM3RNDS2_FIRST =7822, +  XED_IFORMFL_VPSRLVQ_FIRST =8079,
-  XED_IFORMFL_VSM3RNDS2_LAST =7823, +  XED_IFORMFL_VPSRLVQ_LAST =8088,
-  XED_IFORMFL_VSM4KEY4_FIRST =7824, +  XED_IFORMFL_VPSRLVW_FIRST =8089,
-  XED_IFORMFL_VSM4KEY4_LAST =7827, +  XED_IFORMFL_VPSRLVW_LAST =8094,
-  XED_IFORMFL_VSM4RNDS4_FIRST =7828, +  XED_IFORMFL_VPSRLW_FIRST =8095,
-  XED_IFORMFL_VSM4RNDS4_LAST =7831, +  XED_IFORMFL_VPSRLW_LAST =8112,
-  XED_IFORMFL_VSQRTPD_FIRST =7832, +  XED_IFORMFL_VPSUBB_FIRST =8113,
-  XED_IFORMFL_VSQRTPD_LAST =7841, +  XED_IFORMFL_VPSUBB_LAST =8122,
-  XED_IFORMFL_VSQRTPH_FIRST =7842, +  XED_IFORMFL_VPSUBD_FIRST =8123,
-  XED_IFORMFL_VSQRTPH_LAST =7847, +  XED_IFORMFL_VPSUBD_LAST =8132,
-  XED_IFORMFL_VSQRTPS_FIRST =7848, +  XED_IFORMFL_VPSUBQ_FIRST =8133,
-  XED_IFORMFL_VSQRTPS_LAST =7857, +  XED_IFORMFL_VPSUBQ_LAST =8142,
-  XED_IFORMFL_VSQRTSD_FIRST =7858, +  XED_IFORMFL_VPSUBSB_FIRST =8143,
-  XED_IFORMFL_VSQRTSD_LAST =7861, +  XED_IFORMFL_VPSUBSB_LAST =8152,
-  XED_IFORMFL_VSQRTSH_FIRST =7862, +  XED_IFORMFL_VPSUBSW_FIRST =8153,
-  XED_IFORMFL_VSQRTSH_LAST =7863, +  XED_IFORMFL_VPSUBSW_LAST =8162,
-  XED_IFORMFL_VSQRTSS_FIRST =7864, +  XED_IFORMFL_VPSUBUSB_FIRST =8163,
-  XED_IFORMFL_VSQRTSS_LAST =7867, +  XED_IFORMFL_VPSUBUSB_LAST =8172,
-  XED_IFORMFL_VSTMXCSR_FIRST =7868, +  XED_IFORMFL_VPSUBUSW_FIRST =8173,
-  XED_IFORMFL_VSTMXCSR_LAST =7868, +  XED_IFORMFL_VPSUBUSW_LAST =8182,
-  XED_IFORMFL_VSUBPD_FIRST =7869, +  XED_IFORMFL_VPSUBW_FIRST =8183,
-  XED_IFORMFL_VSUBPD_LAST =7878, +  XED_IFORMFL_VPSUBW_LAST =8192,
-  XED_IFORMFL_VSUBPH_FIRST =7879, +  XED_IFORMFL_VPTERNLOGD_FIRST =8193,
-  XED_IFORMFL_VSUBPH_LAST =7884, +  XED_IFORMFL_VPTERNLOGD_LAST =8198,
-  XED_IFORMFL_VSUBPS_FIRST =7885, +  XED_IFORMFL_VPTERNLOGQ_FIRST =8199,
-  XED_IFORMFL_VSUBPS_LAST =7894, +  XED_IFORMFL_VPTERNLOGQ_LAST =8204,
-  XED_IFORMFL_VSUBSD_FIRST =7895, +  XED_IFORMFL_VPTEST_FIRST =8205,
-  XED_IFORMFL_VSUBSD_LAST =7898, +  XED_IFORMFL_VPTEST_LAST =8208,
-  XED_IFORMFL_VSUBSH_FIRST =7899, +  XED_IFORMFL_VPTESTMB_FIRST =8209,
-  XED_IFORMFL_VSUBSH_LAST =7900, +  XED_IFORMFL_VPTESTMB_LAST =8214,
-  XED_IFORMFL_VSUBSS_FIRST =7901, +  XED_IFORMFL_VPTESTMD_FIRST =8215,
-  XED_IFORMFL_VSUBSS_LAST =7904, +  XED_IFORMFL_VPTESTMD_LAST =8220,
-  XED_IFORMFL_VTESTPD_FIRST =7905, +  XED_IFORMFL_VPTESTMQ_FIRST =8221,
-  XED_IFORMFL_VTESTPD_LAST =7908, +  XED_IFORMFL_VPTESTMQ_LAST =8226,
-  XED_IFORMFL_VTESTPS_FIRST =7909, +  XED_IFORMFL_VPTESTMW_FIRST =8227,
-  XED_IFORMFL_VTESTPS_LAST =7912, +  XED_IFORMFL_VPTESTMW_LAST =8232,
-  XED_IFORMFL_VUCOMISD_FIRST =7913, +  XED_IFORMFL_VPTESTNMB_FIRST =8233,
-  XED_IFORMFL_VUCOMISD_LAST =7916, +  XED_IFORMFL_VPTESTNMB_LAST =8238,
-  XED_IFORMFL_VUCOMISH_FIRST =7917, +  XED_IFORMFL_VPTESTNMD_FIRST =8239,
-  XED_IFORMFL_VUCOMISH_LAST =7918, +  XED_IFORMFL_VPTESTNMD_LAST =8244,
-  XED_IFORMFL_VUCOMISS_FIRST =7919, +  XED_IFORMFL_VPTESTNMQ_FIRST =8245,
-  XED_IFORMFL_VUCOMISS_LAST =7922, +  XED_IFORMFL_VPTESTNMQ_LAST =8250,
-  XED_IFORMFL_VUNPCKHPD_FIRST =7923, +  XED_IFORMFL_VPTESTNMW_FIRST =8251,
-  XED_IFORMFL_VUNPCKHPD_LAST =7932, +  XED_IFORMFL_VPTESTNMW_LAST =8256,
-  XED_IFORMFL_VUNPCKHPS_FIRST =7933, +  XED_IFORMFL_VPUNPCKHBW_FIRST =8257,
-  XED_IFORMFL_VUNPCKHPS_LAST =7942, +  XED_IFORMFL_VPUNPCKHBW_LAST =8266,
-  XED_IFORMFL_VUNPCKLPD_FIRST =7943, +  XED_IFORMFL_VPUNPCKHDQ_FIRST =8267,
-  XED_IFORMFL_VUNPCKLPD_LAST =7952, +  XED_IFORMFL_VPUNPCKHDQ_LAST =8276,
-  XED_IFORMFL_VUNPCKLPS_FIRST =7953, +  XED_IFORMFL_VPUNPCKHQDQ_FIRST =8277,
-  XED_IFORMFL_VUNPCKLPS_LAST =7962, +  XED_IFORMFL_VPUNPCKHQDQ_LAST =8286,
-  XED_IFORMFL_VXORPD_FIRST =7963, +  XED_IFORMFL_VPUNPCKHWD_FIRST =8287,
-  XED_IFORMFL_VXORPD_LAST =7972, +  XED_IFORMFL_VPUNPCKHWD_LAST =8296,
-  XED_IFORMFL_VXORPS_FIRST =7973, +  XED_IFORMFL_VPUNPCKLBW_FIRST =8297,
-  XED_IFORMFL_VXORPS_LAST =7982, +  XED_IFORMFL_VPUNPCKLBW_LAST =8306,
-  XED_IFORMFL_VZEROALL_FIRST =7983, +  XED_IFORMFL_VPUNPCKLDQ_FIRST =8307,
-  XED_IFORMFL_VZEROALL_LAST =7983, +  XED_IFORMFL_VPUNPCKLDQ_LAST =8316,
-  XED_IFORMFL_VZEROUPPER_FIRST =7984, +  XED_IFORMFL_VPUNPCKLQDQ_FIRST =8317,
-  XED_IFORMFL_VZEROUPPER_LAST =7984, +  XED_IFORMFL_VPUNPCKLQDQ_LAST =8326,
-  XED_IFORMFL_WBINVD_FIRST =7985, +  XED_IFORMFL_VPUNPCKLWD_FIRST =8327,
-  XED_IFORMFL_WBINVD_LAST =7985, +  XED_IFORMFL_VPUNPCKLWD_LAST =8336,
-  XED_IFORMFL_WBNOINVD_FIRST =7986, +  XED_IFORMFL_VPXOR_FIRST =8337,
-  XED_IFORMFL_WBNOINVD_LAST =7986, +  XED_IFORMFL_VPXOR_LAST =8340,
-  XED_IFORMFL_WRFSBASE_FIRST =7987, +  XED_IFORMFL_VPXORD_FIRST =8341,
-  XED_IFORMFL_WRFSBASE_LAST =7987, +  XED_IFORMFL_VPXORD_LAST =8346,
-  XED_IFORMFL_WRGSBASE_FIRST =7988, +  XED_IFORMFL_VPXORQ_FIRST =8347,
-  XED_IFORMFL_WRGSBASE_LAST =7988, +  XED_IFORMFL_VPXORQ_LAST =8352,
-  XED_IFORMFL_WRMSR_FIRST =7989, +  XED_IFORMFL_VRANGEPD_FIRST =8353,
-  XED_IFORMFL_WRMSR_LAST =7989, +  XED_IFORMFL_VRANGEPD_LAST =8359,
-  XED_IFORMFL_WRMSRLIST_FIRST =7990, +  XED_IFORMFL_VRANGEPS_FIRST =8360,
-  XED_IFORMFL_WRMSRLIST_LAST =7990, +  XED_IFORMFL_VRANGEPS_LAST =8366,
-  XED_IFORMFL_WRMSRNS_FIRST =7991, +  XED_IFORMFL_VRANGESD_FIRST =8367,
-  XED_IFORMFL_WRMSRNS_LAST =7991, +  XED_IFORMFL_VRANGESD_LAST =8369,
-  XED_IFORMFL_WRPKRU_FIRST =7992, +  XED_IFORMFL_VRANGESS_FIRST =8370,
-  XED_IFORMFL_WRPKRU_LAST =7992, +  XED_IFORMFL_VRANGESS_LAST =8372,
-  XED_IFORMFL_WRSSD_FIRST =7993, +  XED_IFORMFL_VRCP14PD_FIRST =8373,
-  XED_IFORMFL_WRSSD_LAST =7994, +  XED_IFORMFL_VRCP14PD_LAST =8378,
-  XED_IFORMFL_WRSSQ_FIRST =7995, +  XED_IFORMFL_VRCP14PS_FIRST =8379,
-  XED_IFORMFL_WRSSQ_LAST =7996, +  XED_IFORMFL_VRCP14PS_LAST =8384,
-  XED_IFORMFL_WRUSSD_FIRST =7997, +  XED_IFORMFL_VRCP14SD_FIRST =8385,
-  XED_IFORMFL_WRUSSD_LAST =7998, +  XED_IFORMFL_VRCP14SD_LAST =8386,
-  XED_IFORMFL_WRUSSQ_FIRST =7999, +  XED_IFORMFL_VRCP14SS_FIRST =8387,
-  XED_IFORMFL_WRUSSQ_LAST =8000, +  XED_IFORMFL_VRCP14SS_LAST =8388,
-  XED_IFORMFL_XABORT_FIRST =8001, +  XED_IFORMFL_VRCP28PD_FIRST =8389,
-  XED_IFORMFL_XABORT_LAST =8001, +  XED_IFORMFL_VRCP28PD_LAST =8390,
-  XED_IFORMFL_XADD_FIRST =8002, +  XED_IFORMFL_VRCP28PS_FIRST =8391,
-  XED_IFORMFL_XADD_LAST =8005, +  XED_IFORMFL_VRCP28PS_LAST =8392,
-  XED_IFORMFL_XADD_LOCK_FIRST =8006, +  XED_IFORMFL_VRCP28SD_FIRST =8393,
-  XED_IFORMFL_XADD_LOCK_LAST =8007, +  XED_IFORMFL_VRCP28SD_LAST =8394,
-  XED_IFORMFL_XBEGIN_FIRST =8008, +  XED_IFORMFL_VRCP28SS_FIRST =8395,
-  XED_IFORMFL_XBEGIN_LAST =8008, +  XED_IFORMFL_VRCP28SS_LAST =8396,
-  XED_IFORMFL_XCHG_FIRST =8009, +  XED_IFORMFL_VRCPPBF16_FIRST =8397,
-  XED_IFORMFL_XCHG_LAST =8013, +  XED_IFORMFL_VRCPPBF16_LAST =8402,
-  XED_IFORMFL_XEND_FIRST =8014, +  XED_IFORMFL_VRCPPH_FIRST =8403,
-  XED_IFORMFL_XEND_LAST =8014, +  XED_IFORMFL_VRCPPH_LAST =8408,
-  XED_IFORMFL_XGETBV_FIRST =8015, +  XED_IFORMFL_VRCPPS_FIRST =8409,
-  XED_IFORMFL_XGETBV_LAST =8015, +  XED_IFORMFL_VRCPPS_LAST =8412,
-  XED_IFORMFL_XLAT_FIRST =8016, +  XED_IFORMFL_VRCPSH_FIRST =8413,
-  XED_IFORMFL_XLAT_LAST =8016, +  XED_IFORMFL_VRCPSH_LAST =8414,
-  XED_IFORMFL_XOR_FIRST =8017, +  XED_IFORMFL_VRCPSS_FIRST =8415,
-  XED_IFORMFL_XOR_LAST =8058, +  XED_IFORMFL_VRCPSS_LAST =8416,
-  XED_IFORMFL_XORPD_FIRST =8059, +  XED_IFORMFL_VREDUCENEPBF16_FIRST =8417,
-  XED_IFORMFL_XORPD_LAST =8060, +  XED_IFORMFL_VREDUCENEPBF16_LAST =8422,
-  XED_IFORMFL_XORPS_FIRST =8061, +  XED_IFORMFL_VREDUCEPD_FIRST =8423,
-  XED_IFORMFL_XORPS_LAST =8062, +  XED_IFORMFL_VREDUCEPD_LAST =8429,
-  XED_IFORMFL_XOR_LOCK_FIRST =8063, +  XED_IFORMFL_VREDUCEPH_FIRST =8430,
-  XED_IFORMFL_XOR_LOCK_LAST =8068, +  XED_IFORMFL_VREDUCEPH_LAST =8436,
-  XED_IFORMFL_XRESLDTRK_FIRST =8069, +  XED_IFORMFL_VREDUCEPS_FIRST =8437,
-  XED_IFORMFL_XRESLDTRK_LAST =8069, +  XED_IFORMFL_VREDUCEPS_LAST =8443,
-  XED_IFORMFL_XRSTOR_FIRST =8070, +  XED_IFORMFL_VREDUCESD_FIRST =8444,
-  XED_IFORMFL_XRSTOR_LAST =8070, +  XED_IFORMFL_VREDUCESD_LAST =8446,
-  XED_IFORMFL_XRSTOR64_FIRST =8071, +  XED_IFORMFL_VREDUCESH_FIRST =8447,
-  XED_IFORMFL_XRSTOR64_LAST =8071, +  XED_IFORMFL_VREDUCESH_LAST =8449,
-  XED_IFORMFL_XRSTORS_FIRST =8072, +  XED_IFORMFL_VREDUCESS_FIRST =8450,
-  XED_IFORMFL_XRSTORS_LAST =8072, +  XED_IFORMFL_VREDUCESS_LAST =8452,
-  XED_IFORMFL_XRSTORS64_FIRST =8073, +  XED_IFORMFL_VRNDSCALENEPBF16_FIRST =8453,
-  XED_IFORMFL_XRSTORS64_LAST =8073, +  XED_IFORMFL_VRNDSCALENEPBF16_LAST =8458,
-  XED_IFORMFL_XSAVE_FIRST =8074, +  XED_IFORMFL_VRNDSCALEPD_FIRST =8459,
-  XED_IFORMFL_XSAVE_LAST =8074, +  XED_IFORMFL_VRNDSCALEPD_LAST =8465,
-  XED_IFORMFL_XSAVE64_FIRST =8075, +  XED_IFORMFL_VRNDSCALEPH_FIRST =8466,
-  XED_IFORMFL_XSAVE64_LAST =8075, +  XED_IFORMFL_VRNDSCALEPH_LAST =8472,
-  XED_IFORMFL_XSAVEC_FIRST =8076, +  XED_IFORMFL_VRNDSCALEPS_FIRST =8473,
-  XED_IFORMFL_XSAVEC_LAST =8076, +  XED_IFORMFL_VRNDSCALEPS_LAST =8479,
-  XED_IFORMFL_XSAVEC64_FIRST =8077, +  XED_IFORMFL_VRNDSCALESD_FIRST =8480,
-  XED_IFORMFL_XSAVEC64_LAST =8077, +  XED_IFORMFL_VRNDSCALESD_LAST =8482,
-  XED_IFORMFL_XSAVEOPT_FIRST =8078, +  XED_IFORMFL_VRNDSCALESH_FIRST =8483,
-  XED_IFORMFL_XSAVEOPT_LAST =8078, +  XED_IFORMFL_VRNDSCALESH_LAST =8485,
-  XED_IFORMFL_XSAVEOPT64_FIRST =8079, +  XED_IFORMFL_VRNDSCALESS_FIRST =8486,
-  XED_IFORMFL_XSAVEOPT64_LAST =8079, +  XED_IFORMFL_VRNDSCALESS_LAST =8488,
-  XED_IFORMFL_XSAVES_FIRST =8080, +  XED_IFORMFL_VROUNDPD_FIRST =8489,
-  XED_IFORMFL_XSAVES_LAST =8080, +  XED_IFORMFL_VROUNDPD_LAST =8492,
-  XED_IFORMFL_XSAVES64_FIRST =8081, +  XED_IFORMFL_VROUNDPS_FIRST =8493,
-  XED_IFORMFL_XSAVES64_LAST =8081, +  XED_IFORMFL_VROUNDPS_LAST =8496,
-  XED_IFORMFL_XSETBV_FIRST =8082, +  XED_IFORMFL_VROUNDSD_FIRST =8497,
-  XED_IFORMFL_XSETBV_LAST =8082, +  XED_IFORMFL_VROUNDSD_LAST =8498,
-  XED_IFORMFL_XSTORE_FIRST =8083, +  XED_IFORMFL_VROUNDSS_FIRST =8499,
-  XED_IFORMFL_XSTORE_LAST =8083, +  XED_IFORMFL_VROUNDSS_LAST =8500,
-  XED_IFORMFL_XSUSLDTRK_FIRST =8084, +  XED_IFORMFL_VRSQRT14PD_FIRST =8501,
-  XED_IFORMFL_XSUSLDTRK_LAST =8084, +  XED_IFORMFL_VRSQRT14PD_LAST =8506,
-  XED_IFORMFL_XTEST_FIRST =8085, +  XED_IFORMFL_VRSQRT14PS_FIRST =8507,
-  XED_IFORMFL_XTEST_LAST =8085, +  XED_IFORMFL_VRSQRT14PS_LAST =8512, +
+  XED_IFORMFL_VRSQRT14SD_FIRST =8513, +
+  XED_IFORMFL_VRSQRT14SD_LAST =8514, +
+  XED_IFORMFL_VRSQRT14SS_FIRST =8515, +
+  XED_IFORMFL_VRSQRT14SS_LAST =8516, +
+  XED_IFORMFL_VRSQRT28PD_FIRST =8517, +
+  XED_IFORMFL_VRSQRT28PD_LAST =8518, +
+  XED_IFORMFL_VRSQRT28PS_FIRST =8519, +
+  XED_IFORMFL_VRSQRT28PS_LAST =8520, +
+  XED_IFORMFL_VRSQRT28SD_FIRST =8521, +
+  XED_IFORMFL_VRSQRT28SD_LAST =8522, +
+  XED_IFORMFL_VRSQRT28SS_FIRST =8523, +
+  XED_IFORMFL_VRSQRT28SS_LAST =8524, +
+  XED_IFORMFL_VRSQRTPBF16_FIRST =8525, +
+  XED_IFORMFL_VRSQRTPBF16_LAST =8530, +
+  XED_IFORMFL_VRSQRTPH_FIRST =8531, +
+  XED_IFORMFL_VRSQRTPH_LAST =8536, +
+  XED_IFORMFL_VRSQRTPS_FIRST =8537, +
+  XED_IFORMFL_VRSQRTPS_LAST =8540, +
+  XED_IFORMFL_VRSQRTSH_FIRST =8541, +
+  XED_IFORMFL_VRSQRTSH_LAST =8542, +
+  XED_IFORMFL_VRSQRTSS_FIRST =8543, +
+  XED_IFORMFL_VRSQRTSS_LAST =8544, +
+  XED_IFORMFL_VSCALEFPBF16_FIRST =8545, +
+  XED_IFORMFL_VSCALEFPBF16_LAST =8550, +
+  XED_IFORMFL_VSCALEFPD_FIRST =8551, +
+  XED_IFORMFL_VSCALEFPD_LAST =8557, +
+  XED_IFORMFL_VSCALEFPH_FIRST =8558, +
+  XED_IFORMFL_VSCALEFPH_LAST =8564, +
+  XED_IFORMFL_VSCALEFPS_FIRST =8565, +
+  XED_IFORMFL_VSCALEFPS_LAST =8571, +
+  XED_IFORMFL_VSCALEFSD_FIRST =8572, +
+  XED_IFORMFL_VSCALEFSD_LAST =8574, +
+  XED_IFORMFL_VSCALEFSH_FIRST =8575, +
+  XED_IFORMFL_VSCALEFSH_LAST =8577, +
+  XED_IFORMFL_VSCALEFSS_FIRST =8578, +
+  XED_IFORMFL_VSCALEFSS_LAST =8580, +
+  XED_IFORMFL_VSCATTERDPD_FIRST =8581, +
+  XED_IFORMFL_VSCATTERDPD_LAST =8583, +
+  XED_IFORMFL_VSCATTERDPS_FIRST =8584, +
+  XED_IFORMFL_VSCATTERDPS_LAST =8586, +
+  XED_IFORMFL_VSCATTERPF0DPD_FIRST =8587, +
+  XED_IFORMFL_VSCATTERPF0DPD_LAST =8587, +
+  XED_IFORMFL_VSCATTERPF0DPS_FIRST =8588, +
+  XED_IFORMFL_VSCATTERPF0DPS_LAST =8588, +
+  XED_IFORMFL_VSCATTERPF0QPD_FIRST =8589, +
+  XED_IFORMFL_VSCATTERPF0QPD_LAST =8589, +
+  XED_IFORMFL_VSCATTERPF0QPS_FIRST =8590, +
+  XED_IFORMFL_VSCATTERPF0QPS_LAST =8590, +
+  XED_IFORMFL_VSCATTERPF1DPD_FIRST =8591, +
+  XED_IFORMFL_VSCATTERPF1DPD_LAST =8591, +
+  XED_IFORMFL_VSCATTERPF1DPS_FIRST =8592, +
+  XED_IFORMFL_VSCATTERPF1DPS_LAST =8592, +
+  XED_IFORMFL_VSCATTERPF1QPD_FIRST =8593, +
+  XED_IFORMFL_VSCATTERPF1QPD_LAST =8593, +
+  XED_IFORMFL_VSCATTERPF1QPS_FIRST =8594, +
+  XED_IFORMFL_VSCATTERPF1QPS_LAST =8594, +
+  XED_IFORMFL_VSCATTERQPD_FIRST =8595, +
+  XED_IFORMFL_VSCATTERQPD_LAST =8597, +
+  XED_IFORMFL_VSCATTERQPS_FIRST =8598, +
+  XED_IFORMFL_VSCATTERQPS_LAST =8600, +
+  XED_IFORMFL_VSHA512MSG1_FIRST =8601, +
+  XED_IFORMFL_VSHA512MSG1_LAST =8601, +
+  XED_IFORMFL_VSHA512MSG2_FIRST =8602, +
+  XED_IFORMFL_VSHA512MSG2_LAST =8602, +
+  XED_IFORMFL_VSHA512RNDS2_FIRST =8603, +
+  XED_IFORMFL_VSHA512RNDS2_LAST =8603, +
+  XED_IFORMFL_VSHUFF32X4_FIRST =8604, +
+  XED_IFORMFL_VSHUFF32X4_LAST =8607, +
+  XED_IFORMFL_VSHUFF64X2_FIRST =8608, +
+  XED_IFORMFL_VSHUFF64X2_LAST =8611, +
+  XED_IFORMFL_VSHUFI32X4_FIRST =8612, +
+  XED_IFORMFL_VSHUFI32X4_LAST =8615, +
+  XED_IFORMFL_VSHUFI64X2_FIRST =8616, +
+  XED_IFORMFL_VSHUFI64X2_LAST =8619, +
+  XED_IFORMFL_VSHUFPD_FIRST =8620, +
+  XED_IFORMFL_VSHUFPD_LAST =8629, +
+  XED_IFORMFL_VSHUFPS_FIRST =8630, +
+  XED_IFORMFL_VSHUFPS_LAST =8639, +
+  XED_IFORMFL_VSM3MSG1_FIRST =8640, +
+  XED_IFORMFL_VSM3MSG1_LAST =8641, +
+  XED_IFORMFL_VSM3MSG2_FIRST =8642, +
+  XED_IFORMFL_VSM3MSG2_LAST =8643, +
+  XED_IFORMFL_VSM3RNDS2_FIRST =8644, +
+  XED_IFORMFL_VSM3RNDS2_LAST =8645, +
+  XED_IFORMFL_VSM4KEY4_FIRST =8646, +
+  XED_IFORMFL_VSM4KEY4_LAST =8655, +
+  XED_IFORMFL_VSM4RNDS4_FIRST =8656, +
+  XED_IFORMFL_VSM4RNDS4_LAST =8665, +
+  XED_IFORMFL_VSQRTNEPBF16_FIRST =8666, +
+  XED_IFORMFL_VSQRTNEPBF16_LAST =8671, +
+  XED_IFORMFL_VSQRTPD_FIRST =8672, +
+  XED_IFORMFL_VSQRTPD_LAST =8682, +
+  XED_IFORMFL_VSQRTPH_FIRST =8683, +
+  XED_IFORMFL_VSQRTPH_LAST =8689, +
+  XED_IFORMFL_VSQRTPS_FIRST =8690, +
+  XED_IFORMFL_VSQRTPS_LAST =8700, +
+  XED_IFORMFL_VSQRTSD_FIRST =8701, +
+  XED_IFORMFL_VSQRTSD_LAST =8705, +
+  XED_IFORMFL_VSQRTSH_FIRST =8706, +
+  XED_IFORMFL_VSQRTSH_LAST =8708, +
+  XED_IFORMFL_VSQRTSS_FIRST =8709, +
+  XED_IFORMFL_VSQRTSS_LAST =8713, +
+  XED_IFORMFL_VSTMXCSR_FIRST =8714, +
+  XED_IFORMFL_VSTMXCSR_LAST =8714, +
+  XED_IFORMFL_VSUBNEPBF16_FIRST =8715, +
+  XED_IFORMFL_VSUBNEPBF16_LAST =8720, +
+  XED_IFORMFL_VSUBPD_FIRST =8721, +
+  XED_IFORMFL_VSUBPD_LAST =8731, +
+  XED_IFORMFL_VSUBPH_FIRST =8732, +
+  XED_IFORMFL_VSUBPH_LAST =8738, +
+  XED_IFORMFL_VSUBPS_FIRST =8739, +
+  XED_IFORMFL_VSUBPS_LAST =8749, +
+  XED_IFORMFL_VSUBSD_FIRST =8750, +
+  XED_IFORMFL_VSUBSD_LAST =8754, +
+  XED_IFORMFL_VSUBSH_FIRST =8755, +
+  XED_IFORMFL_VSUBSH_LAST =8757, +
+  XED_IFORMFL_VSUBSS_FIRST =8758, +
+  XED_IFORMFL_VSUBSS_LAST =8762, +
+  XED_IFORMFL_VTESTPD_FIRST =8763, +
+  XED_IFORMFL_VTESTPD_LAST =8766, +
+  XED_IFORMFL_VTESTPS_FIRST =8767, +
+  XED_IFORMFL_VTESTPS_LAST =8770, +
+  XED_IFORMFL_VUCOMISD_FIRST =8771, +
+  XED_IFORMFL_VUCOMISD_LAST =8775, +
+  XED_IFORMFL_VUCOMISH_FIRST =8776, +
+  XED_IFORMFL_VUCOMISH_LAST =8778, +
+  XED_IFORMFL_VUCOMISS_FIRST =8779, +
+  XED_IFORMFL_VUCOMISS_LAST =8783, +
+  XED_IFORMFL_VUCOMXSD_FIRST =8784, +
+  XED_IFORMFL_VUCOMXSD_LAST =8785, +
+  XED_IFORMFL_VUCOMXSH_FIRST =8786, +
+  XED_IFORMFL_VUCOMXSH_LAST =8787, +
+  XED_IFORMFL_VUCOMXSS_FIRST =8788, +
+  XED_IFORMFL_VUCOMXSS_LAST =8789, +
+  XED_IFORMFL_VUNPCKHPD_FIRST =8790, +
+  XED_IFORMFL_VUNPCKHPD_LAST =8799, +
+  XED_IFORMFL_VUNPCKHPS_FIRST =8800, +
+  XED_IFORMFL_VUNPCKHPS_LAST =8809, +
+  XED_IFORMFL_VUNPCKLPD_FIRST =8810, +
+  XED_IFORMFL_VUNPCKLPD_LAST =8819, +
+  XED_IFORMFL_VUNPCKLPS_FIRST =8820, +
+  XED_IFORMFL_VUNPCKLPS_LAST =8829, +
+  XED_IFORMFL_VXORPD_FIRST =8830, +
+  XED_IFORMFL_VXORPD_LAST =8839, +
+  XED_IFORMFL_VXORPS_FIRST =8840, +
+  XED_IFORMFL_VXORPS_LAST =8849, +
+  XED_IFORMFL_VZEROALL_FIRST =8850, +
+  XED_IFORMFL_VZEROALL_LAST =8850, +
+  XED_IFORMFL_VZEROUPPER_FIRST =8851, +
+  XED_IFORMFL_VZEROUPPER_LAST =8851, +
+  XED_IFORMFL_WBINVD_FIRST =8852, +
+  XED_IFORMFL_WBINVD_LAST =8852, +
+  XED_IFORMFL_WBNOINVD_FIRST =8853, +
+  XED_IFORMFL_WBNOINVD_LAST =8853, +
+  XED_IFORMFL_WRFSBASE_FIRST =8854, +
+  XED_IFORMFL_WRFSBASE_LAST =8854, +
+  XED_IFORMFL_WRGSBASE_FIRST =8855, +
+  XED_IFORMFL_WRGSBASE_LAST =8855, +
+  XED_IFORMFL_WRMSR_FIRST =8856, +
+  XED_IFORMFL_WRMSR_LAST =8856, +
+  XED_IFORMFL_WRMSRLIST_FIRST =8857, +
+  XED_IFORMFL_WRMSRLIST_LAST =8857, +
+  XED_IFORMFL_WRMSRNS_FIRST =8858, +
+  XED_IFORMFL_WRMSRNS_LAST =8860, +
+  XED_IFORMFL_WRPKRU_FIRST =8861, +
+  XED_IFORMFL_WRPKRU_LAST =8861, +
+  XED_IFORMFL_WRSSD_FIRST =8862, +
+  XED_IFORMFL_WRSSD_LAST =8863, +
+  XED_IFORMFL_WRSSQ_FIRST =8864, +
+  XED_IFORMFL_WRSSQ_LAST =8865, +
+  XED_IFORMFL_WRUSSD_FIRST =8866, +
+  XED_IFORMFL_WRUSSD_LAST =8867, +
+  XED_IFORMFL_WRUSSQ_FIRST =8868, +
+  XED_IFORMFL_WRUSSQ_LAST =8869, +
+  XED_IFORMFL_XABORT_FIRST =8870, +
+  XED_IFORMFL_XABORT_LAST =8870, +
+  XED_IFORMFL_XADD_FIRST =8871, +
+  XED_IFORMFL_XADD_LAST =8874, +
+  XED_IFORMFL_XADD_LOCK_FIRST =8875, +
+  XED_IFORMFL_XADD_LOCK_LAST =8876, +
+  XED_IFORMFL_XBEGIN_FIRST =8877, +
+  XED_IFORMFL_XBEGIN_LAST =8877, +
+  XED_IFORMFL_XCHG_FIRST =8878, +
+  XED_IFORMFL_XCHG_LAST =8882, +
+  XED_IFORMFL_XEND_FIRST =8883, +
+  XED_IFORMFL_XEND_LAST =8883, +
+  XED_IFORMFL_XGETBV_FIRST =8884, +
+  XED_IFORMFL_XGETBV_LAST =8884, +
+  XED_IFORMFL_XLAT_FIRST =8885, +
+  XED_IFORMFL_XLAT_LAST =8885, +
+  XED_IFORMFL_XOR_FIRST =8886, +
+  XED_IFORMFL_XOR_LAST =8927, +
+  XED_IFORMFL_XORPD_FIRST =8928, +
+  XED_IFORMFL_XORPD_LAST =8929, +
+  XED_IFORMFL_XORPS_FIRST =8930, +
+  XED_IFORMFL_XORPS_LAST =8931, +
+  XED_IFORMFL_XOR_LOCK_FIRST =8932, +
+  XED_IFORMFL_XOR_LOCK_LAST =8937, +
+  XED_IFORMFL_XRESLDTRK_FIRST =8938, +
+  XED_IFORMFL_XRESLDTRK_LAST =8938, +
+  XED_IFORMFL_XRSTOR_FIRST =8939, +
+  XED_IFORMFL_XRSTOR_LAST =8939, +
+  XED_IFORMFL_XRSTOR64_FIRST =8940, +
+  XED_IFORMFL_XRSTOR64_LAST =8940, +
+  XED_IFORMFL_XRSTORS_FIRST =8941, +
+  XED_IFORMFL_XRSTORS_LAST =8941, +
+  XED_IFORMFL_XRSTORS64_FIRST =8942, +
+  XED_IFORMFL_XRSTORS64_LAST =8942, +
+  XED_IFORMFL_XSAVE_FIRST =8943, +
+  XED_IFORMFL_XSAVE_LAST =8943, +
+  XED_IFORMFL_XSAVE64_FIRST =8944, +
+  XED_IFORMFL_XSAVE64_LAST =8944, +
+  XED_IFORMFL_XSAVEC_FIRST =8945, +
+  XED_IFORMFL_XSAVEC_LAST =8945, +
+  XED_IFORMFL_XSAVEC64_FIRST =8946, +
+  XED_IFORMFL_XSAVEC64_LAST =8946, +
+  XED_IFORMFL_XSAVEOPT_FIRST =8947, +
+  XED_IFORMFL_XSAVEOPT_LAST =8947, +
+  XED_IFORMFL_XSAVEOPT64_FIRST =8948, +
+  XED_IFORMFL_XSAVEOPT64_LAST =8948, +
+  XED_IFORMFL_XSAVES_FIRST =8949, +
+  XED_IFORMFL_XSAVES_LAST =8949, +
+  XED_IFORMFL_XSAVES64_FIRST =8950, +
+  XED_IFORMFL_XSAVES64_LAST =8950, +
+  XED_IFORMFL_XSETBV_FIRST =8951, +
+  XED_IFORMFL_XSETBV_LAST =8951, +
+  XED_IFORMFL_XSTORE_FIRST =8952, +
+  XED_IFORMFL_XSTORE_LAST =8952, +
+  XED_IFORMFL_XSUSLDTRK_FIRST =8953, +
+  XED_IFORMFL_XSUSLDTRK_LAST =8953, +
+  XED_IFORMFL_XTEST_FIRST =8954, +
+  XED_IFORMFL_XTEST_LAST =8954,
  XED_IFORMFL_LAST
@@ -29736,6 +30664,34 @@

+ + + +

◆ XED_IFORMFL_MOVRS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_MOVRS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_MOVRS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_MOVRS_LAST_DEFINED   1
+
+
@@ -34412,6 +35368,34 @@

+ + + +

◆ XED_IFORMFL_PREFETCHRST2_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_PREFETCHRST2_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_PREFETCHRST2_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_PREFETCHRST2_LAST_DEFINED   1
+
+
@@ -40516,6 +41500,230 @@

+ + + +

◆ XED_IFORMFL_T2RPNTLVWZ0_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0RS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0RS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0RS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0RS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0RST1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0RST1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0RST1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0RST1_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0T1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0T1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ0T1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ0T1_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1RS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1RS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1RS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1RS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1RST1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1RST1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1RST1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1RST1_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1T1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1T1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_T2RPNTLVWZ1T1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_T2RPNTLVWZ1T1_LAST_DEFINED   1
+
+
@@ -40572,6 +41780,202 @@

+ + + +

◆ XED_IFORMFL_TCONJTCMMIMFP16PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCONJTCMMIMFP16PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCONJTCMMIMFP16PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCONJTCMMIMFP16PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCONJTFP16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCONJTFP16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCONJTFP16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCONJTFP16_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWD2PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWD2PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWD2PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWD2PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PBF16H_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PBF16H_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PBF16H_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PBF16H_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PBF16L_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PBF16L_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PBF16L_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PBF16L_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PHH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PHH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PHH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PHH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PHL_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PHL_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TCVTROWPS2PHL_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TCVTROWPS2PHL_LAST_DEFINED   1
+
+
@@ -40628,6 +42032,62 @@

+ + + +

◆ XED_IFORMFL_TDPBF8PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPBF8PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPBF8PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPBF8PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPBHF8PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPBHF8PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPBHF8PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPBHF8PS_LAST_DEFINED   1
+
+
@@ -40768,6 +42228,62 @@

+ + + +

◆ XED_IFORMFL_TDPHBF8PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPHBF8PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPHBF8PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPHBF8PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPHF8PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPHF8PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TDPHF8PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TDPHF8PS_LAST_DEFINED   1
+
+
@@ -40852,6 +42368,62 @@

+ + + +

◆ XED_IFORMFL_TILELOADDRS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILELOADDRS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TILELOADDRS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILELOADDRS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TILELOADDRST1_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILELOADDRST1_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TILELOADDRST1_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILELOADDRST1_LAST_DEFINED   1
+
+
@@ -40880,6 +42452,34 @@

+ + + +

◆ XED_IFORMFL_TILEMOVROW_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILEMOVROW_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TILEMOVROW_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TILEMOVROW_LAST_DEFINED   1
+
+
@@ -40992,6 +42592,34 @@

+ + + +

◆ XED_IFORMFL_TMMULTF32PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TMMULTF32PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TMMULTF32PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TMMULTF32PS_LAST_DEFINED   1
+
+
@@ -41020,6 +42648,174 @@

+ + + +

◆ XED_IFORMFL_TTCMMIMFP16PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTCMMIMFP16PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTCMMIMFP16PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTCMMIMFP16PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTCMMRLFP16PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTCMMRLFP16PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTCMMRLFP16PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTCMMRLFP16PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTDPBF16PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTDPBF16PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTDPBF16PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTDPBF16PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTDPFP16PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTDPFP16PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTDPFP16PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTDPFP16PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTMMULTF32PS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTMMULTF32PS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTMMULTF32PS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTMMULTF32PS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTRANSPOSED_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTRANSPOSED_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_TTRANSPOSED_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_TTRANSPOSED_LAST_DEFINED   1
+
+
@@ -41580,6 +43376,34 @@

+ + + +

◆ XED_IFORMFL_VADDNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VADDNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VADDNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VADDNEPBF16_LAST_DEFINED   1
+
+
@@ -42756,6 +44580,34 @@

+ + + +

◆ XED_IFORMFL_VCMPPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCMPPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCMPPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCMPPBF16_LAST_DEFINED   1
+
+
@@ -43064,6 +44916,258 @@

+ + + +

◆ XED_IFORMFL_VCOMSBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMSBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMSBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMSBF16_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSD_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSD_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSD_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSD_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCOMXSS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCOMXSS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVT2PS2PHX_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVT2PS2PHX_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVT2PS2PHX_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVT2PS2PHX_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2BF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2BF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2BF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2BF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2BF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2BF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2BF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2BF8S_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2HF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2HF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2HF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2HF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2HF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2HF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTBIASPH2HF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTBIASPH2HF8S_LAST_DEFINED   1
+
+
@@ -43148,6 +45252,146 @@

+ + + +

◆ XED_IFORMFL_VCVTHF82PH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTHF82PH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTHF82PH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTHF82PH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2BF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2BF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2BF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2BF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2BF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2BF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2BF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2BF8S_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2HF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2HF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2HF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2HF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2HF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2HF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNE2PH2HF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNE2PH2HF8S_LAST_DEFINED   1
+
+
@@ -43176,6 +45420,62 @@

+ + + +

◆ XED_IFORMFL_VCVTNEBF162IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEBF162IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEBF162IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEBF162IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEBF162IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEBF162IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEBF162IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEBF162IUBS_LAST_DEFINED   1
+
+
@@ -43288,6 +45588,118 @@

+ + + +

◆ XED_IFORMFL_VCVTNEPH2BF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2BF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2BF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2BF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2BF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2BF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2BF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2BF8S_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2HF8_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2HF8_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2HF8_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2HF8_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2HF8S_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2HF8S_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTNEPH2HF8S_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTNEPH2HF8S_LAST_DEFINED   1
+
+
@@ -43512,6 +45924,62 @@

+ + + +

◆ XED_IFORMFL_VCVTPH2IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPH2IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPH2IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPH2IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPH2IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPH2IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPH2IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPH2IUBS_LAST_DEFINED   1
+
+
@@ -43764,6 +46232,62 @@

+ + + +

◆ XED_IFORMFL_VCVTPS2IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPS2IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPS2IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPS2IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPS2IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPS2IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTPS2IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTPS2IUBS_LAST_DEFINED   1
+
+
@@ -44436,6 +46960,62 @@

+ + + +

◆ XED_IFORMFL_VCVTTNEBF162IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTNEBF162IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTNEBF162IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTNEBF162IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTNEBF162IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTNEBF162IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTNEBF162IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTNEBF162IUBS_LAST_DEFINED   1
+
+
@@ -44464,6 +47044,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPD2DQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2DQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPD2DQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2DQS_LAST_DEFINED   1
+
+
@@ -44492,6 +47100,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPD2QQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2QQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPD2QQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2QQS_LAST_DEFINED   1
+
+
@@ -44520,6 +47156,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPD2UDQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2UDQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPD2UDQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2UDQS_LAST_DEFINED   1
+
+
@@ -44548,6 +47212,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPD2UQQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2UQQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPD2UQQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPD2UQQS_LAST_DEFINED   1
+
+
@@ -44576,6 +47268,62 @@

+ + + +

◆ XED_IFORMFL_VCVTTPH2IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPH2IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPH2IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPH2IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPH2IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPH2IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPH2IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPH2IUBS_LAST_DEFINED   1
+
+
@@ -44744,6 +47492,90 @@

+ + + +

◆ XED_IFORMFL_VCVTTPS2DQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2DQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2DQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2DQS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2IBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2IBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2IBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2IBS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2IUBS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2IUBS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2IUBS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2IUBS_LAST_DEFINED   1
+
+
@@ -44772,6 +47604,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPS2QQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2QQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2QQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2QQS_LAST_DEFINED   1
+
+
@@ -44800,6 +47660,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPS2UDQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2UDQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2UDQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2UDQS_LAST_DEFINED   1
+
+
@@ -44828,6 +47716,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTPS2UQQS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2UQQS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTPS2UQQS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTPS2UQQS_LAST_DEFINED   1
+
+
@@ -44856,6 +47772,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTSD2SIS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSD2SIS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTSD2SIS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSD2SIS_LAST_DEFINED   1
+
+
@@ -44884,6 +47828,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTSD2USIS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSD2USIS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTSD2USIS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSD2USIS_LAST_DEFINED   1
+
+
@@ -44968,6 +47940,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTSS2SIS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSS2SIS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTSS2SIS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSS2SIS_LAST_DEFINED   1
+
+
@@ -44996,6 +47996,34 @@

+ + + +

◆ XED_IFORMFL_VCVTTSS2USIS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSS2USIS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VCVTTSS2USIS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VCVTTSS2USIS_LAST_DEFINED   1
+
+
@@ -45332,6 +48360,34 @@

+ + + +

◆ XED_IFORMFL_VDIVNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VDIVNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VDIVNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VDIVNEPBF16_LAST_DEFINED   1
+
+
@@ -45556,6 +48612,34 @@

+ + + +

◆ XED_IFORMFL_VDPPHPS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VDPPHPS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VDPPHPS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VDPPHPS_LAST_DEFINED   1
+
+
@@ -46284,6 +49368,34 @@

+ + + +

◆ XED_IFORMFL_VFMADD132NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD132NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMADD132NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD132NEPBF16_LAST_DEFINED   1
+
+
@@ -46452,6 +49564,34 @@

+ + + +

◆ XED_IFORMFL_VFMADD213NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD213NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMADD213NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD213NEPBF16_LAST_DEFINED   1
+
+
@@ -46620,6 +49760,34 @@

+ + + +

◆ XED_IFORMFL_VFMADD231NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD231NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMADD231NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMADD231NEPBF16_LAST_DEFINED   1
+
+
@@ -47264,6 +50432,34 @@

+ + + +

◆ XED_IFORMFL_VFMSUB132NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB132NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMSUB132NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB132NEPBF16_LAST_DEFINED   1
+
+
@@ -47432,6 +50628,34 @@

+ + + +

◆ XED_IFORMFL_VFMSUB213NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB213NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMSUB213NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB213NEPBF16_LAST_DEFINED   1
+
+
@@ -47600,6 +50824,34 @@

+ + + +

◆ XED_IFORMFL_VFMSUB231NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB231NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFMSUB231NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFMSUB231NEPBF16_LAST_DEFINED   1
+
+
@@ -48244,6 +51496,34 @@

+ + + +

◆ XED_IFORMFL_VFNMADD132NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD132NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMADD132NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD132NEPBF16_LAST_DEFINED   1
+
+
@@ -48412,6 +51692,34 @@

+ + + +

◆ XED_IFORMFL_VFNMADD213NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD213NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMADD213NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD213NEPBF16_LAST_DEFINED   1
+
+
@@ -48580,6 +51888,34 @@

+ + + +

◆ XED_IFORMFL_VFNMADD231NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD231NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMADD231NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMADD231NEPBF16_LAST_DEFINED   1
+
+
@@ -48860,6 +52196,34 @@

+ + + +

◆ XED_IFORMFL_VFNMSUB132NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB132NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMSUB132NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB132NEPBF16_LAST_DEFINED   1
+
+
@@ -49028,6 +52392,34 @@

+ + + +

◆ XED_IFORMFL_VFNMSUB213NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB213NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMSUB213NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB213NEPBF16_LAST_DEFINED   1
+
+
@@ -49196,6 +52588,34 @@

+ + + +

◆ XED_IFORMFL_VFNMSUB231NEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB231NEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFNMSUB231NEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFNMSUB231NEPBF16_LAST_DEFINED   1
+
+
@@ -49476,6 +52896,34 @@

+ + + +

◆ XED_IFORMFL_VFPCLASSPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFPCLASSPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VFPCLASSPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VFPCLASSPBF16_LAST_DEFINED   1
+
+
@@ -50092,6 +53540,34 @@

+ + + +

◆ XED_IFORMFL_VGETEXPPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VGETEXPPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VGETEXPPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VGETEXPPBF16_LAST_DEFINED   1
+
+
@@ -50260,6 +53736,34 @@

+ + + +

◆ XED_IFORMFL_VGETMANTPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VGETMANTPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VGETMANTPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VGETMANTPBF16_LAST_DEFINED   1
+
+
@@ -51072,6 +54576,34 @@

+ + + +

◆ XED_IFORMFL_VMAXPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMAXPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMAXPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMAXPBF16_LAST_DEFINED   1
+
+
@@ -51324,6 +54856,230 @@

+ + + +

◆ XED_IFORMFL_VMINMAXNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXNEPBF16_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPD_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPD_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPD_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPD_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXPS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXPS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSD_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSD_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSD_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSD_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINMAXSS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINMAXSS_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMINPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMINPBF16_LAST_DEFINED   1
+
+
@@ -52276,6 +56032,118 @@

+ + + +

◆ XED_IFORMFL_VMOVRSB_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSB_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSB_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSB_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSD_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSD_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSD_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSD_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSQ_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSQ_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSQ_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSQ_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSW_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSW_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMOVRSW_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMOVRSW_LAST_DEFINED   1
+
+
@@ -52696,6 +56564,34 @@

+ + + +

◆ XED_IFORMFL_VMULNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMULNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VMULNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VMULNEPBF16_LAST_DEFINED   1
+
+
@@ -63056,6 +66952,34 @@

+ + + +

◆ XED_IFORMFL_VRCPPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRCPPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VRCPPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRCPPBF16_LAST_DEFINED   1
+
+
@@ -63168,6 +67092,34 @@

+ + + +

◆ XED_IFORMFL_VREDUCENEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VREDUCENEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VREDUCENEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VREDUCENEPBF16_LAST_DEFINED   1
+
+
@@ -63336,6 +67288,34 @@

+ + + +

◆ XED_IFORMFL_VRNDSCALENEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRNDSCALENEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VRNDSCALENEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRNDSCALENEPBF16_LAST_DEFINED   1
+
+
@@ -63840,6 +67820,34 @@

+ + + +

◆ XED_IFORMFL_VRSQRTPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRSQRTPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VRSQRTPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VRSQRTPBF16_LAST_DEFINED   1
+
+
@@ -63952,6 +67960,34 @@

+ + + +

◆ XED_IFORMFL_VSCALEFPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSCALEFPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VSCALEFPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSCALEFPBF16_LAST_DEFINED   1
+
+
@@ -64848,6 +68884,34 @@

+ + + +

◆ XED_IFORMFL_VSQRTNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSQRTNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VSQRTNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSQRTNEPBF16_LAST_DEFINED   1
+
+
@@ -65044,6 +69108,34 @@

+ + + +

◆ XED_IFORMFL_VSUBNEPBF16_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSUBNEPBF16_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VSUBNEPBF16_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VSUBNEPBF16_LAST_DEFINED   1
+
+
@@ -65352,6 +69444,90 @@

+ + + +

◆ XED_IFORMFL_VUCOMXSD_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSD_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VUCOMXSD_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSD_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VUCOMXSH_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSH_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VUCOMXSH_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSH_LAST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VUCOMXSS_FIRST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSS_FIRST_DEFINED   1
+
+ +
+
+ +

◆ XED_IFORMFL_VUCOMXSS_LAST_DEFINED

+ +
+
+ + + + +
#define XED_IFORMFL_VUCOMXSS_LAST_DEFINED   1
+
+
@@ -67793,6 +71969,8 @@

XED_IFORMFL_MOVQ_LAST  XED_IFORMFL_MOVQ2DQ_FIRST  XED_IFORMFL_MOVQ2DQ_LAST  +XED_IFORMFL_MOVRS_FIRST  +XED_IFORMFL_MOVRS_LAST  XED_IFORMFL_MOVSB_FIRST  XED_IFORMFL_MOVSB_LAST  XED_IFORMFL_MOVSD_FIRST  @@ -68127,6 +72305,8 @@

XED_IFORMFL_PREFETCHIT1_LAST  XED_IFORMFL_PREFETCHNTA_FIRST  XED_IFORMFL_PREFETCHNTA_LAST  +XED_IFORMFL_PREFETCHRST2_FIRST  +XED_IFORMFL_PREFETCHRST2_LAST  XED_IFORMFL_PREFETCHT0_FIRST  XED_IFORMFL_PREFETCHT0_LAST  XED_IFORMFL_PREFETCHT1_FIRST  @@ -68567,14 +72747,48 @@

XED_IFORMFL_SYSRET_AMD_LAST  XED_IFORMFL_T1MSKC_FIRST  XED_IFORMFL_T1MSKC_LAST  +XED_IFORMFL_T2RPNTLVWZ0_FIRST  +XED_IFORMFL_T2RPNTLVWZ0_LAST  +XED_IFORMFL_T2RPNTLVWZ0RS_FIRST  +XED_IFORMFL_T2RPNTLVWZ0RS_LAST  +XED_IFORMFL_T2RPNTLVWZ0RST1_FIRST  +XED_IFORMFL_T2RPNTLVWZ0RST1_LAST  +XED_IFORMFL_T2RPNTLVWZ0T1_FIRST  +XED_IFORMFL_T2RPNTLVWZ0T1_LAST  +XED_IFORMFL_T2RPNTLVWZ1_FIRST  +XED_IFORMFL_T2RPNTLVWZ1_LAST  +XED_IFORMFL_T2RPNTLVWZ1RS_FIRST  +XED_IFORMFL_T2RPNTLVWZ1RS_LAST  +XED_IFORMFL_T2RPNTLVWZ1RST1_FIRST  +XED_IFORMFL_T2RPNTLVWZ1RST1_LAST  +XED_IFORMFL_T2RPNTLVWZ1T1_FIRST  +XED_IFORMFL_T2RPNTLVWZ1T1_LAST  XED_IFORMFL_TCMMIMFP16PS_FIRST  XED_IFORMFL_TCMMIMFP16PS_LAST  XED_IFORMFL_TCMMRLFP16PS_FIRST  XED_IFORMFL_TCMMRLFP16PS_LAST  +XED_IFORMFL_TCONJTCMMIMFP16PS_FIRST  +XED_IFORMFL_TCONJTCMMIMFP16PS_LAST  +XED_IFORMFL_TCONJTFP16_FIRST  +XED_IFORMFL_TCONJTFP16_LAST  +XED_IFORMFL_TCVTROWD2PS_FIRST  +XED_IFORMFL_TCVTROWD2PS_LAST  +XED_IFORMFL_TCVTROWPS2PBF16H_FIRST  +XED_IFORMFL_TCVTROWPS2PBF16H_LAST  +XED_IFORMFL_TCVTROWPS2PBF16L_FIRST  +XED_IFORMFL_TCVTROWPS2PBF16L_LAST  +XED_IFORMFL_TCVTROWPS2PHH_FIRST  +XED_IFORMFL_TCVTROWPS2PHH_LAST  +XED_IFORMFL_TCVTROWPS2PHL_FIRST  +XED_IFORMFL_TCVTROWPS2PHL_LAST  XED_IFORMFL_TDCALL_FIRST  XED_IFORMFL_TDCALL_LAST  XED_IFORMFL_TDPBF16PS_FIRST  XED_IFORMFL_TDPBF16PS_LAST  +XED_IFORMFL_TDPBF8PS_FIRST  +XED_IFORMFL_TDPBF8PS_LAST  +XED_IFORMFL_TDPBHF8PS_FIRST  +XED_IFORMFL_TDPBHF8PS_LAST  XED_IFORMFL_TDPBSSD_FIRST  XED_IFORMFL_TDPBSSD_LAST  XED_IFORMFL_TDPBSUD_FIRST  @@ -68585,14 +72799,24 @@

XED_IFORMFL_TDPBUUD_LAST  XED_IFORMFL_TDPFP16PS_FIRST  XED_IFORMFL_TDPFP16PS_LAST  +XED_IFORMFL_TDPHBF8PS_FIRST  +XED_IFORMFL_TDPHBF8PS_LAST  +XED_IFORMFL_TDPHF8PS_FIRST  +XED_IFORMFL_TDPHF8PS_LAST  XED_IFORMFL_TEST_FIRST  XED_IFORMFL_TEST_LAST  XED_IFORMFL_TESTUI_FIRST  XED_IFORMFL_TESTUI_LAST  XED_IFORMFL_TILELOADD_FIRST  XED_IFORMFL_TILELOADD_LAST  +XED_IFORMFL_TILELOADDRS_FIRST  +XED_IFORMFL_TILELOADDRS_LAST  +XED_IFORMFL_TILELOADDRST1_FIRST  +XED_IFORMFL_TILELOADDRST1_LAST  XED_IFORMFL_TILELOADDT1_FIRST  XED_IFORMFL_TILELOADDT1_LAST  +XED_IFORMFL_TILEMOVROW_FIRST  +XED_IFORMFL_TILEMOVROW_LAST  XED_IFORMFL_TILERELEASE_FIRST  XED_IFORMFL_TILERELEASE_LAST  XED_IFORMFL_TILESTORED_FIRST  @@ -68601,8 +72825,22 @@

XED_IFORMFL_TILEZERO_LAST  XED_IFORMFL_TLBSYNC_FIRST  XED_IFORMFL_TLBSYNC_LAST  +XED_IFORMFL_TMMULTF32PS_FIRST  +XED_IFORMFL_TMMULTF32PS_LAST  XED_IFORMFL_TPAUSE_FIRST  XED_IFORMFL_TPAUSE_LAST  +XED_IFORMFL_TTCMMIMFP16PS_FIRST  +XED_IFORMFL_TTCMMIMFP16PS_LAST  +XED_IFORMFL_TTCMMRLFP16PS_FIRST  +XED_IFORMFL_TTCMMRLFP16PS_LAST  +XED_IFORMFL_TTDPBF16PS_FIRST  +XED_IFORMFL_TTDPBF16PS_LAST  +XED_IFORMFL_TTDPFP16PS_FIRST  +XED_IFORMFL_TTDPFP16PS_LAST  +XED_IFORMFL_TTMMULTF32PS_FIRST  +XED_IFORMFL_TTMMULTF32PS_LAST  +XED_IFORMFL_TTRANSPOSED_FIRST  +XED_IFORMFL_TTRANSPOSED_LAST  XED_IFORMFL_TZCNT_FIRST  XED_IFORMFL_TZCNT_LAST  XED_IFORMFL_TZMSK_FIRST  @@ -68643,6 +72881,8 @@

XED_IFORMFL_V4FNMADDPS_LAST  XED_IFORMFL_V4FNMADDSS_FIRST  XED_IFORMFL_V4FNMADDSS_LAST  +XED_IFORMFL_VADDNEPBF16_FIRST  +XED_IFORMFL_VADDNEPBF16_LAST  XED_IFORMFL_VADDPD_FIRST  XED_IFORMFL_VADDPD_LAST  XED_IFORMFL_VADDPH_FIRST  @@ -68727,6 +72967,8 @@

XED_IFORMFL_VBROADCASTSD_LAST  XED_IFORMFL_VBROADCASTSS_FIRST  XED_IFORMFL_VBROADCASTSS_LAST  +XED_IFORMFL_VCMPPBF16_FIRST  +XED_IFORMFL_VCMPPBF16_LAST  XED_IFORMFL_VCMPPD_FIRST  XED_IFORMFL_VCMPPD_LAST  XED_IFORMFL_VCMPPH_FIRST  @@ -68749,14 +72991,46 @@

XED_IFORMFL_VCOMPRESSPD_LAST  XED_IFORMFL_VCOMPRESSPS_FIRST  XED_IFORMFL_VCOMPRESSPS_LAST  +XED_IFORMFL_VCOMSBF16_FIRST  +XED_IFORMFL_VCOMSBF16_LAST  +XED_IFORMFL_VCOMXSD_FIRST  +XED_IFORMFL_VCOMXSD_LAST  +XED_IFORMFL_VCOMXSH_FIRST  +XED_IFORMFL_VCOMXSH_LAST  +XED_IFORMFL_VCOMXSS_FIRST  +XED_IFORMFL_VCOMXSS_LAST  +XED_IFORMFL_VCVT2PS2PHX_FIRST  +XED_IFORMFL_VCVT2PS2PHX_LAST  +XED_IFORMFL_VCVTBIASPH2BF8_FIRST  +XED_IFORMFL_VCVTBIASPH2BF8_LAST  +XED_IFORMFL_VCVTBIASPH2BF8S_FIRST  +XED_IFORMFL_VCVTBIASPH2BF8S_LAST  +XED_IFORMFL_VCVTBIASPH2HF8_FIRST  +XED_IFORMFL_VCVTBIASPH2HF8_LAST  +XED_IFORMFL_VCVTBIASPH2HF8S_FIRST  +XED_IFORMFL_VCVTBIASPH2HF8S_LAST  XED_IFORMFL_VCVTDQ2PD_FIRST  XED_IFORMFL_VCVTDQ2PD_LAST  XED_IFORMFL_VCVTDQ2PH_FIRST  XED_IFORMFL_VCVTDQ2PH_LAST  XED_IFORMFL_VCVTDQ2PS_FIRST  XED_IFORMFL_VCVTDQ2PS_LAST  +XED_IFORMFL_VCVTHF82PH_FIRST  +XED_IFORMFL_VCVTHF82PH_LAST  +XED_IFORMFL_VCVTNE2PH2BF8_FIRST  +XED_IFORMFL_VCVTNE2PH2BF8_LAST  +XED_IFORMFL_VCVTNE2PH2BF8S_FIRST  +XED_IFORMFL_VCVTNE2PH2BF8S_LAST  +XED_IFORMFL_VCVTNE2PH2HF8_FIRST  +XED_IFORMFL_VCVTNE2PH2HF8_LAST  +XED_IFORMFL_VCVTNE2PH2HF8S_FIRST  +XED_IFORMFL_VCVTNE2PH2HF8S_LAST  XED_IFORMFL_VCVTNE2PS2BF16_FIRST  XED_IFORMFL_VCVTNE2PS2BF16_LAST  +XED_IFORMFL_VCVTNEBF162IBS_FIRST  +XED_IFORMFL_VCVTNEBF162IBS_LAST  +XED_IFORMFL_VCVTNEBF162IUBS_FIRST  +XED_IFORMFL_VCVTNEBF162IUBS_LAST  XED_IFORMFL_VCVTNEEBF162PS_FIRST  XED_IFORMFL_VCVTNEEBF162PS_LAST  XED_IFORMFL_VCVTNEEPH2PS_FIRST  @@ -68765,6 +73039,14 @@

XED_IFORMFL_VCVTNEOBF162PS_LAST  XED_IFORMFL_VCVTNEOPH2PS_FIRST  XED_IFORMFL_VCVTNEOPH2PS_LAST  +XED_IFORMFL_VCVTNEPH2BF8_FIRST  +XED_IFORMFL_VCVTNEPH2BF8_LAST  +XED_IFORMFL_VCVTNEPH2BF8S_FIRST  +XED_IFORMFL_VCVTNEPH2BF8S_LAST  +XED_IFORMFL_VCVTNEPH2HF8_FIRST  +XED_IFORMFL_VCVTNEPH2HF8_LAST  +XED_IFORMFL_VCVTNEPH2HF8S_FIRST  +XED_IFORMFL_VCVTNEPH2HF8S_LAST  XED_IFORMFL_VCVTNEPS2BF16_FIRST  XED_IFORMFL_VCVTNEPS2BF16_LAST  XED_IFORMFL_VCVTPD2DQ_FIRST  @@ -68781,6 +73063,10 @@

XED_IFORMFL_VCVTPD2UQQ_LAST  XED_IFORMFL_VCVTPH2DQ_FIRST  XED_IFORMFL_VCVTPH2DQ_LAST  +XED_IFORMFL_VCVTPH2IBS_FIRST  +XED_IFORMFL_VCVTPH2IBS_LAST  +XED_IFORMFL_VCVTPH2IUBS_FIRST  +XED_IFORMFL_VCVTPH2IUBS_LAST  XED_IFORMFL_VCVTPH2PD_FIRST  XED_IFORMFL_VCVTPH2PD_LAST  XED_IFORMFL_VCVTPH2PS_FIRST  @@ -68799,6 +73085,10 @@

XED_IFORMFL_VCVTPH2W_LAST  XED_IFORMFL_VCVTPS2DQ_FIRST  XED_IFORMFL_VCVTPS2DQ_LAST  +XED_IFORMFL_VCVTPS2IBS_FIRST  +XED_IFORMFL_VCVTPS2IBS_LAST  +XED_IFORMFL_VCVTPS2IUBS_FIRST  +XED_IFORMFL_VCVTPS2IUBS_LAST  XED_IFORMFL_VCVTPS2PD_FIRST  XED_IFORMFL_VCVTPS2PD_LAST  XED_IFORMFL_VCVTPS2PH_FIRST  @@ -68847,16 +73137,32 @@

XED_IFORMFL_VCVTSS2SI_LAST  XED_IFORMFL_VCVTSS2USI_FIRST  XED_IFORMFL_VCVTSS2USI_LAST  +XED_IFORMFL_VCVTTNEBF162IBS_FIRST  +XED_IFORMFL_VCVTTNEBF162IBS_LAST  +XED_IFORMFL_VCVTTNEBF162IUBS_FIRST  +XED_IFORMFL_VCVTTNEBF162IUBS_LAST  XED_IFORMFL_VCVTTPD2DQ_FIRST  XED_IFORMFL_VCVTTPD2DQ_LAST  +XED_IFORMFL_VCVTTPD2DQS_FIRST  +XED_IFORMFL_VCVTTPD2DQS_LAST  XED_IFORMFL_VCVTTPD2QQ_FIRST  XED_IFORMFL_VCVTTPD2QQ_LAST  +XED_IFORMFL_VCVTTPD2QQS_FIRST  +XED_IFORMFL_VCVTTPD2QQS_LAST  XED_IFORMFL_VCVTTPD2UDQ_FIRST  XED_IFORMFL_VCVTTPD2UDQ_LAST  +XED_IFORMFL_VCVTTPD2UDQS_FIRST  +XED_IFORMFL_VCVTTPD2UDQS_LAST  XED_IFORMFL_VCVTTPD2UQQ_FIRST  XED_IFORMFL_VCVTTPD2UQQ_LAST  +XED_IFORMFL_VCVTTPD2UQQS_FIRST  +XED_IFORMFL_VCVTTPD2UQQS_LAST  XED_IFORMFL_VCVTTPH2DQ_FIRST  XED_IFORMFL_VCVTTPH2DQ_LAST  +XED_IFORMFL_VCVTTPH2IBS_FIRST  +XED_IFORMFL_VCVTTPH2IBS_LAST  +XED_IFORMFL_VCVTTPH2IUBS_FIRST  +XED_IFORMFL_VCVTTPH2IUBS_LAST  XED_IFORMFL_VCVTTPH2QQ_FIRST  XED_IFORMFL_VCVTTPH2QQ_LAST  XED_IFORMFL_VCVTTPH2UDQ_FIRST  @@ -68869,24 +73175,44 @@

XED_IFORMFL_VCVTTPH2W_LAST  XED_IFORMFL_VCVTTPS2DQ_FIRST  XED_IFORMFL_VCVTTPS2DQ_LAST  +XED_IFORMFL_VCVTTPS2DQS_FIRST  +XED_IFORMFL_VCVTTPS2DQS_LAST  +XED_IFORMFL_VCVTTPS2IBS_FIRST  +XED_IFORMFL_VCVTTPS2IBS_LAST  +XED_IFORMFL_VCVTTPS2IUBS_FIRST  +XED_IFORMFL_VCVTTPS2IUBS_LAST  XED_IFORMFL_VCVTTPS2QQ_FIRST  XED_IFORMFL_VCVTTPS2QQ_LAST  +XED_IFORMFL_VCVTTPS2QQS_FIRST  +XED_IFORMFL_VCVTTPS2QQS_LAST  XED_IFORMFL_VCVTTPS2UDQ_FIRST  XED_IFORMFL_VCVTTPS2UDQ_LAST  +XED_IFORMFL_VCVTTPS2UDQS_FIRST  +XED_IFORMFL_VCVTTPS2UDQS_LAST  XED_IFORMFL_VCVTTPS2UQQ_FIRST  XED_IFORMFL_VCVTTPS2UQQ_LAST  +XED_IFORMFL_VCVTTPS2UQQS_FIRST  +XED_IFORMFL_VCVTTPS2UQQS_LAST  XED_IFORMFL_VCVTTSD2SI_FIRST  XED_IFORMFL_VCVTTSD2SI_LAST  +XED_IFORMFL_VCVTTSD2SIS_FIRST  +XED_IFORMFL_VCVTTSD2SIS_LAST  XED_IFORMFL_VCVTTSD2USI_FIRST  XED_IFORMFL_VCVTTSD2USI_LAST  +XED_IFORMFL_VCVTTSD2USIS_FIRST  +XED_IFORMFL_VCVTTSD2USIS_LAST  XED_IFORMFL_VCVTTSH2SI_FIRST  XED_IFORMFL_VCVTTSH2SI_LAST  XED_IFORMFL_VCVTTSH2USI_FIRST  XED_IFORMFL_VCVTTSH2USI_LAST  XED_IFORMFL_VCVTTSS2SI_FIRST  XED_IFORMFL_VCVTTSS2SI_LAST  +XED_IFORMFL_VCVTTSS2SIS_FIRST  +XED_IFORMFL_VCVTTSS2SIS_LAST  XED_IFORMFL_VCVTTSS2USI_FIRST  XED_IFORMFL_VCVTTSS2USI_LAST  +XED_IFORMFL_VCVTTSS2USIS_FIRST  +XED_IFORMFL_VCVTTSS2USIS_LAST  XED_IFORMFL_VCVTUDQ2PD_FIRST  XED_IFORMFL_VCVTUDQ2PD_LAST  XED_IFORMFL_VCVTUDQ2PH_FIRST  @@ -68911,6 +73237,8 @@

XED_IFORMFL_VCVTW2PH_LAST  XED_IFORMFL_VDBPSADBW_FIRST  XED_IFORMFL_VDBPSADBW_LAST  +XED_IFORMFL_VDIVNEPBF16_FIRST  +XED_IFORMFL_VDIVNEPBF16_LAST  XED_IFORMFL_VDIVPD_FIRST  XED_IFORMFL_VDIVPD_LAST  XED_IFORMFL_VDIVPH_FIRST  @@ -68927,6 +73255,8 @@

XED_IFORMFL_VDPBF16PS_LAST  XED_IFORMFL_VDPPD_FIRST  XED_IFORMFL_VDPPD_LAST  +XED_IFORMFL_VDPPHPS_FIRST  +XED_IFORMFL_VDPPHPS_LAST  XED_IFORMFL_VDPPS_FIRST  XED_IFORMFL_VDPPS_LAST  XED_IFORMFL_VERR_FIRST  @@ -68979,6 +73309,8 @@

XED_IFORMFL_VFIXUPIMMSD_LAST  XED_IFORMFL_VFIXUPIMMSS_FIRST  XED_IFORMFL_VFIXUPIMMSS_LAST  +XED_IFORMFL_VFMADD132NEPBF16_FIRST  +XED_IFORMFL_VFMADD132NEPBF16_LAST  XED_IFORMFL_VFMADD132PD_FIRST  XED_IFORMFL_VFMADD132PD_LAST  XED_IFORMFL_VFMADD132PH_FIRST  @@ -68991,6 +73323,8 @@

XED_IFORMFL_VFMADD132SH_LAST  XED_IFORMFL_VFMADD132SS_FIRST  XED_IFORMFL_VFMADD132SS_LAST  +XED_IFORMFL_VFMADD213NEPBF16_FIRST  +XED_IFORMFL_VFMADD213NEPBF16_LAST  XED_IFORMFL_VFMADD213PD_FIRST  XED_IFORMFL_VFMADD213PD_LAST  XED_IFORMFL_VFMADD213PH_FIRST  @@ -69003,6 +73337,8 @@

XED_IFORMFL_VFMADD213SH_LAST  XED_IFORMFL_VFMADD213SS_FIRST  XED_IFORMFL_VFMADD213SS_LAST  +XED_IFORMFL_VFMADD231NEPBF16_FIRST  +XED_IFORMFL_VFMADD231NEPBF16_LAST  XED_IFORMFL_VFMADD231PD_FIRST  XED_IFORMFL_VFMADD231PD_LAST  XED_IFORMFL_VFMADD231PH_FIRST  @@ -69049,6 +73385,8 @@

XED_IFORMFL_VFMADDSUBPD_LAST  XED_IFORMFL_VFMADDSUBPS_FIRST  XED_IFORMFL_VFMADDSUBPS_LAST  +XED_IFORMFL_VFMSUB132NEPBF16_FIRST  +XED_IFORMFL_VFMSUB132NEPBF16_LAST  XED_IFORMFL_VFMSUB132PD_FIRST  XED_IFORMFL_VFMSUB132PD_LAST  XED_IFORMFL_VFMSUB132PH_FIRST  @@ -69061,6 +73399,8 @@

XED_IFORMFL_VFMSUB132SH_LAST  XED_IFORMFL_VFMSUB132SS_FIRST  XED_IFORMFL_VFMSUB132SS_LAST  +XED_IFORMFL_VFMSUB213NEPBF16_FIRST  +XED_IFORMFL_VFMSUB213NEPBF16_LAST  XED_IFORMFL_VFMSUB213PD_FIRST  XED_IFORMFL_VFMSUB213PD_LAST  XED_IFORMFL_VFMSUB213PH_FIRST  @@ -69073,6 +73413,8 @@

XED_IFORMFL_VFMSUB213SH_LAST  XED_IFORMFL_VFMSUB213SS_FIRST  XED_IFORMFL_VFMSUB213SS_LAST  +XED_IFORMFL_VFMSUB231NEPBF16_FIRST  +XED_IFORMFL_VFMSUB231NEPBF16_LAST  XED_IFORMFL_VFMSUB231PD_FIRST  XED_IFORMFL_VFMSUB231PD_LAST  XED_IFORMFL_VFMSUB231PH_FIRST  @@ -69119,6 +73461,8 @@

XED_IFORMFL_VFMULCPH_LAST  XED_IFORMFL_VFMULCSH_FIRST  XED_IFORMFL_VFMULCSH_LAST  +XED_IFORMFL_VFNMADD132NEPBF16_FIRST  +XED_IFORMFL_VFNMADD132NEPBF16_LAST  XED_IFORMFL_VFNMADD132PD_FIRST  XED_IFORMFL_VFNMADD132PD_LAST  XED_IFORMFL_VFNMADD132PH_FIRST  @@ -69131,6 +73475,8 @@

XED_IFORMFL_VFNMADD132SH_LAST  XED_IFORMFL_VFNMADD132SS_FIRST  XED_IFORMFL_VFNMADD132SS_LAST  +XED_IFORMFL_VFNMADD213NEPBF16_FIRST  +XED_IFORMFL_VFNMADD213NEPBF16_LAST  XED_IFORMFL_VFNMADD213PD_FIRST  XED_IFORMFL_VFNMADD213PD_LAST  XED_IFORMFL_VFNMADD213PH_FIRST  @@ -69143,6 +73489,8 @@

XED_IFORMFL_VFNMADD213SH_LAST  XED_IFORMFL_VFNMADD213SS_FIRST  XED_IFORMFL_VFNMADD213SS_LAST  +XED_IFORMFL_VFNMADD231NEPBF16_FIRST  +XED_IFORMFL_VFNMADD231NEPBF16_LAST  XED_IFORMFL_VFNMADD231PD_FIRST  XED_IFORMFL_VFNMADD231PD_LAST  XED_IFORMFL_VFNMADD231PH_FIRST  @@ -69163,6 +73511,8 @@

XED_IFORMFL_VFNMADDSD_LAST  XED_IFORMFL_VFNMADDSS_FIRST  XED_IFORMFL_VFNMADDSS_LAST  +XED_IFORMFL_VFNMSUB132NEPBF16_FIRST  +XED_IFORMFL_VFNMSUB132NEPBF16_LAST  XED_IFORMFL_VFNMSUB132PD_FIRST  XED_IFORMFL_VFNMSUB132PD_LAST  XED_IFORMFL_VFNMSUB132PH_FIRST  @@ -69175,6 +73525,8 @@

XED_IFORMFL_VFNMSUB132SH_LAST  XED_IFORMFL_VFNMSUB132SS_FIRST  XED_IFORMFL_VFNMSUB132SS_LAST  +XED_IFORMFL_VFNMSUB213NEPBF16_FIRST  +XED_IFORMFL_VFNMSUB213NEPBF16_LAST  XED_IFORMFL_VFNMSUB213PD_FIRST  XED_IFORMFL_VFNMSUB213PD_LAST  XED_IFORMFL_VFNMSUB213PH_FIRST  @@ -69187,6 +73539,8 @@

XED_IFORMFL_VFNMSUB213SH_LAST  XED_IFORMFL_VFNMSUB213SS_FIRST  XED_IFORMFL_VFNMSUB213SS_LAST  +XED_IFORMFL_VFNMSUB231NEPBF16_FIRST  +XED_IFORMFL_VFNMSUB231NEPBF16_LAST  XED_IFORMFL_VFNMSUB231PD_FIRST  XED_IFORMFL_VFNMSUB231PD_LAST  XED_IFORMFL_VFNMSUB231PH_FIRST  @@ -69207,6 +73561,8 @@

XED_IFORMFL_VFNMSUBSD_LAST  XED_IFORMFL_VFNMSUBSS_FIRST  XED_IFORMFL_VFNMSUBSS_LAST  +XED_IFORMFL_VFPCLASSPBF16_FIRST  +XED_IFORMFL_VFPCLASSPBF16_LAST  XED_IFORMFL_VFPCLASSPD_FIRST  XED_IFORMFL_VFPCLASSPD_LAST  XED_IFORMFL_VFPCLASSPH_FIRST  @@ -69251,6 +73607,8 @@

XED_IFORMFL_VGATHERQPD_LAST  XED_IFORMFL_VGATHERQPS_FIRST  XED_IFORMFL_VGATHERQPS_LAST  +XED_IFORMFL_VGETEXPPBF16_FIRST  +XED_IFORMFL_VGETEXPPBF16_LAST  XED_IFORMFL_VGETEXPPD_FIRST  XED_IFORMFL_VGETEXPPD_LAST  XED_IFORMFL_VGETEXPPH_FIRST  @@ -69263,6 +73621,8 @@

XED_IFORMFL_VGETEXPSH_LAST  XED_IFORMFL_VGETEXPSS_FIRST  XED_IFORMFL_VGETEXPSS_LAST  +XED_IFORMFL_VGETMANTPBF16_FIRST  +XED_IFORMFL_VGETMANTPBF16_LAST  XED_IFORMFL_VGETMANTPD_FIRST  XED_IFORMFL_VGETMANTPD_LAST  XED_IFORMFL_VGETMANTPH_FIRST  @@ -69321,6 +73681,8 @@

XED_IFORMFL_VMASKMOVPD_LAST  XED_IFORMFL_VMASKMOVPS_FIRST  XED_IFORMFL_VMASKMOVPS_LAST  +XED_IFORMFL_VMAXPBF16_FIRST  +XED_IFORMFL_VMAXPBF16_LAST  XED_IFORMFL_VMAXPD_FIRST  XED_IFORMFL_VMAXPD_LAST  XED_IFORMFL_VMAXPH_FIRST  @@ -69339,6 +73701,22 @@

XED_IFORMFL_VMCLEAR_LAST  XED_IFORMFL_VMFUNC_FIRST  XED_IFORMFL_VMFUNC_LAST  +XED_IFORMFL_VMINMAXNEPBF16_FIRST  +XED_IFORMFL_VMINMAXNEPBF16_LAST  +XED_IFORMFL_VMINMAXPD_FIRST  +XED_IFORMFL_VMINMAXPD_LAST  +XED_IFORMFL_VMINMAXPH_FIRST  +XED_IFORMFL_VMINMAXPH_LAST  +XED_IFORMFL_VMINMAXPS_FIRST  +XED_IFORMFL_VMINMAXPS_LAST  +XED_IFORMFL_VMINMAXSD_FIRST  +XED_IFORMFL_VMINMAXSD_LAST  +XED_IFORMFL_VMINMAXSH_FIRST  +XED_IFORMFL_VMINMAXSH_LAST  +XED_IFORMFL_VMINMAXSS_FIRST  +XED_IFORMFL_VMINMAXSS_LAST  +XED_IFORMFL_VMINPBF16_FIRST  +XED_IFORMFL_VMINPBF16_LAST  XED_IFORMFL_VMINPD_FIRST  XED_IFORMFL_VMINPD_LAST  XED_IFORMFL_VMINPH_FIRST  @@ -69407,6 +73785,14 @@

XED_IFORMFL_VMOVNTPS_LAST  XED_IFORMFL_VMOVQ_FIRST  XED_IFORMFL_VMOVQ_LAST  +XED_IFORMFL_VMOVRSB_FIRST  +XED_IFORMFL_VMOVRSB_LAST  +XED_IFORMFL_VMOVRSD_FIRST  +XED_IFORMFL_VMOVRSD_LAST  +XED_IFORMFL_VMOVRSQ_FIRST  +XED_IFORMFL_VMOVRSQ_LAST  +XED_IFORMFL_VMOVRSW_FIRST  +XED_IFORMFL_VMOVRSW_LAST  XED_IFORMFL_VMOVSD_FIRST  XED_IFORMFL_VMOVSD_LAST  XED_IFORMFL_VMOVSH_FIRST  @@ -69437,6 +73823,8 @@

XED_IFORMFL_VMRUN_LAST  XED_IFORMFL_VMSAVE_FIRST  XED_IFORMFL_VMSAVE_LAST  +XED_IFORMFL_VMULNEPBF16_FIRST  +XED_IFORMFL_VMULNEPBF16_LAST  XED_IFORMFL_VMULPD_FIRST  XED_IFORMFL_VMULPD_LAST  XED_IFORMFL_VMULPH_FIRST  @@ -70177,6 +74565,8 @@

XED_IFORMFL_VRCP28SD_LAST  XED_IFORMFL_VRCP28SS_FIRST  XED_IFORMFL_VRCP28SS_LAST  +XED_IFORMFL_VRCPPBF16_FIRST  +XED_IFORMFL_VRCPPBF16_LAST  XED_IFORMFL_VRCPPH_FIRST  XED_IFORMFL_VRCPPH_LAST  XED_IFORMFL_VRCPPS_FIRST  @@ -70185,6 +74575,8 @@

XED_IFORMFL_VRCPSH_LAST  XED_IFORMFL_VRCPSS_FIRST  XED_IFORMFL_VRCPSS_LAST  +XED_IFORMFL_VREDUCENEPBF16_FIRST  +XED_IFORMFL_VREDUCENEPBF16_LAST  XED_IFORMFL_VREDUCEPD_FIRST  XED_IFORMFL_VREDUCEPD_LAST  XED_IFORMFL_VREDUCEPH_FIRST  @@ -70197,6 +74589,8 @@

XED_IFORMFL_VREDUCESH_LAST  XED_IFORMFL_VREDUCESS_FIRST  XED_IFORMFL_VREDUCESS_LAST  +XED_IFORMFL_VRNDSCALENEPBF16_FIRST  +XED_IFORMFL_VRNDSCALENEPBF16_LAST  XED_IFORMFL_VRNDSCALEPD_FIRST  XED_IFORMFL_VRNDSCALEPD_LAST  XED_IFORMFL_VRNDSCALEPH_FIRST  @@ -70233,6 +74627,8 @@

XED_IFORMFL_VRSQRT28SD_LAST  XED_IFORMFL_VRSQRT28SS_FIRST  XED_IFORMFL_VRSQRT28SS_LAST  +XED_IFORMFL_VRSQRTPBF16_FIRST  +XED_IFORMFL_VRSQRTPBF16_LAST  XED_IFORMFL_VRSQRTPH_FIRST  XED_IFORMFL_VRSQRTPH_LAST  XED_IFORMFL_VRSQRTPS_FIRST  @@ -70241,6 +74637,8 @@

XED_IFORMFL_VRSQRTSH_LAST  XED_IFORMFL_VRSQRTSS_FIRST  XED_IFORMFL_VRSQRTSS_LAST  +XED_IFORMFL_VSCALEFPBF16_FIRST  +XED_IFORMFL_VSCALEFPBF16_LAST  XED_IFORMFL_VSCALEFPD_FIRST  XED_IFORMFL_VSCALEFPD_LAST  XED_IFORMFL_VSCALEFPH_FIRST  @@ -70305,6 +74703,8 @@

XED_IFORMFL_VSM4KEY4_LAST  XED_IFORMFL_VSM4RNDS4_FIRST  XED_IFORMFL_VSM4RNDS4_LAST  +XED_IFORMFL_VSQRTNEPBF16_FIRST  +XED_IFORMFL_VSQRTNEPBF16_LAST  XED_IFORMFL_VSQRTPD_FIRST  XED_IFORMFL_VSQRTPD_LAST  XED_IFORMFL_VSQRTPH_FIRST  @@ -70319,6 +74719,8 @@

XED_IFORMFL_VSQRTSS_LAST  XED_IFORMFL_VSTMXCSR_FIRST  XED_IFORMFL_VSTMXCSR_LAST  +XED_IFORMFL_VSUBNEPBF16_FIRST  +XED_IFORMFL_VSUBNEPBF16_LAST  XED_IFORMFL_VSUBPD_FIRST  XED_IFORMFL_VSUBPD_LAST  XED_IFORMFL_VSUBPH_FIRST  @@ -70341,6 +74743,12 @@

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null ], + [ "XED_IFORMFL_VRSQRTPBF16_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36abc950e9af7daca447d7c54bf602fa507", null ], [ "XED_IFORMFL_VRSQRTPH_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36ab7e5a2779edc628563769359ea99133b", null ], [ "XED_IFORMFL_VRSQRTPH_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36aaa4d3b97a37c6ecd652170b34d3bfcfe", null ], [ "XED_IFORMFL_VRSQRTPS_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a71944d34336f7a2685e2bcb31ce9c6df", null ], @@ -7204,6 +7656,8 @@ var xed_iformfl_enum_8h = [ "XED_IFORMFL_VRSQRTSH_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a88461bd2b7500511958056619a4016a6", null ], [ "XED_IFORMFL_VRSQRTSS_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a041c570a6a8b2fa3f1f18e622a6cdabf", null ], [ "XED_IFORMFL_VRSQRTSS_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a493348ac98f308b1d8d199cbd1ce027a", null ], + [ "XED_IFORMFL_VSCALEFPBF16_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a10ba6f141690a96aec11b75ed94c0324", null ], + [ "XED_IFORMFL_VSCALEFPBF16_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a36271c00057fac9c74d5b7a0fd133db6", null ], [ "XED_IFORMFL_VSCALEFPD_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a1bf9c0c65d88b9890a0b99a199bc9b7f", null ], [ "XED_IFORMFL_VSCALEFPD_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a7f83717f55f56483ad0b214298ae2df0", null ], [ "XED_IFORMFL_VSCALEFPH_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36afb4079b0c8851b4071e93ff321587279", null ], @@ -7268,6 +7722,8 @@ var xed_iformfl_enum_8h = [ "XED_IFORMFL_VSM4KEY4_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a59dcc6593d2a7490fc08536150a7e0be", null ], [ "XED_IFORMFL_VSM4RNDS4_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a25cdd975dac50a18f6c70f503dd0f0fc", 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null ], [ "XED_IFORMFL_VSTMXCSR_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36adeb2bc2313a0618c3f77d3ffa1acc9f9", null ], [ "XED_IFORMFL_VSTMXCSR_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a675ef5e0dcf78c8766a220896b74c54c", null ], + [ "XED_IFORMFL_VSUBNEPBF16_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a5bcc6bf70c2919213e407648f1b8bb1f", null ], + [ "XED_IFORMFL_VSUBNEPBF16_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a9c633e7f26a6dbf732b7501cf14cc516", null ], [ "XED_IFORMFL_VSUBPD_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a3fe671c797c8f2e66c4de9468a81e3cd", null ], [ "XED_IFORMFL_VSUBPD_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36ad877a558ecb892c539865b16f3c1fb4c", null ], [ "XED_IFORMFL_VSUBPH_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a3b449759828415624d4067614d09aff7", null ], @@ -7304,6 +7762,12 @@ var xed_iformfl_enum_8h = [ "XED_IFORMFL_VUCOMISH_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a9274a09f947995590bdf6e32d97dd6e0", null ], [ "XED_IFORMFL_VUCOMISS_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36acc7b3fe582c1e82f9eeed19b6909a6fa", null ], [ "XED_IFORMFL_VUCOMISS_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a37b5f3d06973f27b7c85a4a0d66fc02b", null ], + [ "XED_IFORMFL_VUCOMXSD_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a08306e605d26dd8c83eb77f6f7d12342", null ], + [ "XED_IFORMFL_VUCOMXSD_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36acb02357e6649b6d0623b28f1bfdd4b7f", null ], + [ "XED_IFORMFL_VUCOMXSH_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36afb4b8fb60619631aa5e90c0b3b274a6c", null ], + [ "XED_IFORMFL_VUCOMXSH_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36ad6fbe19acc5ff4f9db92281ddfc5185c", null ], + [ "XED_IFORMFL_VUCOMXSS_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a8dcc759316beec00807723c5c3aaa2f1", null ], + [ "XED_IFORMFL_VUCOMXSS_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36af4f3f54a86c91052482b206c6fa81128", null ], [ "XED_IFORMFL_VUNPCKHPD_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a0e32646ef9fe9ea386aa9840fe5e1a1a", null ], [ "XED_IFORMFL_VUNPCKHPD_LAST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36aafa5950978044d0f97129bf349941495", null ], [ "XED_IFORMFL_VUNPCKHPS_FIRST", "xed-iformfl-enum_8h.html#a261aba9f055ef9754e8152bf28debe36a1fb33ef8f7f87b8cc4bdc41da78ab1a9", null ], diff --git a/ref-manual/xed-ild-enum_8h.html b/ref-manual/xed-ild-enum_8h.html index 1d36713..031e97c 100644 --- a/ref-manual/xed-ild-enum_8h.html +++ b/ref-manual/xed-ild-enum_8h.html @@ -133,6 +133,8 @@   #define XED_ILD_VEX_MAP3_DEFINED   1   +#define XED_ILD_VEX_MAP5_DEFINED   1 +  #define XED_ILD_VEX_MAP7_DEFINED   1   @@ -175,6 +177,8 @@
  XED_ILD_VEX_MAP3 =3,
+  XED_ILD_VEX_MAP5 =5, +
  XED_ILD_VEX_MAP7 =7,
  XED_ILD_MAP_INVALID, @@ -475,6 +479,20 @@

+ + + +

◆ XED_ILD_VEX_MAP5_DEFINED

+ +
+
+

+ + + +
#define XED_ILD_VEX_MAP5_DEFINED   1
+
+
@@ -522,6 +540,7 @@

XED_ILD_VEX_MAP1  XED_ILD_VEX_MAP2  XED_ILD_VEX_MAP3  +XED_ILD_VEX_MAP5  XED_ILD_VEX_MAP7  XED_ILD_MAP_INVALID  XED_ILD_LAST  diff --git a/ref-manual/xed-ild-enum_8h.js b/ref-manual/xed-ild-enum_8h.js index db15aa5..e23d4d9 100644 --- a/ref-manual/xed-ild-enum_8h.js +++ b/ref-manual/xed-ild-enum_8h.js @@ -20,6 +20,7 @@ var xed_ild_enum_8h = [ "XED_ILD_VEX_MAP1_DEFINED", "xed-ild-enum_8h.html#aa39be214d759b5346876bb32cf6fb75b", null ], [ "XED_ILD_VEX_MAP2_DEFINED", "xed-ild-enum_8h.html#a820f4b0488c08715d485ed76370a6f8a", null ], [ "XED_ILD_VEX_MAP3_DEFINED", "xed-ild-enum_8h.html#aeab9eaa784b8ae064d5de85a59695b4d", null ], + [ "XED_ILD_VEX_MAP5_DEFINED", "xed-ild-enum_8h.html#afe1cc1832155d2c6ced5994a03d899ef", null ], [ "XED_ILD_VEX_MAP7_DEFINED", "xed-ild-enum_8h.html#a822f3ea9752a884402ae764487657db5", null ], [ "xed_ild_map_enum_t", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772d", [ [ "XED_ILD_AMD_3DNOW", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772da1228937b80806bdd31fac1020610ba28", null ], @@ -40,6 +41,7 @@ var xed_ild_enum_8h = [ "XED_ILD_VEX_MAP1", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772da46c38b585d36bcbdae3a1b66bfb3098d", null ], [ "XED_ILD_VEX_MAP2", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772dabd5c91b37e73a7086d8fb556b85ddd8e", null ], [ "XED_ILD_VEX_MAP3", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772dabb81ecb7b44acf861d976e58dd1647a3", null ], + [ "XED_ILD_VEX_MAP5", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772da791a2e2f989f110f473bb5f5a3821ec0", null ], [ "XED_ILD_VEX_MAP7", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772dae94525246705a16cab5ceb33ac71d6bd", null ], [ "XED_ILD_MAP_INVALID", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772da5a1925bfedeb28184c13b9a96a5357ee", null ], [ "XED_ILD_LAST", "xed-ild-enum_8h.html#a573968bc8cdeb699857acbd9fa0b772da343b62400c222f36b1b4e65d4a7cfc22", null ] diff --git a/ref-manual/xed-init_8h.html b/ref-manual/xed-init_8h.html index 6d5cc67..c892142 100644 --- a/ref-manual/xed-init_8h.html +++ b/ref-manual/xed-init_8h.html @@ -90,8 +90,8 @@ - - + +

Functions

void XED_DLL_EXPORT xed_tables_init (void)
 
XED_DLL_EXPORT void xed_tables_init (void)
 
diff --git a/ref-manual/xed-init_8h.js b/ref-manual/xed-init_8h.js index 12a8fab..977c37d 100644 --- a/ref-manual/xed-init_8h.js +++ b/ref-manual/xed-init_8h.js @@ -1,4 +1,4 @@ var xed_init_8h = [ - [ "xed_tables_init", "group__INIT.html#gacc180d75159533eb63e61611004d4512", null ] + [ "xed_tables_init", "group__INIT.html#ga0fba52fba611ceaf93ace0a236d9cb7c", null ] ]; \ No newline at end of file diff --git a/ref-manual/xed-isa-set-enum_8h.html b/ref-manual/xed-isa-set-enum_8h.html index 52cfb26..f933c1d 100644 --- a/ref-manual/xed-isa-set-enum_8h.html +++ b/ref-manual/xed-isa-set-enum_8h.html @@ -103,16 +103,36 @@   #define XED_ISA_SET_AMD_INVLPGB_DEFINED   1   +#define XED_ISA_SET_AMX_AVX512_DEFINED   1 +  #define XED_ISA_SET_AMX_BF16_DEFINED   1   #define XED_ISA_SET_AMX_COMPLEX_DEFINED   1   #define XED_ISA_SET_AMX_FP16_DEFINED   1   +#define XED_ISA_SET_AMX_FP8_DEFINED   1 +  #define XED_ISA_SET_AMX_INT8_DEFINED   1   +#define XED_ISA_SET_AMX_MOVRS_DEFINED   1 +  +#define XED_ISA_SET_AMX_TF32_DEFINED   1 +  #define XED_ISA_SET_AMX_TILE_DEFINED   1   +#define XED_ISA_SET_AMX_TRANSPOSE_BF16_DEFINED   1 +  +#define XED_ISA_SET_AMX_TRANSPOSE_COMPLEX_DEFINED   1 +  +#define XED_ISA_SET_AMX_TRANSPOSE_DEFINED   1 +  +#define XED_ISA_SET_AMX_TRANSPOSE_FP16_DEFINED   1 +  +#define XED_ISA_SET_AMX_TRANSPOSE_MOVRS_DEFINED   1 +  +#define XED_ISA_SET_AMX_TRANSPOSE_TF32_DEFINED   1 +  #define XED_ISA_SET_APX_F_ADX_DEFINED   1   #define XED_ISA_SET_APX_F_AMX_DEFINED   1 @@ -147,6 +167,8 @@   #define XED_ISA_SET_APX_F_MOVDIRI_DEFINED   1   +#define XED_ISA_SET_APX_F_MSR_IMM_DEFINED   1 +  #define XED_ISA_SET_APX_F_POPCNT_DEFINED   1   #define XED_ISA_SET_APX_F_RAO_INT_DEFINED   1 @@ -155,6 +177,16 @@   #define XED_ISA_SET_APX_F_VMX_DEFINED   1   +#define XED_ISA_SET_AVX10_2_RC_256_DEFINED   1 +  +#define XED_ISA_SET_AVX10_2_RC_SCALAR_DEFINED   1 +  +#define XED_ISA_SET_AVX10_MOVRS_128_DEFINED   1 +  +#define XED_ISA_SET_AVX10_MOVRS_256_DEFINED   1 +  +#define XED_ISA_SET_AVX10_MOVRS_512_DEFINED   1 +  #define XED_ISA_SET_AVX2_DEFINED   1   #define XED_ISA_SET_AVX2GATHER_DEFINED   1 @@ -171,12 +203,22 @@   #define XED_ISA_SET_AVX512_BF16_512_DEFINED   1   +#define XED_ISA_SET_AVX512_BF16_NE_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_BF16_NE_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_BF16_NE_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_BF16_NE_SCALAR_DEFINED   1 +  #define XED_ISA_SET_AVX512_BITALG_128_DEFINED   1   #define XED_ISA_SET_AVX512_BITALG_256_DEFINED   1   #define XED_ISA_SET_AVX512_BITALG_512_DEFINED   1   +#define XED_ISA_SET_AVX512_COM_EF_SCALAR_DEFINED   1 +  #define XED_ISA_SET_AVX512_FP16_128_DEFINED   1   #define XED_ISA_SET_AVX512_FP16_128N_DEFINED   1 @@ -185,6 +227,12 @@   #define XED_ISA_SET_AVX512_FP16_512_DEFINED   1   +#define XED_ISA_SET_AVX512_FP16_CONVERT_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_FP16_CONVERT_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_FP16_CONVERT_512_DEFINED   1 +  #define XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED   1   #define XED_ISA_SET_AVX512_GFNI_128_DEFINED   1 @@ -199,6 +247,42 @@   #define XED_ISA_SET_AVX512_IFMA_512_DEFINED   1   +#define XED_ISA_SET_AVX512_MEDIAX_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MEDIAX_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MEDIAX_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MINMAX_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MINMAX_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MINMAX_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MINMAX_SCALAR_DEFINED   1 +  +#define XED_ISA_SET_AVX512_MOVZXC_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_DS_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_DS_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_DS_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_SAT_CVT_DS_SCALAR_DEFINED   1 +  #define XED_ISA_SET_AVX512_VAES_128_DEFINED   1   #define XED_ISA_SET_AVX512_VAES_256_DEFINED   1 @@ -223,6 +307,24 @@   #define XED_ISA_SET_AVX512_VNNI_512_DEFINED   1   +#define XED_ISA_SET_AVX512_VNNI_FP16_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_FP16_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_FP16_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT16_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT16_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT16_512_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT8_128_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT8_256_DEFINED   1 +  +#define XED_ISA_SET_AVX512_VNNI_INT8_512_DEFINED   1 +  #define XED_ISA_SET_AVX512_VP2INTERSECT_128_DEFINED   1   #define XED_ISA_SET_AVX512_VP2INTERSECT_256_DEFINED   1 @@ -401,8 +503,12 @@   #define XED_ISA_SET_MOVDIRI_DEFINED   1   +#define XED_ISA_SET_MOVRS_DEFINED   1 +  #define XED_ISA_SET_MPX_DEFINED   1   +#define XED_ISA_SET_MSR_IMM_DEFINED   1 +  #define XED_ISA_SET_MSRLIST_DEFINED   1   #define XED_ISA_SET_PAUSE_DEFINED   1 @@ -467,6 +573,12 @@   #define XED_ISA_SET_SM3_DEFINED   1   +#define XED_ISA_SET_SM4_128_DEFINED   1 +  +#define XED_ISA_SET_SM4_256_DEFINED   1 +  +#define XED_ISA_SET_SM4_512_DEFINED   1 +  #define XED_ISA_SET_SM4_DEFINED   1   #define XED_ISA_SET_SMAP_DEFINED   1 @@ -561,16 +673,36 @@
  XED_ISA_SET_AMD_INVLPGB,
+  XED_ISA_SET_AMX_AVX512, +
  XED_ISA_SET_AMX_BF16,
  XED_ISA_SET_AMX_COMPLEX,
  XED_ISA_SET_AMX_FP16,
+  XED_ISA_SET_AMX_FP8, +
  XED_ISA_SET_AMX_INT8,
+  XED_ISA_SET_AMX_MOVRS, +
+  XED_ISA_SET_AMX_TF32, +
  XED_ISA_SET_AMX_TILE,
+  XED_ISA_SET_AMX_TRANSPOSE, +
+  XED_ISA_SET_AMX_TRANSPOSE_BF16, +
+  XED_ISA_SET_AMX_TRANSPOSE_COMPLEX, +
+  XED_ISA_SET_AMX_TRANSPOSE_FP16, +
+  XED_ISA_SET_AMX_TRANSPOSE_MOVRS, +
+  XED_ISA_SET_AMX_TRANSPOSE_TF32, +
  XED_ISA_SET_APX_F,
  XED_ISA_SET_APX_F_ADX, @@ -605,6 +737,8 @@
  XED_ISA_SET_APX_F_MOVDIRI,
+  XED_ISA_SET_APX_F_MSR_IMM, +
  XED_ISA_SET_APX_F_POPCNT,
  XED_ISA_SET_APX_F_RAO_INT, @@ -615,6 +749,16 @@
  XED_ISA_SET_AVX,
+  XED_ISA_SET_AVX10_2_RC_256, +
+  XED_ISA_SET_AVX10_2_RC_SCALAR, +
+  XED_ISA_SET_AVX10_MOVRS_128, +
+  XED_ISA_SET_AVX10_MOVRS_256, +
+  XED_ISA_SET_AVX10_MOVRS_512, +
  XED_ISA_SET_AVX2,
  XED_ISA_SET_AVX2GATHER, @@ -681,12 +825,22 @@
  XED_ISA_SET_AVX512_BF16_512,
+  XED_ISA_SET_AVX512_BF16_NE_128, +
+  XED_ISA_SET_AVX512_BF16_NE_256, +
+  XED_ISA_SET_AVX512_BF16_NE_512, +
+  XED_ISA_SET_AVX512_BF16_NE_SCALAR, +
  XED_ISA_SET_AVX512_BITALG_128,
  XED_ISA_SET_AVX512_BITALG_256,
  XED_ISA_SET_AVX512_BITALG_512,
+  XED_ISA_SET_AVX512_COM_EF_SCALAR, +
  XED_ISA_SET_AVX512_FP16_128,
  XED_ISA_SET_AVX512_FP16_128N, @@ -695,6 +849,12 @@
  XED_ISA_SET_AVX512_FP16_512,
+  XED_ISA_SET_AVX512_FP16_CONVERT_128, +
+  XED_ISA_SET_AVX512_FP16_CONVERT_256, +
+  XED_ISA_SET_AVX512_FP16_CONVERT_512, +
  XED_ISA_SET_AVX512_FP16_SCALAR,
  XED_ISA_SET_AVX512_GFNI_128, @@ -709,6 +869,42 @@
  XED_ISA_SET_AVX512_IFMA_512,
+  XED_ISA_SET_AVX512_MEDIAX_128, +
+  XED_ISA_SET_AVX512_MEDIAX_256, +
+  XED_ISA_SET_AVX512_MEDIAX_512, +
+  XED_ISA_SET_AVX512_MINMAX_128, +
+  XED_ISA_SET_AVX512_MINMAX_256, +
+  XED_ISA_SET_AVX512_MINMAX_512, +
+  XED_ISA_SET_AVX512_MINMAX_SCALAR, +
+  XED_ISA_SET_AVX512_MOVZXC_128, +
+  XED_ISA_SET_AVX512_NE_CONVERT_FP8_128, +
+  XED_ISA_SET_AVX512_NE_CONVERT_FP8_256, +
+  XED_ISA_SET_AVX512_NE_CONVERT_FP8_512, +
+  XED_ISA_SET_AVX512_SAT_CVT_128, +
+  XED_ISA_SET_AVX512_SAT_CVT_256, +
+  XED_ISA_SET_AVX512_SAT_CVT_512, +
+  XED_ISA_SET_AVX512_SAT_CVT_DS_128, +
+  XED_ISA_SET_AVX512_SAT_CVT_DS_256, +
+  XED_ISA_SET_AVX512_SAT_CVT_DS_512, +
+  XED_ISA_SET_AVX512_SAT_CVT_DS_SCALAR, +
  XED_ISA_SET_AVX512_VAES_128,
  XED_ISA_SET_AVX512_VAES_256, @@ -733,6 +929,24 @@
  XED_ISA_SET_AVX512_VNNI_512,
+  XED_ISA_SET_AVX512_VNNI_FP16_128, +
+  XED_ISA_SET_AVX512_VNNI_FP16_256, +
+  XED_ISA_SET_AVX512_VNNI_FP16_512, +
+  XED_ISA_SET_AVX512_VNNI_INT16_128, +
+  XED_ISA_SET_AVX512_VNNI_INT16_256, +
+  XED_ISA_SET_AVX512_VNNI_INT16_512, +
+  XED_ISA_SET_AVX512_VNNI_INT8_128, +
+  XED_ISA_SET_AVX512_VNNI_INT8_256, +
+  XED_ISA_SET_AVX512_VNNI_INT8_512, +
  XED_ISA_SET_AVX512_VP2INTERSECT_128,
  XED_ISA_SET_AVX512_VP2INTERSECT_256, @@ -855,10 +1069,14 @@
  XED_ISA_SET_MOVDIRI,
+  XED_ISA_SET_MOVRS, +
  XED_ISA_SET_MPX,
  XED_ISA_SET_MSRLIST,
+  XED_ISA_SET_MSR_IMM, +
  XED_ISA_SET_PAUSE,
  XED_ISA_SET_PBNDKB, @@ -923,6 +1141,12 @@
  XED_ISA_SET_SM4,
+  XED_ISA_SET_SM4_128, +
+  XED_ISA_SET_SM4_256, +
+  XED_ISA_SET_SM4_512, +
  XED_ISA_SET_SMAP,
  XED_ISA_SET_SMX, @@ -1085,6 +1309,20 @@

+ + + +

◆ XED_ISA_SET_AMX_AVX512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_AVX512_DEFINED   1
+
+
@@ -1127,6 +1365,20 @@

+ + + +

◆ XED_ISA_SET_AMX_FP8_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_FP8_DEFINED   1
+
+
@@ -1141,6 +1393,34 @@

+ + + +

◆ XED_ISA_SET_AMX_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TF32_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TF32_DEFINED   1
+
+
@@ -1155,6 +1435,90 @@

+ + + +

◆ XED_ISA_SET_AMX_TRANSPOSE_BF16_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_BF16_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TRANSPOSE_COMPLEX_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_COMPLEX_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TRANSPOSE_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TRANSPOSE_FP16_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_FP16_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TRANSPOSE_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_MOVRS_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AMX_TRANSPOSE_TF32_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AMX_TRANSPOSE_TF32_DEFINED   1
+
+
@@ -1255,672 +1619,1246 @@

-

◆ XED_ISA_SET_APX_F_ENQCMD_DEFINED

+ +

◆ XED_ISA_SET_APX_F_ENQCMD_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_ENQCMD_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_INVPCID_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_INVPCID_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_KOPB_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_KOPB_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_KOPD_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_KOPD_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_KOPQ_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_KOPQ_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_KOPW_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_KOPW_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_LZCNT_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_LZCNT_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_MOVBE_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_MOVBE_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_MOVDIR64B_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_MOVDIR64B_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_MOVDIRI_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_MOVDIRI_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_MSR_IMM_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_MSR_IMM_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_POPCNT_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_POPCNT_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_RAO_INT_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_RAO_INT_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_USER_MSR_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_USER_MSR_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_APX_F_VMX_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_APX_F_VMX_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX10_2_RC_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX10_2_RC_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX10_2_RC_SCALAR_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX10_2_RC_SCALAR_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX10_MOVRS_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX10_MOVRS_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX10_MOVRS_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX10_MOVRS_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX10_MOVRS_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX10_MOVRS_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX2_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX2_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX2GATHER_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX2GATHER_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_4FMAPS_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_4FMAPS_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_4VNNIW_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_4VNNIW_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_NE_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_NE_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_NE_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_NE_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_NE_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_NE_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BF16_NE_SCALAR_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BF16_NE_SCALAR_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BITALG_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BITALG_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BITALG_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BITALG_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_BITALG_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_BITALG_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_COM_EF_SCALAR_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_COM_EF_SCALAR_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_FP16_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_128N_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_FP16_128N_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_FP16_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_FP16_512_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_CONVERT_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_AVX512_FP16_CONVERT_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_AVX512_FP16_CONVERT_256_DEFINED

- +
#define XED_ISA_SET_APX_F_ENQCMD_DEFINED   1#define XED_ISA_SET_AVX512_FP16_CONVERT_256_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_INVPCID_DEFINED

+ +

◆ XED_ISA_SET_AVX512_FP16_CONVERT_512_DEFINED

- +
#define XED_ISA_SET_APX_F_INVPCID_DEFINED   1#define XED_ISA_SET_AVX512_FP16_CONVERT_512_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_KOPB_DEFINED

+ +

◆ XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED

- +
#define XED_ISA_SET_APX_F_KOPB_DEFINED   1#define XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_KOPD_DEFINED

+ +

◆ XED_ISA_SET_AVX512_GFNI_128_DEFINED

- +
#define XED_ISA_SET_APX_F_KOPD_DEFINED   1#define XED_ISA_SET_AVX512_GFNI_128_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_KOPQ_DEFINED

+ +

◆ XED_ISA_SET_AVX512_GFNI_256_DEFINED

- +
#define XED_ISA_SET_APX_F_KOPQ_DEFINED   1#define XED_ISA_SET_AVX512_GFNI_256_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_KOPW_DEFINED

+ +

◆ XED_ISA_SET_AVX512_GFNI_512_DEFINED

- +
#define XED_ISA_SET_APX_F_KOPW_DEFINED   1#define XED_ISA_SET_AVX512_GFNI_512_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_LZCNT_DEFINED

+ +

◆ XED_ISA_SET_AVX512_IFMA_128_DEFINED

- +
#define XED_ISA_SET_APX_F_LZCNT_DEFINED   1#define XED_ISA_SET_AVX512_IFMA_128_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_MOVBE_DEFINED

+ +

◆ XED_ISA_SET_AVX512_IFMA_256_DEFINED

- +
#define XED_ISA_SET_APX_F_MOVBE_DEFINED   1#define XED_ISA_SET_AVX512_IFMA_256_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_MOVDIR64B_DEFINED

+ +

◆ XED_ISA_SET_AVX512_IFMA_512_DEFINED

- +
#define XED_ISA_SET_APX_F_MOVDIR64B_DEFINED   1#define XED_ISA_SET_AVX512_IFMA_512_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_MOVDIRI_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MEDIAX_128_DEFINED

- +
#define XED_ISA_SET_APX_F_MOVDIRI_DEFINED   1#define XED_ISA_SET_AVX512_MEDIAX_128_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_POPCNT_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MEDIAX_256_DEFINED

- +
#define XED_ISA_SET_APX_F_POPCNT_DEFINED   1#define XED_ISA_SET_AVX512_MEDIAX_256_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_RAO_INT_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MEDIAX_512_DEFINED

- +
#define XED_ISA_SET_APX_F_RAO_INT_DEFINED   1#define XED_ISA_SET_AVX512_MEDIAX_512_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_USER_MSR_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MINMAX_128_DEFINED

- +
#define XED_ISA_SET_APX_F_USER_MSR_DEFINED   1#define XED_ISA_SET_AVX512_MINMAX_128_DEFINED   1
- -

◆ XED_ISA_SET_APX_F_VMX_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MINMAX_256_DEFINED

- +
#define XED_ISA_SET_APX_F_VMX_DEFINED   1#define XED_ISA_SET_AVX512_MINMAX_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX2_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MINMAX_512_DEFINED

- +
#define XED_ISA_SET_AVX2_DEFINED   1#define XED_ISA_SET_AVX512_MINMAX_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX2GATHER_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MINMAX_SCALAR_DEFINED

- +
#define XED_ISA_SET_AVX2GATHER_DEFINED   1#define XED_ISA_SET_AVX512_MINMAX_SCALAR_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_4FMAPS_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_MOVZXC_128_DEFINED

- +
#define XED_ISA_SET_AVX512_4FMAPS_512_DEFINED   1#define XED_ISA_SET_AVX512_MOVZXC_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED

+ +

◆ XED_ISA_SET_AVX512_NE_CONVERT_FP8_128_DEFINED

- +
#define XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED   1#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_4VNNIW_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_NE_CONVERT_FP8_256_DEFINED

- +
#define XED_ISA_SET_AVX512_4VNNIW_512_DEFINED   1#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BF16_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_NE_CONVERT_FP8_512_DEFINED

- +
#define XED_ISA_SET_AVX512_BF16_128_DEFINED   1#define XED_ISA_SET_AVX512_NE_CONVERT_FP8_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BF16_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_128_DEFINED

- +
#define XED_ISA_SET_AVX512_BF16_256_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BF16_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_256_DEFINED

- +
#define XED_ISA_SET_AVX512_BF16_512_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BITALG_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_512_DEFINED

- +
#define XED_ISA_SET_AVX512_BITALG_128_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BITALG_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_DS_128_DEFINED

- +
#define XED_ISA_SET_AVX512_BITALG_256_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_DS_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_BITALG_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_DS_256_DEFINED

- +
#define XED_ISA_SET_AVX512_BITALG_512_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_DS_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_FP16_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_DS_512_DEFINED

- +
#define XED_ISA_SET_AVX512_FP16_128_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_DS_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_FP16_128N_DEFINED

+ +

◆ XED_ISA_SET_AVX512_SAT_CVT_DS_SCALAR_DEFINED

- +
#define XED_ISA_SET_AVX512_FP16_128N_DEFINED   1#define XED_ISA_SET_AVX512_SAT_CVT_DS_SCALAR_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_FP16_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VAES_128_DEFINED

- +
#define XED_ISA_SET_AVX512_FP16_256_DEFINED   1#define XED_ISA_SET_AVX512_VAES_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_FP16_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VAES_256_DEFINED

- +
#define XED_ISA_SET_AVX512_FP16_512_DEFINED   1#define XED_ISA_SET_AVX512_VAES_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VAES_512_DEFINED

- +
#define XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED   1#define XED_ISA_SET_AVX512_VAES_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_GFNI_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI2_128_DEFINED

- +
#define XED_ISA_SET_AVX512_GFNI_128_DEFINED   1#define XED_ISA_SET_AVX512_VBMI2_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_GFNI_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI2_256_DEFINED

- +
#define XED_ISA_SET_AVX512_GFNI_256_DEFINED   1#define XED_ISA_SET_AVX512_VBMI2_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_GFNI_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI2_512_DEFINED

- +
#define XED_ISA_SET_AVX512_GFNI_512_DEFINED   1#define XED_ISA_SET_AVX512_VBMI2_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_IFMA_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI_128_DEFINED

- +
#define XED_ISA_SET_AVX512_IFMA_128_DEFINED   1#define XED_ISA_SET_AVX512_VBMI_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_IFMA_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI_256_DEFINED

- +
#define XED_ISA_SET_AVX512_IFMA_256_DEFINED   1#define XED_ISA_SET_AVX512_VBMI_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_IFMA_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VBMI_512_DEFINED

- +
#define XED_ISA_SET_AVX512_IFMA_512_DEFINED   1#define XED_ISA_SET_AVX512_VBMI_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VAES_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_128_DEFINED

- +
#define XED_ISA_SET_AVX512_VAES_128_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VAES_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_256_DEFINED

- +
#define XED_ISA_SET_AVX512_VAES_256_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VAES_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_512_DEFINED

- +
#define XED_ISA_SET_AVX512_VAES_512_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI2_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_FP16_128_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI2_128_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_FP16_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI2_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_FP16_256_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI2_256_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_FP16_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI2_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_FP16_512_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI2_512_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_FP16_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT16_128_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI_128_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT16_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT16_256_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI_256_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT16_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VBMI_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT16_512_DEFINED

- +
#define XED_ISA_SET_AVX512_VBMI_512_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT16_512_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VNNI_128_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT8_128_DEFINED

- +
#define XED_ISA_SET_AVX512_VNNI_128_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT8_128_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VNNI_256_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT8_256_DEFINED

- +
#define XED_ISA_SET_AVX512_VNNI_256_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT8_256_DEFINED   1
- -

◆ XED_ISA_SET_AVX512_VNNI_512_DEFINED

+ +

◆ XED_ISA_SET_AVX512_VNNI_INT8_512_DEFINED

- +
#define XED_ISA_SET_AVX512_VNNI_512_DEFINED   1#define XED_ISA_SET_AVX512_VNNI_INT8_512_DEFINED   1
@@ -3171,6 +4109,20 @@

+

+
+ +

◆ XED_ISA_SET_MOVRS_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_MOVRS_DEFINED   1
+
+
@@ -3185,6 +4137,20 @@

+ + + +

◆ XED_ISA_SET_MSR_IMM_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_MSR_IMM_DEFINED   1
+
+
@@ -3633,6 +4599,48 @@

+ + + +

◆ XED_ISA_SET_SM4_128_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_SM4_128_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_SM4_256_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_SM4_256_DEFINED   1
+
+ +
+
+ +

◆ XED_ISA_SET_SM4_512_DEFINED

+ +
+
+ + + + +
#define XED_ISA_SET_SM4_512_DEFINED   1
+
+
@@ -4200,11 +5208,21 @@

XED_ISA_SET_AES  XED_ISA_SET_AMD  XED_ISA_SET_AMD_INVLPGB  +XED_ISA_SET_AMX_AVX512  XED_ISA_SET_AMX_BF16  XED_ISA_SET_AMX_COMPLEX  XED_ISA_SET_AMX_FP16  +XED_ISA_SET_AMX_FP8  XED_ISA_SET_AMX_INT8  +XED_ISA_SET_AMX_MOVRS  +XED_ISA_SET_AMX_TF32  XED_ISA_SET_AMX_TILE  +XED_ISA_SET_AMX_TRANSPOSE  +XED_ISA_SET_AMX_TRANSPOSE_BF16  +XED_ISA_SET_AMX_TRANSPOSE_COMPLEX  +XED_ISA_SET_AMX_TRANSPOSE_FP16  +XED_ISA_SET_AMX_TRANSPOSE_MOVRS  +XED_ISA_SET_AMX_TRANSPOSE_TF32  XED_ISA_SET_APX_F  XED_ISA_SET_APX_F_ADX  XED_ISA_SET_APX_F_AMX  @@ -4222,11 +5240,17 @@

XED_ISA_SET_APX_F_MOVBE  XED_ISA_SET_APX_F_MOVDIR64B  XED_ISA_SET_APX_F_MOVDIRI  +XED_ISA_SET_APX_F_MSR_IMM  XED_ISA_SET_APX_F_POPCNT  XED_ISA_SET_APX_F_RAO_INT  XED_ISA_SET_APX_F_USER_MSR  XED_ISA_SET_APX_F_VMX  XED_ISA_SET_AVX  +XED_ISA_SET_AVX10_2_RC_256  +XED_ISA_SET_AVX10_2_RC_SCALAR  +XED_ISA_SET_AVX10_MOVRS_128  +XED_ISA_SET_AVX10_MOVRS_256  +XED_ISA_SET_AVX10_MOVRS_512  XED_ISA_SET_AVX2  XED_ISA_SET_AVX2GATHER  XED_ISA_SET_AVX512BW_128  @@ -4260,13 +5284,21 @@

XED_ISA_SET_AVX512_BF16_128  XED_ISA_SET_AVX512_BF16_256  XED_ISA_SET_AVX512_BF16_512  +XED_ISA_SET_AVX512_BF16_NE_128  +XED_ISA_SET_AVX512_BF16_NE_256  +XED_ISA_SET_AVX512_BF16_NE_512  +XED_ISA_SET_AVX512_BF16_NE_SCALAR  XED_ISA_SET_AVX512_BITALG_128  XED_ISA_SET_AVX512_BITALG_256  XED_ISA_SET_AVX512_BITALG_512  +XED_ISA_SET_AVX512_COM_EF_SCALAR  XED_ISA_SET_AVX512_FP16_128  XED_ISA_SET_AVX512_FP16_128N  XED_ISA_SET_AVX512_FP16_256  XED_ISA_SET_AVX512_FP16_512  +XED_ISA_SET_AVX512_FP16_CONVERT_128  +XED_ISA_SET_AVX512_FP16_CONVERT_256  +XED_ISA_SET_AVX512_FP16_CONVERT_512  XED_ISA_SET_AVX512_FP16_SCALAR  XED_ISA_SET_AVX512_GFNI_128  XED_ISA_SET_AVX512_GFNI_256  @@ -4274,6 +5306,24 @@

XED_ISA_SET_AVX512_IFMA_128  XED_ISA_SET_AVX512_IFMA_256  XED_ISA_SET_AVX512_IFMA_512  +XED_ISA_SET_AVX512_MEDIAX_128  +XED_ISA_SET_AVX512_MEDIAX_256  +XED_ISA_SET_AVX512_MEDIAX_512  +XED_ISA_SET_AVX512_MINMAX_128  +XED_ISA_SET_AVX512_MINMAX_256  +XED_ISA_SET_AVX512_MINMAX_512  +XED_ISA_SET_AVX512_MINMAX_SCALAR  +XED_ISA_SET_AVX512_MOVZXC_128  +XED_ISA_SET_AVX512_NE_CONVERT_FP8_128  +XED_ISA_SET_AVX512_NE_CONVERT_FP8_256  +XED_ISA_SET_AVX512_NE_CONVERT_FP8_512  +XED_ISA_SET_AVX512_SAT_CVT_128  +XED_ISA_SET_AVX512_SAT_CVT_256  +XED_ISA_SET_AVX512_SAT_CVT_512  +XED_ISA_SET_AVX512_SAT_CVT_DS_128  +XED_ISA_SET_AVX512_SAT_CVT_DS_256  +XED_ISA_SET_AVX512_SAT_CVT_DS_512  +XED_ISA_SET_AVX512_SAT_CVT_DS_SCALAR  XED_ISA_SET_AVX512_VAES_128  XED_ISA_SET_AVX512_VAES_256  XED_ISA_SET_AVX512_VAES_512  @@ -4286,6 +5336,15 @@

XED_ISA_SET_AVX512_VNNI_128  XED_ISA_SET_AVX512_VNNI_256  XED_ISA_SET_AVX512_VNNI_512  +XED_ISA_SET_AVX512_VNNI_FP16_128  +XED_ISA_SET_AVX512_VNNI_FP16_256  +XED_ISA_SET_AVX512_VNNI_FP16_512  +XED_ISA_SET_AVX512_VNNI_INT16_128  +XED_ISA_SET_AVX512_VNNI_INT16_256  +XED_ISA_SET_AVX512_VNNI_INT16_512  +XED_ISA_SET_AVX512_VNNI_INT8_128  +XED_ISA_SET_AVX512_VNNI_INT8_256  +XED_ISA_SET_AVX512_VNNI_INT8_512  XED_ISA_SET_AVX512_VP2INTERSECT_128  XED_ISA_SET_AVX512_VP2INTERSECT_256  XED_ISA_SET_AVX512_VP2INTERSECT_512  @@ -4347,8 +5406,10 @@

XED_ISA_SET_MOVBE  XED_ISA_SET_MOVDIR64B  XED_ISA_SET_MOVDIRI  +XED_ISA_SET_MOVRS  XED_ISA_SET_MPX  XED_ISA_SET_MSRLIST  +XED_ISA_SET_MSR_IMM  XED_ISA_SET_PAUSE  XED_ISA_SET_PBNDKB  XED_ISA_SET_PCLMULQDQ  @@ -4381,6 +5442,9 @@

XED_ISA_SET_SHA512  XED_ISA_SET_SM3  XED_ISA_SET_SM4  +XED_ISA_SET_SM4_128  +XED_ISA_SET_SM4_256  +XED_ISA_SET_SM4_512  XED_ISA_SET_SMAP  XED_ISA_SET_SMX  XED_ISA_SET_SNP  diff --git a/ref-manual/xed-isa-set-enum_8h.js b/ref-manual/xed-isa-set-enum_8h.js index 07ac89a..feb3fa0 100644 --- a/ref-manual/xed-isa-set-enum_8h.js +++ b/ref-manual/xed-isa-set-enum_8h.js @@ -5,11 +5,21 @@ var xed_isa_set_enum_8h = [ "XED_ISA_SET_AES_DEFINED", "xed-isa-set-enum_8h.html#aa3c2e93f90bef92fabe5a64d602025a8", null ], [ "XED_ISA_SET_AMD_DEFINED", "xed-isa-set-enum_8h.html#a02069f18dea23e6be32815b04b6a054c", null ], [ "XED_ISA_SET_AMD_INVLPGB_DEFINED", "xed-isa-set-enum_8h.html#a6ce5c6b371093407e01927ab66711352", null ], + [ "XED_ISA_SET_AMX_AVX512_DEFINED", "xed-isa-set-enum_8h.html#a167f56a0a9711f7653357bbc8862ac67", null ], [ "XED_ISA_SET_AMX_BF16_DEFINED", "xed-isa-set-enum_8h.html#a3baedc06f252fe1c85e4a0583b3ab9f8", null ], [ "XED_ISA_SET_AMX_COMPLEX_DEFINED", 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"xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a884018205d3f96ddc0b373c4bb9ef694", null ], + [ "XED_ISA_SET_AVX512_VNNI_INT8_128", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a266fd7db94d7ab66df17439b9fc53283", null ], + [ "XED_ISA_SET_AVX512_VNNI_INT8_256", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a8ff236f75c79fa7cea13440f846c45c0", null ], + [ "XED_ISA_SET_AVX512_VNNI_INT8_512", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681aee1eedef393c5f7ea0999fab6ad1a2a6", null ], [ "XED_ISA_SET_AVX512_VP2INTERSECT_128", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a5387df286635fcffdb1509c19c7174ba", null ], [ "XED_ISA_SET_AVX512_VP2INTERSECT_256", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681aba78fb9c272c26dfecb17a1316e5434c", null ], [ "XED_ISA_SET_AVX512_VP2INTERSECT_512", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a4d1c2f05a8aba60a98db4ee872a6a625", null ], @@ -380,8 +487,10 @@ var xed_isa_set_enum_8h = [ "XED_ISA_SET_MOVBE", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681aa50c0c2fbf4f9bbb6879124bd756011f", null ], [ "XED_ISA_SET_MOVDIR64B", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681afb64b4d5d145f62a015a038deb1d66fa", null ], [ "XED_ISA_SET_MOVDIRI", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681ac45118c9ad73ef6dec4a9c1331827a61", null ], + [ "XED_ISA_SET_MOVRS", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a6d973a5d48c21c135df26bfc0b5ac91f", null ], [ "XED_ISA_SET_MPX", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681afa18e3b6cd3c1c41a828b63e3877cc57", null ], [ "XED_ISA_SET_MSRLIST", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681aeb00904286a33e88b73e4a0fd21d0c9f", null ], + [ "XED_ISA_SET_MSR_IMM", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a73ba68d84682197471fffa50b7a23f55", null ], [ "XED_ISA_SET_PAUSE", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681afb98395618bad43203c4ef14d6e04375", null ], [ "XED_ISA_SET_PBNDKB", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a1caf2c4a5428deeea03ee247caa7abe2", null ], [ "XED_ISA_SET_PCLMULQDQ", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681ae0d00cc9de6169a18a826df9b703847f", null ], @@ -414,6 +523,9 @@ var xed_isa_set_enum_8h = [ "XED_ISA_SET_SHA512", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681ad2d9c4433bb724a3a0d8904b15773603", null ], [ "XED_ISA_SET_SM3", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a074dc5516f668e040a257771987b34e3", null ], [ "XED_ISA_SET_SM4", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681ad605a7040918ec01b43996586abfd636", null ], + [ "XED_ISA_SET_SM4_128", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681aa4a43a97c08c02440cb74c9e3b63e225", null ], + [ "XED_ISA_SET_SM4_256", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a1482e993461d416d5840a396ac96b920", null ], + [ "XED_ISA_SET_SM4_512", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a0a16e46f9af52a115d3ea0167b77243b", null ], [ "XED_ISA_SET_SMAP", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681ab4702464efb481c29c9693fcd6b7e3f9", null ], [ "XED_ISA_SET_SMX", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681afd1a287b6b0c66906a0270e7b4622871", null ], [ "XED_ISA_SET_SNP", "xed-isa-set-enum_8h.html#a4a1095357d6e9552d94418d2bd9f5681a8d8b579e37e32f0e401b752ea1575af4", null ], diff --git a/ref-manual/xed-mapu-enum_8h.html b/ref-manual/xed-mapu-enum_8h.html index c83d0d3..ad23046 100644 --- a/ref-manual/xed-mapu-enum_8h.html +++ b/ref-manual/xed-mapu-enum_8h.html @@ -133,6 +133,8 @@   #define XED_MAPU_VEX_MAP3_DEFINED   1   +#define XED_MAPU_VEX_MAP5_DEFINED   1 +  #define XED_MAPU_VEX_MAP7_DEFINED   1   @@ -177,6 +179,8 @@
  XED_MAPU_VEX_MAP3,
+  XED_MAPU_VEX_MAP5, +
  XED_MAPU_VEX_MAP7,
  XED_MAPU_LAST @@ -475,6 +479,20 @@

+ + + +

◆ XED_MAPU_VEX_MAP5_DEFINED

+ +
+
+

+ + + +
#define XED_MAPU_VEX_MAP5_DEFINED   1
+
+
@@ -523,6 +541,7 @@

XED_MAPU_VEX_MAP1  XED_MAPU_VEX_MAP2  XED_MAPU_VEX_MAP3  +XED_MAPU_VEX_MAP5  XED_MAPU_VEX_MAP7  XED_MAPU_LAST  diff --git a/ref-manual/xed-mapu-enum_8h.js b/ref-manual/xed-mapu-enum_8h.js index 589ef66..c2e5ab8 100644 --- a/ref-manual/xed-mapu-enum_8h.js +++ b/ref-manual/xed-mapu-enum_8h.js @@ -20,6 +20,7 @@ var xed_mapu_enum_8h = [ "XED_MAPU_VEX_MAP1_DEFINED", "xed-mapu-enum_8h.html#a2dcd2279be79692bf89788e7045acb89", null ], [ "XED_MAPU_VEX_MAP2_DEFINED", "xed-mapu-enum_8h.html#a284440b0d85191c1d9fe0a5e68f35216", null ], [ "XED_MAPU_VEX_MAP3_DEFINED", "xed-mapu-enum_8h.html#a2b4af3d1e1baf50c0fa8dd9bb06f9198", null ], + [ "XED_MAPU_VEX_MAP5_DEFINED", "xed-mapu-enum_8h.html#a399e4fb2434618f538854cf91cc16cce", null ], [ "XED_MAPU_VEX_MAP7_DEFINED", "xed-mapu-enum_8h.html#a0b58d6ebb087d38f098f815b89d8797e", null ], [ "xed_mapu_enum_t", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6b", [ [ "XED_MAPU_INVALID", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6ba534419c97d26987706dfed1f57ebd7bb", null ], @@ -41,6 +42,7 @@ var xed_mapu_enum_8h = [ "XED_MAPU_VEX_MAP1", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6ba4fda5710fc50aadb6252b24c07a50159", null ], [ "XED_MAPU_VEX_MAP2", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6baaab8fd7d5836acb6b95979192d5a80ad", null ], [ "XED_MAPU_VEX_MAP3", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6ba123d6eac55ea9af4a2ce1ddfa18bd7f6", null ], + [ "XED_MAPU_VEX_MAP5", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6ba4d412509ea5340550138481babfb66f3", null ], [ "XED_MAPU_VEX_MAP7", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6bac8f87ff55b589923c9143357ed03e4ca", null ], [ "XED_MAPU_LAST", "xed-mapu-enum_8h.html#a4735ecb72821e6c68d4e410db638ba6ba954405caa0e7507eb3b8118789bf7686", null ] ] ], diff --git a/ref-manual/xed-nonterminal-enum_8h.html b/ref-manual/xed-nonterminal-enum_8h.html index 167c265..af52531 100644 --- a/ref-manual/xed-nonterminal-enum_8h.html +++ b/ref-manual/xed-nonterminal-enum_8h.html @@ -163,6 +163,8 @@   #define XED_NONTERMINAL_ASZ_NONTERM_DEFINED   1   +#define XED_NONTERMINAL_AVX256_ROUND_DEFINED   1 +  #define XED_NONTERMINAL_AVX512_ROUND_DEFINED   1   #define XED_NONTERMINAL_AVX_INSTRUCTIONS_DEFINED   1 @@ -255,6 +257,8 @@   #define XED_NONTERMINAL_FIX_ROUND_LEN128_DEFINED   1   +#define XED_NONTERMINAL_FIX_ROUND_LEN256_DEFINED   1 +  #define XED_NONTERMINAL_FIX_ROUND_LEN512_DEFINED   1   #define XED_NONTERMINAL_FORCE64_DEFINED   1 @@ -369,30 +373,6 @@   #define XED_NONTERMINAL_NELEM_FULLMEM_DEFINED   1   -#define XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_READER_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_GSCAT_DEFINED   1 -  #define XED_NONTERMINAL_NELEM_HALF_DEFINED   1   #define XED_NONTERMINAL_NELEM_HALFMEM_DEFINED   1 @@ -401,22 +381,14 @@   #define XED_NONTERMINAL_NELEM_MOVDDUP_DEFINED   1   +#define XED_NONTERMINAL_NELEM_ONE_DEFINED   1 +  #define XED_NONTERMINAL_NELEM_QUARTER_DEFINED   1   #define XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED   1   -#define XED_NONTERMINAL_NELEM_SCALAR_DEFINED   1 -  #define XED_NONTERMINAL_NELEM_TUPLE1_4X_DEFINED   1   -#define XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_TUPLE1_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED   1 -  -#define XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED   1 -  #define XED_NONTERMINAL_NELEM_TUPLE2_DEFINED   1   #define XED_NONTERMINAL_NELEM_TUPLE4_DEFINED   1 @@ -457,6 +429,8 @@   #define XED_NONTERMINAL_RIPA_DEFINED   1   +#define XED_NONTERMINAL_SAE256_DEFINED   1 +  #define XED_NONTERMINAL_SAE_DEFINED   1   #define XED_NONTERMINAL_SE_IMM8_DEFINED   1 @@ -477,6 +451,8 @@   #define XED_NONTERMINAL_SRSP_DEFINED   1   +#define XED_NONTERMINAL_TMM_B3_DEFINED   1 +  #define XED_NONTERMINAL_TMM_B_DEFINED   1   #define XED_NONTERMINAL_TMM_N_DEFINED   1 @@ -737,6 +713,8 @@
  XED_NONTERMINAL_ASZ_NONTERM,
+  XED_NONTERMINAL_AVX256_ROUND, +
  XED_NONTERMINAL_AVX512_ROUND,
  XED_NONTERMINAL_AVX_INSTRUCTIONS, @@ -833,6 +811,8 @@
  XED_NONTERMINAL_FIX_ROUND_LEN128,
+  XED_NONTERMINAL_FIX_ROUND_LEN256, +
  XED_NONTERMINAL_FIX_ROUND_LEN512,
  XED_NONTERMINAL_FORCE64, @@ -943,30 +923,6 @@
  XED_NONTERMINAL_NELEM_FULLMEM,
-  XED_NONTERMINAL_NELEM_GPR_READER, -
-  XED_NONTERMINAL_NELEM_GPR_READER_BYTE, -
-  XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD, -
-  XED_NONTERMINAL_NELEM_GPR_READER_WORD, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_STORE, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD, -
-  XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD, -
-  XED_NONTERMINAL_NELEM_GSCAT, -
  XED_NONTERMINAL_NELEM_HALF,
  XED_NONTERMINAL_NELEM_HALFMEM, @@ -975,22 +931,14 @@
  XED_NONTERMINAL_NELEM_MOVDDUP,
+  XED_NONTERMINAL_NELEM_ONE, +
  XED_NONTERMINAL_NELEM_QUARTER,
  XED_NONTERMINAL_NELEM_QUARTERMEM,
-  XED_NONTERMINAL_NELEM_SCALAR, -
-  XED_NONTERMINAL_NELEM_TUPLE1, -
  XED_NONTERMINAL_NELEM_TUPLE1_4X,
-  XED_NONTERMINAL_NELEM_TUPLE1_BYTE, -
-  XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD, -
-  XED_NONTERMINAL_NELEM_TUPLE1_WORD, -
  XED_NONTERMINAL_NELEM_TUPLE2,
  XED_NONTERMINAL_NELEM_TUPLE4, @@ -1033,6 +981,8 @@
  XED_NONTERMINAL_SAE,
+  XED_NONTERMINAL_SAE256, +
  XED_NONTERMINAL_SEG,
  XED_NONTERMINAL_SEG_MOV, @@ -1053,6 +1003,8 @@
  XED_NONTERMINAL_TMM_B,
+  XED_NONTERMINAL_TMM_B3, +
  XED_NONTERMINAL_TMM_N,
  XED_NONTERMINAL_TMM_R, @@ -1745,6 +1697,20 @@

+ + + +

◆ XED_NONTERMINAL_AVX256_ROUND_DEFINED

+ +
+
+ + + + +
#define XED_NONTERMINAL_AVX256_ROUND_DEFINED   1
+
+
@@ -2389,6 +2355,20 @@

+ + + +

◆ XED_NONTERMINAL_FIX_ROUND_LEN256_DEFINED

+ +
+
+ + + + +
#define XED_NONTERMINAL_FIX_ROUND_LEN256_DEFINED   1
+
+
@@ -3187,174 +3167,6 @@

- - - -

◆ XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_READER_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_READER_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_GSCAT_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_GSCAT_DEFINED   1
-
-
@@ -3413,42 +3225,42 @@

-

◆ XED_NONTERMINAL_NELEM_QUARTER_DEFINED

+ +

◆ XED_NONTERMINAL_NELEM_ONE_DEFINED

- +
#define XED_NONTERMINAL_NELEM_QUARTER_DEFINED   1#define XED_NONTERMINAL_NELEM_ONE_DEFINED   1
- -

◆ XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED

+ +

◆ XED_NONTERMINAL_NELEM_QUARTER_DEFINED

- +
#define XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED   1#define XED_NONTERMINAL_NELEM_QUARTER_DEFINED   1
- -

◆ XED_NONTERMINAL_NELEM_SCALAR_DEFINED

+ +

◆ XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED

- +
#define XED_NONTERMINAL_NELEM_SCALAR_DEFINED   1#define XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED   1
@@ -3467,62 +3279,6 @@

-

-
- -

◆ XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_TUPLE1_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_TUPLE1_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED   1
-
- -
-
- -

◆ XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED

- -
-
- - - - -
#define XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED   1
-
-
@@ -3803,6 +3559,20 @@

+ + + +

◆ XED_NONTERMINAL_SAE256_DEFINED

+ +
+
+ + + + +
#define XED_NONTERMINAL_SAE256_DEFINED   1
+
+
@@ -3943,6 +3713,20 @@

+ + + +

◆ XED_NONTERMINAL_TMM_B3_DEFINED

+ +
+
+ + + + +
#define XED_NONTERMINAL_TMM_B3_DEFINED   1
+
+
@@ -5308,6 +5092,7 @@

XED_NONTERMINAL_ARSI  XED_NONTERMINAL_ARSP  XED_NONTERMINAL_ASZ_NONTERM  +XED_NONTERMINAL_AVX256_ROUND  XED_NONTERMINAL_AVX512_ROUND  XED_NONTERMINAL_AVX_INSTRUCTIONS  XED_NONTERMINAL_AVX_SPLITTER  @@ -5356,6 +5141,7 @@

XED_NONTERMINAL_FINAL_SSEG_MODE64  XED_NONTERMINAL_FINAL_SSEG_NOT64  XED_NONTERMINAL_FIX_ROUND_LEN128  +XED_NONTERMINAL_FIX_ROUND_LEN256  XED_NONTERMINAL_FIX_ROUND_LEN512  XED_NONTERMINAL_FORCE64  XED_NONTERMINAL_GPR16_B  @@ -5411,30 +5197,14 @@

XED_NONTERMINAL_NELEM_EIGHTHMEM  XED_NONTERMINAL_NELEM_FULL  XED_NONTERMINAL_NELEM_FULLMEM  -XED_NONTERMINAL_NELEM_GPR_READER  -XED_NONTERMINAL_NELEM_GPR_READER_BYTE  -XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD  -XED_NONTERMINAL_NELEM_GPR_READER_WORD  -XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP  -XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D  -XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q  -XED_NONTERMINAL_NELEM_GPR_WRITER_STORE  -XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE  -XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD  -XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD  -XED_NONTERMINAL_NELEM_GSCAT  XED_NONTERMINAL_NELEM_HALF  XED_NONTERMINAL_NELEM_HALFMEM  XED_NONTERMINAL_NELEM_MEM128  XED_NONTERMINAL_NELEM_MOVDDUP  +XED_NONTERMINAL_NELEM_ONE  XED_NONTERMINAL_NELEM_QUARTER  XED_NONTERMINAL_NELEM_QUARTERMEM  -XED_NONTERMINAL_NELEM_SCALAR  -XED_NONTERMINAL_NELEM_TUPLE1  XED_NONTERMINAL_NELEM_TUPLE1_4X  -XED_NONTERMINAL_NELEM_TUPLE1_BYTE  -XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD  -XED_NONTERMINAL_NELEM_TUPLE1_WORD  XED_NONTERMINAL_NELEM_TUPLE2  XED_NONTERMINAL_NELEM_TUPLE4  XED_NONTERMINAL_NELEM_TUPLE8  @@ -5456,6 +5226,7 @@

XED_NONTERMINAL_RIP  XED_NONTERMINAL_RIPA  XED_NONTERMINAL_SAE  +XED_NONTERMINAL_SAE256  XED_NONTERMINAL_SEG  XED_NONTERMINAL_SEG_MOV  XED_NONTERMINAL_SE_IMM8  @@ -5466,6 +5237,7 @@

XED_NONTERMINAL_SRBP  XED_NONTERMINAL_SRSP  XED_NONTERMINAL_TMM_B  +XED_NONTERMINAL_TMM_B3  XED_NONTERMINAL_TMM_N  XED_NONTERMINAL_TMM_R  XED_NONTERMINAL_TMM_R3  diff --git a/ref-manual/xed-nonterminal-enum_8h.js b/ref-manual/xed-nonterminal-enum_8h.js index d63a62e..a2c24df 100644 --- a/ref-manual/xed-nonterminal-enum_8h.js +++ b/ref-manual/xed-nonterminal-enum_8h.js @@ -35,6 +35,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_ARSI_DEFINED", "xed-nonterminal-enum_8h.html#a00a5df48a3ce028beac37e074a08318b", null ], [ "XED_NONTERMINAL_ARSP_DEFINED", "xed-nonterminal-enum_8h.html#ac4ed2d8fe71cf3571646eb51d4941693", null ], [ "XED_NONTERMINAL_ASZ_NONTERM_DEFINED", "xed-nonterminal-enum_8h.html#a367918b60d09f7eec2572e40811d0279", null ], + [ "XED_NONTERMINAL_AVX256_ROUND_DEFINED", "xed-nonterminal-enum_8h.html#a75b909c1d5a4d5535f19da0395da8e46", null ], [ "XED_NONTERMINAL_AVX512_ROUND_DEFINED", "xed-nonterminal-enum_8h.html#a1cf631dc3f50008487ca46af9fc39be3", null ], [ "XED_NONTERMINAL_AVX_INSTRUCTIONS_DEFINED", "xed-nonterminal-enum_8h.html#abb23076b7b9f4785136c7eacada06035", null ], [ "XED_NONTERMINAL_AVX_SPLITTER_DEFINED", "xed-nonterminal-enum_8h.html#aaf690c7374438e0c15ba7e47d452cc4d", null ], @@ -81,6 +82,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_FINAL_SSEG_MODE64_DEFINED", "xed-nonterminal-enum_8h.html#a3dab5bfc947719ee7c685f85db074d79", null ], [ "XED_NONTERMINAL_FINAL_SSEG_NOT64_DEFINED", "xed-nonterminal-enum_8h.html#aec8e4cc551caa752cf4d353f57e42792", null ], [ "XED_NONTERMINAL_FIX_ROUND_LEN128_DEFINED", "xed-nonterminal-enum_8h.html#aa3d42600bb24f6807d530fc8eca6aec1", null ], + [ "XED_NONTERMINAL_FIX_ROUND_LEN256_DEFINED", "xed-nonterminal-enum_8h.html#a92e86dd68b9a2f088d1c98dabc7d7d63", null ], [ "XED_NONTERMINAL_FIX_ROUND_LEN512_DEFINED", "xed-nonterminal-enum_8h.html#a2f91426184d5c9fb804708ca465d1227", null ], [ "XED_NONTERMINAL_FORCE64_DEFINED", "xed-nonterminal-enum_8h.html#a12b4fd3b4699e233a7358cd763ea7144", null ], [ "XED_NONTERMINAL_GPR16_B_DEFINED", "xed-nonterminal-enum_8h.html#a229a7514e9445d4351dcd9686c4a5071", null ], @@ -138,30 +140,14 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_NELEM_EIGHTHMEM_DEFINED", "xed-nonterminal-enum_8h.html#a77c7a3e55d39748d67e8562f62f300a9", null ], [ "XED_NONTERMINAL_NELEM_FULL_DEFINED", "xed-nonterminal-enum_8h.html#a5c69aa00b59434ca3defd8cb65c160d4", null ], [ "XED_NONTERMINAL_NELEM_FULLMEM_DEFINED", "xed-nonterminal-enum_8h.html#ab50668ed3258b8e34001501717b16e11", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED", "xed-nonterminal-enum_8h.html#a4542700b4dc73dc0c60e5b90189e4a65", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_DEFINED", "xed-nonterminal-enum_8h.html#a873f4f75f76ae6a3034de1a457efdadc", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED", "xed-nonterminal-enum_8h.html#a20cd4b94559d8a82d24bf398fc52848c", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED", "xed-nonterminal-enum_8h.html#a837e5f8cb34de111781e61b48e0d361a", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED", "xed-nonterminal-enum_8h.html#aa33eb03b3103669016a533b6088c288d", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED", "xed-nonterminal-enum_8h.html#ab3ed42487259cddf9a732d24c1a66e67", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED", "xed-nonterminal-enum_8h.html#a0dbb39a2ad68458d555935d1934be030", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED", "xed-nonterminal-enum_8h.html#ab6cf668ab17137bf28e5979ef4668050", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED", "xed-nonterminal-enum_8h.html#a61d97dc1ac8cd7dfa3faddb3758203a0", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED", "xed-nonterminal-enum_8h.html#a1d8f7693e6791611094c2a0dd4eb0f61", null ], - [ "XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED", "xed-nonterminal-enum_8h.html#a1a87fa46d923c7610a28cfe5af1c9af9", null ], - [ "XED_NONTERMINAL_NELEM_GSCAT_DEFINED", "xed-nonterminal-enum_8h.html#a0f1f0d4b2e4bbe245f71845e8ea4612f", null ], [ "XED_NONTERMINAL_NELEM_HALF_DEFINED", "xed-nonterminal-enum_8h.html#a795f143120c783e4d2d0dede76404750", null ], [ "XED_NONTERMINAL_NELEM_HALFMEM_DEFINED", "xed-nonterminal-enum_8h.html#ae2cb759f15f9c475e23d1c35928bcc98", null ], [ "XED_NONTERMINAL_NELEM_MEM128_DEFINED", "xed-nonterminal-enum_8h.html#ab215d10fc4b9a08130b96e60100772a3", null ], [ "XED_NONTERMINAL_NELEM_MOVDDUP_DEFINED", "xed-nonterminal-enum_8h.html#aa0a3d438f53f099f34d3b1fa144a4fe1", null ], + [ "XED_NONTERMINAL_NELEM_ONE_DEFINED", "xed-nonterminal-enum_8h.html#ab3f7304ce7013a07f4d8182358493be8", null ], [ "XED_NONTERMINAL_NELEM_QUARTER_DEFINED", "xed-nonterminal-enum_8h.html#ad1db99e0d2309fe9f898caba9d1b3f72", null ], [ "XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED", "xed-nonterminal-enum_8h.html#a4d4c82cf9569ffae79b71655e56a5c43", null ], - [ "XED_NONTERMINAL_NELEM_SCALAR_DEFINED", "xed-nonterminal-enum_8h.html#aca7c4e68c18ed8ff051088e69d530241", null ], [ "XED_NONTERMINAL_NELEM_TUPLE1_4X_DEFINED", "xed-nonterminal-enum_8h.html#a0080e2f25a08e1bdb36ad222bab5657c", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED", "xed-nonterminal-enum_8h.html#a530ce146f6b7fee6c6693e4778539410", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_DEFINED", "xed-nonterminal-enum_8h.html#a6635d58a7ebde5a413ea6b7494ac5d3d", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED", "xed-nonterminal-enum_8h.html#aa7bd260685dbe7e9fbdfd11f7b9aed1c", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED", "xed-nonterminal-enum_8h.html#a57fbd1cb87a93bf7b818c049eb63a8f8", null ], [ "XED_NONTERMINAL_NELEM_TUPLE2_DEFINED", "xed-nonterminal-enum_8h.html#ae79db9c09390c5ec8bc54163c153d0cc", null ], [ "XED_NONTERMINAL_NELEM_TUPLE4_DEFINED", "xed-nonterminal-enum_8h.html#ac9e0a38bb368cb55ba41040c4bd4e871", null ], [ "XED_NONTERMINAL_NELEM_TUPLE8_DEFINED", "xed-nonterminal-enum_8h.html#a73f63675011d73b1045024245bc1e974", null ], @@ -182,6 +168,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_RFLAGS_DEFINED", "xed-nonterminal-enum_8h.html#ace0c5a1bb8f78a751cff4383e17238ab", null ], [ "XED_NONTERMINAL_RIP_DEFINED", "xed-nonterminal-enum_8h.html#ac5f394950a67f9a7c2773d297ee3928a", null ], [ "XED_NONTERMINAL_RIPA_DEFINED", "xed-nonterminal-enum_8h.html#aad85c01113caacecb222942ffb0e6670", null ], + [ "XED_NONTERMINAL_SAE256_DEFINED", "xed-nonterminal-enum_8h.html#a28a894817bebb3c457d03a15e04d774d", null ], [ "XED_NONTERMINAL_SAE_DEFINED", "xed-nonterminal-enum_8h.html#ae1445d8004f0115670da2c38f48b1f30", null ], [ "XED_NONTERMINAL_SE_IMM8_DEFINED", "xed-nonterminal-enum_8h.html#af8308da31b342125ee6277989da39cf6", null ], [ "XED_NONTERMINAL_SEG_DEFINED", "xed-nonterminal-enum_8h.html#ae76303808cc452c681d02de730b86c2c", null ], @@ -192,6 +179,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_SIMMZ_DEFINED", "xed-nonterminal-enum_8h.html#ab80a41f2f3fac38e26c7ec85a7e0bd6c", null ], [ "XED_NONTERMINAL_SRBP_DEFINED", "xed-nonterminal-enum_8h.html#a4e31d3c1fa240913a766c18a82dc136e", null ], [ "XED_NONTERMINAL_SRSP_DEFINED", "xed-nonterminal-enum_8h.html#a372c6b798dc5550f15fb17afb3f8de98", null ], + [ "XED_NONTERMINAL_TMM_B3_DEFINED", "xed-nonterminal-enum_8h.html#adae5634d0264ee7617460d1751d3d0cd", null ], [ "XED_NONTERMINAL_TMM_B_DEFINED", "xed-nonterminal-enum_8h.html#a0de1f96928e9af7881c98761a6dbfca9", null ], [ "XED_NONTERMINAL_TMM_N_DEFINED", "xed-nonterminal-enum_8h.html#ad361da1e6e93f9c4bb7cfd7b774dac70", null ], [ "XED_NONTERMINAL_TMM_R3_DEFINED", "xed-nonterminal-enum_8h.html#ac91281a2440e1ee536b5cc8a93661dc6", null ], @@ -321,6 +309,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_ARSI", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaa2b39ccb4ed78f22e1ad87fc5badea84", null ], [ "XED_NONTERMINAL_ARSP", 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xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_NELEM_EIGHTHMEM", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa9224b76da14e6df470566d41658d01b1", null ], [ "XED_NONTERMINAL_NELEM_FULL", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afab386aa1596fe198007a274324dd424b9", null ], [ "XED_NONTERMINAL_NELEM_FULLMEM", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa9452ea5a4d2c3f68ac8a1300a5ad2554", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afabb05c7d68079274228e55e29d5236b72", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_BYTE", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaee15faa53e0e00097b76ef734a1ae845", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa5727fd7040bed87173519b763c0fd170", null ], - [ "XED_NONTERMINAL_NELEM_GPR_READER_WORD", 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"XED_NONTERMINAL_NELEM_ONE", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa57da0e1b94e8850348c24738564ce9fe", null ], [ "XED_NONTERMINAL_NELEM_QUARTER", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa8b3079621f900de8e7031b3bef350a47", null ], [ "XED_NONTERMINAL_NELEM_QUARTERMEM", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaa685ca2fce832ad071b2bd73f639299b", null ], - [ "XED_NONTERMINAL_NELEM_SCALAR", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa7c308f9dbc8a0718849ac887497982e3", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaf7f57ea91361e45d2dc8eb73d7931704", null ], [ "XED_NONTERMINAL_NELEM_TUPLE1_4X", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa0a3cba698e8bc732432248100605eb7e", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_BYTE", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afad7b0b7d42b6255d19f331e31f5a32ddf", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa41e18ff54f73d4740afa0cd1508a450c", null ], - [ "XED_NONTERMINAL_NELEM_TUPLE1_WORD", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa8d1c90ddd143d8894f427996b11449c9", null ], [ "XED_NONTERMINAL_NELEM_TUPLE2", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa01a24d3027e848900b584b977a2c6203", null ], [ "XED_NONTERMINAL_NELEM_TUPLE4", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaf905deb9e41aa4f01309d04e804c01a2", null ], [ "XED_NONTERMINAL_NELEM_TUPLE8", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa704662ca930bed3f4e58592ed1f1003c", null ], @@ -469,6 +443,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_RIP", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa41f88a7299659cdf1b63baeefd320260", null ], [ "XED_NONTERMINAL_RIPA", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaf02a4d2a06bb536b5f02a13639653562", null ], [ "XED_NONTERMINAL_SAE", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa61d35a90dd00571fd870ca7b5892dc2c", null ], + [ "XED_NONTERMINAL_SAE256", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afad87b396a8321d176d47fc561ee5cadd9", null ], [ "XED_NONTERMINAL_SEG", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa555d9858907eedc2d3789e038b359284", null ], [ "XED_NONTERMINAL_SEG_MOV", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afaa445ac33a08aa31554dd25b3962d9b29", null ], [ "XED_NONTERMINAL_SE_IMM8", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa601381268ac4d96e50c3ceee25778b67", null ], @@ -479,6 +454,7 @@ var xed_nonterminal_enum_8h = [ "XED_NONTERMINAL_SRBP", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa4f1e53a0e2d1e084a22c9843faade57c", null ], [ "XED_NONTERMINAL_SRSP", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa9675bf5e74ac0b1d829c9632841affd2", null ], [ "XED_NONTERMINAL_TMM_B", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afabf09f55a9e04db6d6d2a32fe71e26c0c", null ], + [ "XED_NONTERMINAL_TMM_B3", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa9e9c43669cdc2ad47f09f04bcc77d5d6", null ], [ "XED_NONTERMINAL_TMM_N", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa4ed2e8af0eae861b5465ef7bd4e69f88", null ], [ "XED_NONTERMINAL_TMM_R", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa5a6982fabc9a3661a71e6ee89a83ad1f", null ], [ "XED_NONTERMINAL_TMM_R3", "xed-nonterminal-enum_8h.html#ae0eb8f71a8f89cddf0df4b1a6a2b27afa4d307274335cce3d8fe78c70b68be31e", null ], diff --git a/ref-manual/xed-operand-element-type-enum_8h.html b/ref-manual/xed-operand-element-type-enum_8h.html index 67fdeac..a69eb5b 100644 --- a/ref-manual/xed-operand-element-type-enum_8h.html +++ b/ref-manual/xed-operand-element-type-enum_8h.html @@ -95,10 +95,16 @@ Macros

#define XED_OPERAND_ELEMENT_TYPE_BFLOAT16_DEFINED   1   +#define XED_OPERAND_ELEMENT_TYPE_BFLOAT8_DEFINED   1 +  #define XED_OPERAND_ELEMENT_TYPE_DOUBLE_DEFINED   1   #define XED_OPERAND_ELEMENT_TYPE_FLOAT16_DEFINED   1   +#define XED_OPERAND_ELEMENT_TYPE_FLOAT8_DEFINED   1 +  +#define XED_OPERAND_ELEMENT_TYPE_HFLOAT8_DEFINED   1 +  #define XED_OPERAND_ELEMENT_TYPE_INT8_DEFINED   1   #define XED_OPERAND_ELEMENT_TYPE_INT_DEFINED   1 @@ -147,6 +153,12 @@
  XED_OPERAND_ELEMENT_TYPE_BFLOAT16,
+  XED_OPERAND_ELEMENT_TYPE_BFLOAT8, +
+  XED_OPERAND_ELEMENT_TYPE_FLOAT8, +
+  XED_OPERAND_ELEMENT_TYPE_HFLOAT8, +
  XED_OPERAND_ELEMENT_TYPE_INT8,
  XED_OPERAND_ELEMENT_TYPE_UINT8, @@ -181,6 +193,20 @@

+ + + +

◆ XED_OPERAND_ELEMENT_TYPE_BFLOAT8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_ELEMENT_TYPE_BFLOAT8_DEFINED   1
+
+
@@ -209,6 +235,34 @@

+ + + +

◆ XED_OPERAND_ELEMENT_TYPE_FLOAT8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_ELEMENT_TYPE_FLOAT8_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_ELEMENT_TYPE_HFLOAT8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_ELEMENT_TYPE_HFLOAT8_DEFINED   1
+
+
@@ -399,6 +453,12 @@

XED_OPERAND_ELEMENT_TYPE_BFLOAT16 

bfloat16 floating point

+XED_OPERAND_ELEMENT_TYPE_BFLOAT8 

bfloat8 floating point

+ +XED_OPERAND_ELEMENT_TYPE_FLOAT8 

float8 floating point

+ +XED_OPERAND_ELEMENT_TYPE_HFLOAT8 

hybrid float8

+ XED_OPERAND_ELEMENT_TYPE_INT8 

8 bit integer

XED_OPERAND_ELEMENT_TYPE_UINT8 

8 bit unsigned integer

diff --git a/ref-manual/xed-operand-element-type-enum_8h.js b/ref-manual/xed-operand-element-type-enum_8h.js index dee2be4..d730852 100644 --- a/ref-manual/xed-operand-element-type-enum_8h.js +++ b/ref-manual/xed-operand-element-type-enum_8h.js @@ -1,8 +1,11 @@ var xed_operand_element_type_enum_8h = [ [ "XED_OPERAND_ELEMENT_TYPE_BFLOAT16_DEFINED", "xed-operand-element-type-enum_8h.html#a605d3d866ef14a129f5e41b965d457ea", null ], + [ "XED_OPERAND_ELEMENT_TYPE_BFLOAT8_DEFINED", "xed-operand-element-type-enum_8h.html#a607534aded8fe79807dbcf2c1a811544", null ], [ "XED_OPERAND_ELEMENT_TYPE_DOUBLE_DEFINED", "xed-operand-element-type-enum_8h.html#ae8c7a51d5a8d529fce6549d9f924f537", null ], [ "XED_OPERAND_ELEMENT_TYPE_FLOAT16_DEFINED", "xed-operand-element-type-enum_8h.html#ae23167448fe9c9a9de2e3d84cb9e0a89", null ], + [ "XED_OPERAND_ELEMENT_TYPE_FLOAT8_DEFINED", "xed-operand-element-type-enum_8h.html#a377bb319bb3f1359a279f4ac0bcf1914", null ], + [ "XED_OPERAND_ELEMENT_TYPE_HFLOAT8_DEFINED", "xed-operand-element-type-enum_8h.html#aeb1d88b825431ef2e571a894b8789887", null ], [ "XED_OPERAND_ELEMENT_TYPE_INT8_DEFINED", "xed-operand-element-type-enum_8h.html#a6ebdbdda070c44f419a285a6144e3615", null ], [ "XED_OPERAND_ELEMENT_TYPE_INT_DEFINED", "xed-operand-element-type-enum_8h.html#addfdf70704ad2e2a605b56347764c614", null ], [ "XED_OPERAND_ELEMENT_TYPE_INVALID_DEFINED", "xed-operand-element-type-enum_8h.html#a2de5cc078552bb3742d35d5b7dd7b35a", null ], @@ -26,6 +29,9 @@ var xed_operand_element_type_enum_8h = [ "XED_OPERAND_ELEMENT_TYPE_VARIABLE", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5ae91732a43e1ab1830b63bcb01c3ce6d1", null ], [ "XED_OPERAND_ELEMENT_TYPE_FLOAT16", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5afff623b411920b0dd8d53fe5439901b0", null ], [ "XED_OPERAND_ELEMENT_TYPE_BFLOAT16", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5a9f17a539e8cbcded20825d5e65cafc67", null ], + [ "XED_OPERAND_ELEMENT_TYPE_BFLOAT8", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5a15ef7834b026d16f7634abb2c1225f60", null ], + [ "XED_OPERAND_ELEMENT_TYPE_FLOAT8", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5a9a4cfc342817126f503417cb99b5aa0c", null ], + [ "XED_OPERAND_ELEMENT_TYPE_HFLOAT8", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5ae11af1ce6bc457e3f000aa791b66f6d7", null ], [ "XED_OPERAND_ELEMENT_TYPE_INT8", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5a65c513b782b4b1926be1e28c1dd14342", null ], [ "XED_OPERAND_ELEMENT_TYPE_UINT8", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5a86f475e7d469d5c35d299632d9008adc", null ], [ "XED_OPERAND_ELEMENT_TYPE_LAST", "xed-operand-element-type-enum_8h.html#a6942f19fe2b1943a9a98d6598ff2c9d5ad54ac5f4faa48b32f7e5d4ba0879c803", null ] diff --git a/ref-manual/xed-operand-element-xtype-enum_8h.html b/ref-manual/xed-operand-element-xtype-enum_8h.html index 2e2139e..4d87d51 100644 --- a/ref-manual/xed-operand-element-xtype-enum_8h.html +++ b/ref-manual/xed-operand-element-xtype-enum_8h.html @@ -95,12 +95,22 @@ Macros

#define XED_OPERAND_XTYPE_2BF16_DEFINED   1   +#define XED_OPERAND_XTYPE_2BF8_DEFINED   1 +  #define XED_OPERAND_XTYPE_2F16_DEFINED   1   +#define XED_OPERAND_XTYPE_2HF8_DEFINED   1 +  #define XED_OPERAND_XTYPE_2I16_DEFINED   1   +#define XED_OPERAND_XTYPE_2I8_DEFINED   1 +  #define XED_OPERAND_XTYPE_2U16_DEFINED   1   +#define XED_OPERAND_XTYPE_4BF8_DEFINED   1 +  +#define XED_OPERAND_XTYPE_4HF8_DEFINED   1 +  #define XED_OPERAND_XTYPE_4I8_DEFINED   1   #define XED_OPERAND_XTYPE_4U8_DEFINED   1 @@ -109,6 +119,8 @@   #define XED_OPERAND_XTYPE_BF16_DEFINED   1   +#define XED_OPERAND_XTYPE_BF8_DEFINED   1 +  #define XED_OPERAND_XTYPE_F16_DEFINED   1   #define XED_OPERAND_XTYPE_F32_DEFINED   1 @@ -117,6 +129,8 @@   #define XED_OPERAND_XTYPE_F80_DEFINED   1   +#define XED_OPERAND_XTYPE_HF8_DEFINED   1 +  #define XED_OPERAND_XTYPE_I128_DEFINED   1   #define XED_OPERAND_XTYPE_I16_DEFINED   1 @@ -161,12 +175,22 @@
  XED_OPERAND_XTYPE_2BF16,
+  XED_OPERAND_XTYPE_2BF8, +
  XED_OPERAND_XTYPE_2F16,
+  XED_OPERAND_XTYPE_2HF8, +
  XED_OPERAND_XTYPE_2I16,
+  XED_OPERAND_XTYPE_2I8, +
  XED_OPERAND_XTYPE_2U16,
+  XED_OPERAND_XTYPE_4BF8, +
+  XED_OPERAND_XTYPE_4HF8, +
  XED_OPERAND_XTYPE_4I8,
  XED_OPERAND_XTYPE_4U8, @@ -175,6 +199,8 @@
  XED_OPERAND_XTYPE_BF16,
+  XED_OPERAND_XTYPE_BF8, +
  XED_OPERAND_XTYPE_F16,
  XED_OPERAND_XTYPE_F32, @@ -183,6 +209,8 @@
  XED_OPERAND_XTYPE_F80,
+  XED_OPERAND_XTYPE_HF8, +
  XED_OPERAND_XTYPE_I1,
  XED_OPERAND_XTYPE_I128, @@ -245,6 +273,20 @@

+ + + +

◆ XED_OPERAND_XTYPE_2BF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_2BF8_DEFINED   1
+
+
@@ -259,6 +301,20 @@

+ + + +

◆ XED_OPERAND_XTYPE_2HF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_2HF8_DEFINED   1
+
+
@@ -273,6 +329,20 @@

+ + + +

◆ XED_OPERAND_XTYPE_2I8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_2I8_DEFINED   1
+
+
@@ -287,6 +357,34 @@

+ + + +

◆ XED_OPERAND_XTYPE_4BF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_4BF8_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_XTYPE_4HF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_4HF8_DEFINED   1
+
+
@@ -343,6 +441,20 @@

+ + + +

◆ XED_OPERAND_XTYPE_BF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_BF8_DEFINED   1
+
+
@@ -399,6 +511,20 @@

+ + + +

◆ XED_OPERAND_XTYPE_HF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_XTYPE_HF8_DEFINED   1
+
+
@@ -668,17 +794,24 @@

EnumeratorXED_OPERAND_XTYPE_INVALID  XED_OPERAND_XTYPE_2BF16  +XED_OPERAND_XTYPE_2BF8  XED_OPERAND_XTYPE_2F16  +XED_OPERAND_XTYPE_2HF8  XED_OPERAND_XTYPE_2I16  +XED_OPERAND_XTYPE_2I8  XED_OPERAND_XTYPE_2U16  +XED_OPERAND_XTYPE_4BF8  +XED_OPERAND_XTYPE_4HF8  XED_OPERAND_XTYPE_4I8  XED_OPERAND_XTYPE_4U8  XED_OPERAND_XTYPE_B80  XED_OPERAND_XTYPE_BF16  +XED_OPERAND_XTYPE_BF8  XED_OPERAND_XTYPE_F16  XED_OPERAND_XTYPE_F32  XED_OPERAND_XTYPE_F64  XED_OPERAND_XTYPE_F80  +XED_OPERAND_XTYPE_HF8  XED_OPERAND_XTYPE_I1  XED_OPERAND_XTYPE_I128  XED_OPERAND_XTYPE_I16  diff --git a/ref-manual/xed-operand-element-xtype-enum_8h.js b/ref-manual/xed-operand-element-xtype-enum_8h.js index 15048e4..0141073 100644 --- a/ref-manual/xed-operand-element-xtype-enum_8h.js +++ b/ref-manual/xed-operand-element-xtype-enum_8h.js @@ -1,17 +1,24 @@ var xed_operand_element_xtype_enum_8h = [ [ "XED_OPERAND_XTYPE_2BF16_DEFINED", "xed-operand-element-xtype-enum_8h.html#af7cae62c38b95b9b89e34bb5a3fa8eac", null ], + [ "XED_OPERAND_XTYPE_2BF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a64a49b033b25274e15358f0ca8c2d828", null ], [ "XED_OPERAND_XTYPE_2F16_DEFINED", "xed-operand-element-xtype-enum_8h.html#a7a9128f98db258919d4b0558545ee18a", null ], + [ "XED_OPERAND_XTYPE_2HF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a23e339be20be7f18a420a09e2a8df9aa", null ], [ "XED_OPERAND_XTYPE_2I16_DEFINED", "xed-operand-element-xtype-enum_8h.html#ad9ae0ed8620a3a29e04e07f88b08d9b9", null ], + [ "XED_OPERAND_XTYPE_2I8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a52b3d6737bcef4c23dc113a061e5774c", null ], [ "XED_OPERAND_XTYPE_2U16_DEFINED", "xed-operand-element-xtype-enum_8h.html#a290d63bc0661d0167c824cd2f28166eb", null ], + [ "XED_OPERAND_XTYPE_4BF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#aafff2e55c177d01c7f5f1578bed6cdcb", null ], + [ "XED_OPERAND_XTYPE_4HF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a83f43fc2a67f9136bde90c4226b88661", null ], [ "XED_OPERAND_XTYPE_4I8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a18ec49740aa763ef6c06a08013078b10", null ], [ "XED_OPERAND_XTYPE_4U8_DEFINED", "xed-operand-element-xtype-enum_8h.html#a19137526b59455378bfc79c9856bc07c", null ], [ "XED_OPERAND_XTYPE_B80_DEFINED", "xed-operand-element-xtype-enum_8h.html#aabf8fa0038fa40af828a63262709fc62", null ], [ "XED_OPERAND_XTYPE_BF16_DEFINED", "xed-operand-element-xtype-enum_8h.html#ae4bf43020cf974e4ee25fbb67b03b9e7", null ], + [ "XED_OPERAND_XTYPE_BF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#af376abc0c5ef7ab2ed2647071d3cb539", null ], [ "XED_OPERAND_XTYPE_F16_DEFINED", "xed-operand-element-xtype-enum_8h.html#a6f04abc5a5ec32a188f0c6310599b2c6", null ], [ "XED_OPERAND_XTYPE_F32_DEFINED", "xed-operand-element-xtype-enum_8h.html#a6d1c11ae60cec37299788fdadacd5a15", null ], [ "XED_OPERAND_XTYPE_F64_DEFINED", "xed-operand-element-xtype-enum_8h.html#a3753da30f212420fda63dc71c7a7cc64", null ], [ "XED_OPERAND_XTYPE_F80_DEFINED", "xed-operand-element-xtype-enum_8h.html#a3398f539b64f7cf7829b4cbdb814c457", null ], + [ "XED_OPERAND_XTYPE_HF8_DEFINED", "xed-operand-element-xtype-enum_8h.html#ab41e15ddcffcf1503dafd0a07c5ab191", null ], [ "XED_OPERAND_XTYPE_I128_DEFINED", "xed-operand-element-xtype-enum_8h.html#ae9e136d5748e26971e900325f3969c4f", null ], [ "XED_OPERAND_XTYPE_I16_DEFINED", "xed-operand-element-xtype-enum_8h.html#a4198397104b3a906c7a95b8c6c839783", null ], [ "XED_OPERAND_XTYPE_I1_DEFINED", "xed-operand-element-xtype-enum_8h.html#a4655cee0649810d22f2d1ffb4c452e37", null ], @@ -33,17 +40,24 @@ var xed_operand_element_xtype_enum_8h = [ "xed_operand_element_xtype_enum_t", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413", [ [ "XED_OPERAND_XTYPE_INVALID", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413aa6716d05dbc35d0e384739bf1a7e09b0", null ], [ "XED_OPERAND_XTYPE_2BF16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a616868c44a7b3ac971f051676b1ecc18", null ], + [ "XED_OPERAND_XTYPE_2BF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a2c080ff54d9e5c53c70f07f1b3b136c3", null ], [ "XED_OPERAND_XTYPE_2F16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a13b0211ad80028a03983ef2f5db25a05", null ], + [ "XED_OPERAND_XTYPE_2HF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a35205292cd3b9e073d6c20dfe16ce670", null ], [ "XED_OPERAND_XTYPE_2I16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a4214f6f5b7d42210108e3d9529fe2bec", null ], + [ "XED_OPERAND_XTYPE_2I8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a1892d5fdd6ec50aa1651b0554561e441", null ], [ "XED_OPERAND_XTYPE_2U16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a86c40bcfb458b8fabe225ffea38170e2", null ], + [ "XED_OPERAND_XTYPE_4BF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a3f8657b5b8b9080cfd38eca30d56d419", null ], + [ "XED_OPERAND_XTYPE_4HF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413aef91a165366505e3375c4e49101b5b78", null ], [ "XED_OPERAND_XTYPE_4I8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413ab7a6edefc9b8e2c7633c67776bb5046a", null ], [ "XED_OPERAND_XTYPE_4U8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a717cd6723350fd3f2400a672c1e98297", null ], [ "XED_OPERAND_XTYPE_B80", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a466d64664df90d2eb5a7a29d535f4abe", null ], [ "XED_OPERAND_XTYPE_BF16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a029a21d5108e2a12f342e66091a59bc7", null ], + [ "XED_OPERAND_XTYPE_BF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a1cf00f3524649dcdef56b7cf552c743d", null ], [ "XED_OPERAND_XTYPE_F16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a46fab1cca84fcf362af8b79b2b0f2198", null ], [ "XED_OPERAND_XTYPE_F32", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a50e38169ae7cc86f8a5c33c7eead5ded", null ], [ "XED_OPERAND_XTYPE_F64", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413af85243fa9edb3a2c364f48490fb198fe", null ], [ "XED_OPERAND_XTYPE_F80", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a49607544525ae37e9bba8b2013569a64", null ], + [ "XED_OPERAND_XTYPE_HF8", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a5e22b56ad595c7d2719942d2d10b6f81", null ], [ "XED_OPERAND_XTYPE_I1", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a3dc280bc527efbd15d4235f466ebf889", null ], [ "XED_OPERAND_XTYPE_I128", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a21b23642e29edcabd25c0f5dedfedfd2", null ], [ "XED_OPERAND_XTYPE_I16", "xed-operand-element-xtype-enum_8h.html#a2df598e1a20ef98a15d7b1f8f844c413a3e43c0a0f0cf3221a93b70911d19c9d5", null ], diff --git a/ref-manual/xed-operand-values-interface_8h.html b/ref-manual/xed-operand-values-interface_8h.html index 8753431..1bbaeb9 100644 --- a/ref-manual/xed-operand-values-interface_8h.html +++ b/ref-manual/xed-operand-values-interface_8h.html @@ -144,8 +144,6 @@   XED_DLL_EXPORT xed_bool_t xed_operand_values_has_branch_displacement (const xed_operand_values_t *p)   -XED_DLL_EXPORT xed_bool_t xed_operand_values_has_disp (const xed_operand_values_t *p) -  XED_DLL_EXPORT xed_bool_t xed_operand_values_has_displacement (const xed_operand_values_t *p)   XED_DLL_EXPORT xed_bool_t xed_operand_values_has_immediate (const xed_operand_values_t *p) @@ -160,8 +158,6 @@   XED_DLL_EXPORT xed_bool_t xed_operand_values_has_segment_prefix (const xed_operand_values_t *p)   -XED_DLL_EXPORT xed_bool_t xed_operand_values_is_prefetch (const xed_operand_values_t *p) -  XED_DLL_EXPORT xed_bool_t xed_operand_values_lockable (const xed_operand_values_t *p)   XED_DLL_EXPORT xed_bool_t xed_operand_values_mandatory_66_prefix (const xed_operand_values_t *p) @@ -194,6 +190,10 @@   XED_DLL_EXPORT xed_bool_t xed_operand_values_has_sib_byte (const xed_operand_values_t *p)   +xed_bool_t xed_operand_values_ignored_branch_not_taken_hint (const xed_operand_values_t *p) +  +xed_bool_t xed_operand_values_ignored_branch_taken_hint (const xed_operand_values_t *p) +  XED_DLL_EXPORT xed_bool_t xed_operand_values_is_nop (const xed_operand_values_t *p)   XED_DLL_EXPORT xed_bool_t xed_operand_values_memop_without_modrm (const xed_operand_values_t *p) diff --git a/ref-manual/xed-operand-values-interface_8h.js b/ref-manual/xed-operand-values-interface_8h.js index 5ebbc96..989fc4f 100644 --- a/ref-manual/xed-operand-values-interface_8h.js +++ b/ref-manual/xed-operand-values-interface_8h.js @@ -38,7 +38,6 @@ var xed_operand_values_interface_8h = [ "xed_operand_values_has_66_prefix", "group__OPERANDS.html#gab0dbe428e16fea4d11c2498ce23eb489", null ], [ "xed_operand_values_has_address_size_prefix", "group__OPERANDS.html#gae3a5a7fec6f106c2f00029920cc5fa27", null ], [ "xed_operand_values_has_branch_displacement", "group__OPERANDS.html#ga4ad34793ee0b41476c742182fa625caa", null ], - [ "xed_operand_values_has_disp", "group__OPERANDS.html#gab0d49de82df18773d120efd1b5facb96", null ], [ "xed_operand_values_has_displacement", "group__OPERANDS.html#ga35cc443e8ea463cfe087ed5ad3287de5", null ], [ "xed_operand_values_has_immediate", "group__OPERANDS.html#ga7be044800ef408c7043e7c443c8c9702", null ], [ "xed_operand_values_has_lock_prefix", "group__OPERANDS.html#gaa2538c59d88956f3eb10a67ee935f468", null ], @@ -51,11 +50,12 @@ var xed_operand_values_interface_8h = [ "xed_operand_values_has_rexw_prefix", "group__OPERANDS.html#gaf2906d60081b02aa491198720295dae4", null ], [ "xed_operand_values_has_segment_prefix", "group__OPERANDS.html#ga83152cba3e67d2753d01bff505012c6e", null ], [ "xed_operand_values_has_sib_byte", "group__OPERANDS.html#ga87e7a1bf6ad7fc739d57334c60da30f3", null ], + [ "xed_operand_values_ignored_branch_not_taken_hint", "group__OPERANDS.html#ga5ad363d31f2bb56a184e050f9d726574", null ], + [ "xed_operand_values_ignored_branch_taken_hint", "group__OPERANDS.html#ga2a003fcb55418bbb7bab8936fcb56237", null ], [ "xed_operand_values_init", "group__OPERANDS.html#ga5b6cd7ad6c5c853c8ae1179df71fe6d1", null ], [ "xed_operand_values_init_keep_mode", "group__OPERANDS.html#gae001db086cdf4d03d81301448133bbb1", null ], [ "xed_operand_values_init_set_mode", "group__OPERANDS.html#ga6eb60207e9dc46671fc89b83c10071aa", null ], [ "xed_operand_values_is_nop", "group__OPERANDS.html#ga1e19112db73aea4cb91a8682cf7c1dac", null ], - [ "xed_operand_values_is_prefetch", "group__OPERANDS.html#gaf1b7e94aa1e7bc4a75d707d31ca66254", null ], [ "xed_operand_values_lockable", "group__OPERANDS.html#gad6f0386f64431371591ce8c6cb914e7f", null ], [ "xed_operand_values_mandatory_66_prefix", "group__OPERANDS.html#ga8447fdb1d49250e5a38ac9dd5b62e75f", null ], [ "xed_operand_values_memop_without_modrm", "group__OPERANDS.html#ga85403c1bc57896f0cc1f0c5d9abd2274", null ], diff --git a/ref-manual/xed-operand-width-enum_8h.html b/ref-manual/xed-operand-width-enum_8h.html index 2d05340..fc90702 100644 --- a/ref-manual/xed-operand-width-enum_8h.html +++ b/ref-manual/xed-operand-width-enum_8h.html @@ -303,12 +303,24 @@   #define XED_OPERAND_WIDTH_Z2F16_DEFINED   1   +#define XED_OPERAND_WIDTH_Z2I16_DEFINED   1 +  +#define XED_OPERAND_WIDTH_Z2I8_DEFINED   1 +  +#define XED_OPERAND_WIDTH_Z2U16_DEFINED   1 +  +#define XED_OPERAND_WIDTH_Z4I8_DEFINED   1 +  +#define XED_OPERAND_WIDTH_Z4U8_DEFINED   1 +  #define XED_OPERAND_WIDTH_Z_DEFINED   1   #define XED_OPERAND_WIDTH_ZB_DEFINED   1   #define XED_OPERAND_WIDTH_ZBF16_DEFINED   1   +#define XED_OPERAND_WIDTH_ZBF8_DEFINED   1 +  #define XED_OPERAND_WIDTH_ZD0_DEFINED   1   #define XED_OPERAND_WIDTH_ZD_DEFINED   1 @@ -319,6 +331,8 @@   #define XED_OPERAND_WIDTH_ZF64_DEFINED   1   +#define XED_OPERAND_WIDTH_ZHF8_DEFINED   1 +  #define XED_OPERAND_WIDTH_ZI16_DEFINED   1   #define XED_OPERAND_WIDTH_ZI32_DEFINED   1 @@ -615,6 +629,20 @@
  XED_OPERAND_WIDTH_ZD0,
+  XED_OPERAND_WIDTH_Z2I16, +
+  XED_OPERAND_WIDTH_Z2U16, +
+  XED_OPERAND_WIDTH_ZHF8, +
+  XED_OPERAND_WIDTH_ZBF8, +
+  XED_OPERAND_WIDTH_Z4U8, +
+  XED_OPERAND_WIDTH_Z4I8, +
+  XED_OPERAND_WIDTH_Z2I8, +
  XED_OPERAND_WIDTH_LAST
} @@ -2101,6 +2129,76 @@

+ + + +

◆ XED_OPERAND_WIDTH_Z2I16_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_Z2I16_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_WIDTH_Z2I8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_Z2I8_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_WIDTH_Z2U16_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_Z2U16_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_WIDTH_Z4I8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_Z4I8_DEFINED   1
+
+ +
+
+ +

◆ XED_OPERAND_WIDTH_Z4U8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_Z4U8_DEFINED   1
+
+
@@ -2143,6 +2241,20 @@

+ + + +

◆ XED_OPERAND_WIDTH_ZBF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_ZBF8_DEFINED   1
+
+
@@ -2213,6 +2325,20 @@

+ + + +

◆ XED_OPERAND_WIDTH_ZHF8_DEFINED

+ +
+
+ + + + +
#define XED_OPERAND_WIDTH_ZHF8_DEFINED   1
+
+
@@ -2595,6 +2721,13 @@

XED_OPERAND_WIDTH_Z2F16  XED_OPERAND_WIDTH_YU  XED_OPERAND_WIDTH_ZD0  +XED_OPERAND_WIDTH_Z2I16  +XED_OPERAND_WIDTH_Z2U16  +XED_OPERAND_WIDTH_ZHF8  +XED_OPERAND_WIDTH_ZBF8  +XED_OPERAND_WIDTH_Z4U8  +XED_OPERAND_WIDTH_Z4I8  +XED_OPERAND_WIDTH_Z2I8  XED_OPERAND_WIDTH_LAST  diff --git a/ref-manual/xed-operand-width-enum_8h.js b/ref-manual/xed-operand-width-enum_8h.js index 1b93c4e..63adcf9 100644 --- a/ref-manual/xed-operand-width-enum_8h.js +++ b/ref-manual/xed-operand-width-enum_8h.js @@ -105,14 +105,21 @@ var xed_operand_width_enum_8h = [ "XED_OPERAND_WIDTH_YUW_DEFINED", "xed-operand-width-enum_8h.html#aa731ab5dbf36c43bb14917236de766db", null ], [ "XED_OPERAND_WIDTH_YW_DEFINED", "xed-operand-width-enum_8h.html#aef519cb3c950bc3931c8645fd433f2a8", null ], [ "XED_OPERAND_WIDTH_Z2F16_DEFINED", "xed-operand-width-enum_8h.html#a8a346a5e73bd0384e4ca83f55ba39c42", null ], + [ "XED_OPERAND_WIDTH_Z2I16_DEFINED", "xed-operand-width-enum_8h.html#a8a053273ec9806d9bd70af0941cc673c", null ], + [ "XED_OPERAND_WIDTH_Z2I8_DEFINED", "xed-operand-width-enum_8h.html#a8149f2e618de99f1babbcf0fd730c723", null ], + [ "XED_OPERAND_WIDTH_Z2U16_DEFINED", "xed-operand-width-enum_8h.html#a0226f24c56d26827f30e925ab32b0ff4", null ], + [ "XED_OPERAND_WIDTH_Z4I8_DEFINED", "xed-operand-width-enum_8h.html#a5d31323d519d26bc0692ff5a6c71d5f8", null ], + [ "XED_OPERAND_WIDTH_Z4U8_DEFINED", "xed-operand-width-enum_8h.html#a46ec8d33821462252c95c72b8789f742", null ], [ "XED_OPERAND_WIDTH_Z_DEFINED", "xed-operand-width-enum_8h.html#a7c7067ce51fbeeb7c70a0ca7bc7b4734", null ], [ "XED_OPERAND_WIDTH_ZB_DEFINED", "xed-operand-width-enum_8h.html#af72cbcb875e134b1325c3406311c59e8", null ], [ "XED_OPERAND_WIDTH_ZBF16_DEFINED", "xed-operand-width-enum_8h.html#aefdff1e1629746a7a2a249dbbe1310ad", null ], + [ "XED_OPERAND_WIDTH_ZBF8_DEFINED", "xed-operand-width-enum_8h.html#a13a180a2a297ceee24d82f2b07541999", null ], [ "XED_OPERAND_WIDTH_ZD0_DEFINED", "xed-operand-width-enum_8h.html#a236eb49d12bc13b5a05d22516b93d201", null ], [ "XED_OPERAND_WIDTH_ZD_DEFINED", "xed-operand-width-enum_8h.html#abdb6cf08c57e8fc2bb8edbb406deea0e", null ], [ "XED_OPERAND_WIDTH_ZF16_DEFINED", "xed-operand-width-enum_8h.html#a8ae5e52c8ed6b163e5fefbff7e48750a", null ], [ "XED_OPERAND_WIDTH_ZF32_DEFINED", "xed-operand-width-enum_8h.html#a6bc43ecbc68d86f224226c5442a79124", null ], [ "XED_OPERAND_WIDTH_ZF64_DEFINED", "xed-operand-width-enum_8h.html#a8a75573c9d0456572357855a6a89a51a", null ], + [ "XED_OPERAND_WIDTH_ZHF8_DEFINED", "xed-operand-width-enum_8h.html#a5bc5051d2b652b1b06b236541da475c9", null ], [ "XED_OPERAND_WIDTH_ZI16_DEFINED", "xed-operand-width-enum_8h.html#a9b0cbaeee80b3eec9803e88f63d975d9", null ], [ "XED_OPERAND_WIDTH_ZI32_DEFINED", "xed-operand-width-enum_8h.html#a06187aa609bac9678724a596e52d1cdb", null ], [ "XED_OPERAND_WIDTH_ZI64_DEFINED", "xed-operand-width-enum_8h.html#a5022e6aef1f9d78b90dafb4b41bbf3e4", null ], @@ -260,6 +267,13 @@ var xed_operand_width_enum_8h = [ "XED_OPERAND_WIDTH_Z2F16", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676ada145f11de41863cdd0c20b3b76caa29", null ], [ "XED_OPERAND_WIDTH_YU", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676aa7ccb54d5d9080009e1324a620bb921e", null ], [ "XED_OPERAND_WIDTH_ZD0", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676aa5a3a96e5fd374f7dc0e40244e59d35b", null ], + [ "XED_OPERAND_WIDTH_Z2I16", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a3003a01025ffe25aea9c7c11cd8bfc67", null ], + [ "XED_OPERAND_WIDTH_Z2U16", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676adbfd9c748ead7cf7043f7797cd073481", null ], + [ "XED_OPERAND_WIDTH_ZHF8", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a3621c38c5b742188b22d0ecddf1c7d76", null ], + [ "XED_OPERAND_WIDTH_ZBF8", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a788fbb94cd93619fc320ab9d8dd00ef3", null ], + [ "XED_OPERAND_WIDTH_Z4U8", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a269170634d0ffb7662fa559c9847a821", null ], + [ "XED_OPERAND_WIDTH_Z4I8", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a8654301d174b728177b6b2aa2e7987f9", null ], + [ "XED_OPERAND_WIDTH_Z2I8", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a3cb0bcbb8724e5a06d2562b3ab3ef9a4", null ], [ "XED_OPERAND_WIDTH_LAST", "xed-operand-width-enum_8h.html#a4bc2ed96b8433c06c363d614a2fa1676a61fadbaa8155dbd2544f8170e1802b23", null ] ] ], [ "str2xed_operand_width_enum_t", "group__ENUM.html#ga0924246b32d361e6c996ce1fe103abf3", null ], diff --git a/ref-manual/xed-reg-enum_8h.html b/ref-manual/xed-reg-enum_8h.html index 244f8f1..44e1858 100644 --- a/ref-manual/xed-reg-enum_8h.html +++ b/ref-manual/xed-reg-enum_8h.html @@ -1343,8 +1343,6 @@
  XED_REG_TILECONFIG,
-  XED_REG_IA32_KERNEL_GS_BASE, -
  XED_REG_DFV0,
  XED_REG_DFV1, @@ -1377,6 +1375,8 @@
  XED_REG_DFV15,
+  XED_REG_IA32_KERNEL_GS_BASE, +
  XED_REG_X87CONTROL,
  XED_REG_X87STATUS, @@ -1743,7 +1743,7 @@
  XED_REG_PSEUDO_FIRST =XED_REG_STACKPUSH,
-  XED_REG_PSEUDO_LAST =XED_REG_DFV15, +  XED_REG_PSEUDO_LAST =XED_REG_IA32_KERNEL_GS_BASE,
  XED_REG_PSEUDOX87_FIRST =XED_REG_X87CONTROL,
@@ -7923,7 +7923,6 @@

XED_REG_FSBASE  XED_REG_GSBASE  XED_REG_TILECONFIG  -XED_REG_IA32_KERNEL_GS_BASE  XED_REG_DFV0  XED_REG_DFV1  XED_REG_DFV2  @@ -7940,6 +7939,7 @@

XED_REG_DFV13  XED_REG_DFV14  XED_REG_DFV15  +XED_REG_IA32_KERNEL_GS_BASE  XED_REG_X87CONTROL  XED_REG_X87STATUS  XED_REG_X87TAG  diff --git a/ref-manual/xed-reg-enum_8h.js b/ref-manual/xed-reg-enum_8h.js index f15aa4e..639b9b4 100644 --- a/ref-manual/xed-reg-enum_8h.js +++ b/ref-manual/xed-reg-enum_8h.js @@ -624,7 +624,6 @@ var xed_reg_enum_8h = [ "XED_REG_FSBASE", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a964f6af2bc8d22bce7a2ac7bf3b8e100", null ], [ "XED_REG_GSBASE", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a091a1d5a538f1a143d598c498466e314", null ], [ "XED_REG_TILECONFIG", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61aec333803672d4f9317198faa16535df6", null ], - [ "XED_REG_IA32_KERNEL_GS_BASE", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61adbf23c905b7f860b98ea29d210a9b6f7", null ], [ "XED_REG_DFV0", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a31c7fe3bdde476ffb225ad22ccc908c4", null ], [ "XED_REG_DFV1", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a938b999ccdad087e4c93f226ae7a3c59", null ], [ "XED_REG_DFV2", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61ae62fe5968d32b9107f807adafa98b759", null ], @@ -641,6 +640,7 @@ var xed_reg_enum_8h = [ "XED_REG_DFV13", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61ab19546620a31cc19848482982cc0c8c8", null ], [ "XED_REG_DFV14", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61ae2fb9c47d6a7658fb56ba0b72c609fc0", null ], [ "XED_REG_DFV15", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a109eabcc1d98f57fe4e17cf5c09b278f", null ], + [ "XED_REG_IA32_KERNEL_GS_BASE", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61adbf23c905b7f860b98ea29d210a9b6f7", null ], [ "XED_REG_X87CONTROL", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61a85e9380a781b38209b6ea7e616ccd872", null ], [ "XED_REG_X87STATUS", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61aa2bcad2140c60812654e2a46e380c2e9", null ], [ "XED_REG_X87TAG", "xed-reg-enum_8h.html#af05c33c5a68e9304d1d8ac0408ae3f61abe1498274f6c478a81f4009e2dbd8afa", null ],