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[RISCV] When using vror.vi for left rotate, mask the inverted immediate to SEW.
This makes the assembly more readable. Reviewed By: luke Differential Revision: https://reviews.llvm.org/D156348
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-20
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‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -269,7 +269,20 @@ defm : VPatUnarySDNode_V<ctpop, "PseudoVCPOP">;
269269

270270
defm : VPatBinarySDNode_VV_VX<rotl, "PseudoVROL">;
271271

272-
def NegImm64 : SDNodeXForm<imm, [{
272+
// Invert the immediate and mask it to SEW for readability.
273+
def InvRot8Imm : SDNodeXForm<imm, [{
274+
return CurDAG->getTargetConstant(0x7 & (64 - N->getZExtValue()), SDLoc(N),
275+
N->getValueType(0));
276+
}]>;
277+
def InvRot16Imm : SDNodeXForm<imm, [{
278+
return CurDAG->getTargetConstant(0xf & (64 - N->getZExtValue()), SDLoc(N),
279+
N->getValueType(0));
280+
}]>;
281+
def InvRot32Imm : SDNodeXForm<imm, [{
282+
return CurDAG->getTargetConstant(0x1f & (64 - N->getZExtValue()), SDLoc(N),
283+
N->getValueType(0));
284+
}]>;
285+
def InvRot64Imm : SDNodeXForm<imm, [{
273286
return CurDAG->getTargetConstant(0x3f & (64 - N->getZExtValue()), SDLoc(N),
274287
N->getValueType(0));
275288
}]>;
@@ -284,7 +297,7 @@ foreach vti = AllIntegerVectors in {
284297
(!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX)
285298
(vti.Vector (IMPLICIT_DEF)),
286299
vti.RegClass:$rs2,
287-
(NegImm64 uimm6:$rs1),
300+
(!cast<SDNodeXForm>("InvRot" # vti.SEW # "Imm") uimm6:$rs1),
288301
vti.AVL, vti.Log2SEW, TA_MA)>;
289302
}
290303
}

‎llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ define <vscale x 1 x i8> @vror_vi_rotl_nxv1i8(<vscale x 1 x i8> %a) {
8282
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i8:
8383
; CHECK-ZVBB: # %bb.0:
8484
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
85-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
85+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
8686
; CHECK-ZVBB-NEXT: ret
8787
%x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> shufflevector(<vscale x 1 x i8> insertelement(<vscale x 1 x i8> poison, i8 1, i32 0), <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer))
8888
ret <vscale x 1 x i8> %x
@@ -166,7 +166,7 @@ define <vscale x 2 x i8> @vror_vi_rotl_nxv2i8(<vscale x 2 x i8> %a) {
166166
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i8:
167167
; CHECK-ZVBB: # %bb.0:
168168
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
169-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
169+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
170170
; CHECK-ZVBB-NEXT: ret
171171
%x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> shufflevector(<vscale x 2 x i8> insertelement(<vscale x 2 x i8> poison, i8 1, i32 0), <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer))
172172
ret <vscale x 2 x i8> %x
@@ -250,7 +250,7 @@ define <vscale x 4 x i8> @vror_vi_rotl_nxv4i8(<vscale x 4 x i8> %a) {
250250
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i8:
251251
; CHECK-ZVBB: # %bb.0:
252252
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
253-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
253+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
254254
; CHECK-ZVBB-NEXT: ret
255255
%x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> shufflevector(<vscale x 4 x i8> insertelement(<vscale x 4 x i8> poison, i8 1, i32 0), <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer))
256256
ret <vscale x 4 x i8> %x
@@ -334,7 +334,7 @@ define <vscale x 8 x i8> @vror_vi_rotl_nxv8i8(<vscale x 8 x i8> %a) {
334334
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i8:
335335
; CHECK-ZVBB: # %bb.0:
336336
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
337-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
337+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
338338
; CHECK-ZVBB-NEXT: ret
339339
%x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> shufflevector(<vscale x 8 x i8> insertelement(<vscale x 8 x i8> poison, i8 1, i32 0), <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer))
340340
ret <vscale x 8 x i8> %x
@@ -418,7 +418,7 @@ define <vscale x 16 x i8> @vror_vi_rotl_nxv16i8(<vscale x 16 x i8> %a) {
418418
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i8:
419419
; CHECK-ZVBB: # %bb.0:
420420
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
421-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
421+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
422422
; CHECK-ZVBB-NEXT: ret
423423
%x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> shufflevector(<vscale x 16 x i8> insertelement(<vscale x 16 x i8> poison, i8 1, i32 0), <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer))
424424
ret <vscale x 16 x i8> %x
@@ -502,7 +502,7 @@ define <vscale x 32 x i8> @vror_vi_rotl_nxv32i8(<vscale x 32 x i8> %a) {
502502
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv32i8:
503503
; CHECK-ZVBB: # %bb.0:
504504
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
505-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
505+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
506506
; CHECK-ZVBB-NEXT: ret
507507
%x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> shufflevector(<vscale x 32 x i8> insertelement(<vscale x 32 x i8> poison, i8 1, i32 0), <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer))
508508
ret <vscale x 32 x i8> %x
@@ -586,7 +586,7 @@ define <vscale x 64 x i8> @vror_vi_rotl_nxv64i8(<vscale x 64 x i8> %a) {
586586
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv64i8:
587587
; CHECK-ZVBB: # %bb.0:
588588
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
589-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
589+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 7
590590
; CHECK-ZVBB-NEXT: ret
591591
%x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> shufflevector(<vscale x 64 x i8> insertelement(<vscale x 64 x i8> poison, i8 1, i32 0), <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer))
592592
ret <vscale x 64 x i8> %x
@@ -670,7 +670,7 @@ define <vscale x 1 x i16> @vror_vi_rotl_nxv1i16(<vscale x 1 x i16> %a) {
670670
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i16:
671671
; CHECK-ZVBB: # %bb.0:
672672
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
673-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
673+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
674674
; CHECK-ZVBB-NEXT: ret
675675
%x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> shufflevector(<vscale x 1 x i16> insertelement(<vscale x 1 x i16> poison, i16 1, i32 0), <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer))
676676
ret <vscale x 1 x i16> %x
@@ -754,7 +754,7 @@ define <vscale x 2 x i16> @vror_vi_rotl_nxv2i16(<vscale x 2 x i16> %a) {
754754
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i16:
755755
; CHECK-ZVBB: # %bb.0:
756756
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
757-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
757+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
758758
; CHECK-ZVBB-NEXT: ret
759759
%x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> shufflevector(<vscale x 2 x i16> insertelement(<vscale x 2 x i16> poison, i16 1, i32 0), <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer))
760760
ret <vscale x 2 x i16> %x
@@ -838,7 +838,7 @@ define <vscale x 4 x i16> @vror_vi_rotl_nxv4i16(<vscale x 4 x i16> %a) {
838838
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i16:
839839
; CHECK-ZVBB: # %bb.0:
840840
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
841-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
841+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
842842
; CHECK-ZVBB-NEXT: ret
843843
%x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> shufflevector(<vscale x 4 x i16> insertelement(<vscale x 4 x i16> poison, i16 1, i32 0), <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer))
844844
ret <vscale x 4 x i16> %x
@@ -922,7 +922,7 @@ define <vscale x 8 x i16> @vror_vi_rotl_nxv8i16(<vscale x 8 x i16> %a) {
922922
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i16:
923923
; CHECK-ZVBB: # %bb.0:
924924
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
925-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
925+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
926926
; CHECK-ZVBB-NEXT: ret
927927
%x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> shufflevector(<vscale x 8 x i16> insertelement(<vscale x 8 x i16> poison, i16 1, i32 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer))
928928
ret <vscale x 8 x i16> %x
@@ -1006,7 +1006,7 @@ define <vscale x 16 x i16> @vror_vi_rotl_nxv16i16(<vscale x 16 x i16> %a) {
10061006
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i16:
10071007
; CHECK-ZVBB: # %bb.0:
10081008
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
1009-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1009+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
10101010
; CHECK-ZVBB-NEXT: ret
10111011
%x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> shufflevector(<vscale x 16 x i16> insertelement(<vscale x 16 x i16> poison, i16 1, i32 0), <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer))
10121012
ret <vscale x 16 x i16> %x
@@ -1090,7 +1090,7 @@ define <vscale x 32 x i16> @vror_vi_rotl_nxv32i16(<vscale x 32 x i16> %a) {
10901090
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv32i16:
10911091
; CHECK-ZVBB: # %bb.0:
10921092
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
1093-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1093+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 15
10941094
; CHECK-ZVBB-NEXT: ret
10951095
%x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> shufflevector(<vscale x 32 x i16> insertelement(<vscale x 32 x i16> poison, i16 1, i32 0), <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer))
10961096
ret <vscale x 32 x i16> %x
@@ -1187,7 +1187,7 @@ define <vscale x 1 x i32> @vror_vi_rotl_nxv1i32(<vscale x 1 x i32> %a) {
11871187
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv1i32:
11881188
; CHECK-ZVBB: # %bb.0:
11891189
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
1190-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1190+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31
11911191
; CHECK-ZVBB-NEXT: ret
11921192
%x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> shufflevector(<vscale x 1 x i32> insertelement(<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer))
11931193
ret <vscale x 1 x i32> %x
@@ -1284,7 +1284,7 @@ define <vscale x 2 x i32> @vror_vi_rotl_nxv2i32(<vscale x 2 x i32> %a) {
12841284
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv2i32:
12851285
; CHECK-ZVBB: # %bb.0:
12861286
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
1287-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1287+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31
12881288
; CHECK-ZVBB-NEXT: ret
12891289
%x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> shufflevector(<vscale x 2 x i32> insertelement(<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer))
12901290
ret <vscale x 2 x i32> %x
@@ -1381,7 +1381,7 @@ define <vscale x 4 x i32> @vror_vi_rotl_nxv4i32(<vscale x 4 x i32> %a) {
13811381
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv4i32:
13821382
; CHECK-ZVBB: # %bb.0:
13831383
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
1384-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1384+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31
13851385
; CHECK-ZVBB-NEXT: ret
13861386
%x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> shufflevector(<vscale x 4 x i32> insertelement(<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer))
13871387
ret <vscale x 4 x i32> %x
@@ -1478,7 +1478,7 @@ define <vscale x 8 x i32> @vror_vi_rotl_nxv8i32(<vscale x 8 x i32> %a) {
14781478
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv8i32:
14791479
; CHECK-ZVBB: # %bb.0:
14801480
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1481-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1481+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31
14821482
; CHECK-ZVBB-NEXT: ret
14831483
%x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> shufflevector(<vscale x 8 x i32> insertelement(<vscale x 8 x i32> poison, i32 1, i32 0), <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer))
14841484
ret <vscale x 8 x i32> %x
@@ -1575,7 +1575,7 @@ define <vscale x 16 x i32> @vror_vi_rotl_nxv16i32(<vscale x 16 x i32> %a) {
15751575
; CHECK-ZVBB-LABEL: vror_vi_rotl_nxv16i32:
15761576
; CHECK-ZVBB: # %bb.0:
15771577
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1578-
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 63
1578+
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 31
15791579
; CHECK-ZVBB-NEXT: ret
15801580
%x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> shufflevector(<vscale x 16 x i32> insertelement(<vscale x 16 x i32> poison, i32 1, i32 0), <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer))
15811581
ret <vscale x 16 x i32> %x

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