Skip to content

Commit fdce239

Browse files
davemgreendavemgreen
committed
[AArch64] Attempt to emitConjunction from brcond
We currently use emitConjunction to create CCMP conjunctions from the conditions of selects, helping turning and/ors into more optimal ccmp sequences that don't need to go through csels. This extends that to also be used whilst lowering brcond, giving more opportunity for better condition generation. Differential Revision: https://reviews.llvm.org/D118650
1 parent c00db97 commit fdce239

File tree

2 files changed

+83
-81
lines changed

2 files changed

+83
-81
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+19-1
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
345345
setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
346346
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
347347
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
348-
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
348+
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
349349
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
350350
setOperationAction(ISD::BR_CC, MVT::i64, Custom);
351351
setOperationAction(ISD::BR_CC, MVT::f16, Custom);
@@ -5004,6 +5004,22 @@ SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
50045004
Cmp.getValue(1));
50055005
}
50065006

5007+
static SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5008+
SDValue Chain = Op.getOperand(0);
5009+
SDValue Cond = Op.getOperand(1);
5010+
SDValue Dest = Op.getOperand(2);
5011+
5012+
AArch64CC::CondCode CC;
5013+
if (SDValue Cmp = emitConjunction(DAG, Cond, CC)) {
5014+
SDLoc dl(Op);
5015+
SDValue CCVal = DAG.getConstant(CC, dl, MVT::i32);
5016+
return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
5017+
Cmp);
5018+
}
5019+
5020+
return SDValue();
5021+
}
5022+
50075023
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
50085024
SelectionDAG &DAG) const {
50095025
LLVM_DEBUG(dbgs() << "Custom lowering: ");
@@ -5023,6 +5039,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
50235039
case ISD::STRICT_FSETCC:
50245040
case ISD::STRICT_FSETCCS:
50255041
return LowerSETCC(Op, DAG);
5042+
case ISD::BRCOND:
5043+
return LowerBRCOND(Op, DAG);
50265044
case ISD::BR_CC:
50275045
return LowerBR_CC(Op, DAG);
50285046
case ISD::SELECT:

‎llvm/test/CodeGen/AArch64/andorbrcompare.ll

+64-80
Original file line numberDiff line numberDiff line change
@@ -6,19 +6,17 @@ declare void @dummy()
66
define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
77
; CHECK-LABEL: and_eq_ne_ult:
88
; CHECK: // %bb.0: // %entry
9-
; CHECK-NEXT: cmp w0, w1
10-
; CHECK-NEXT: ccmp w2, w3, #4, eq
11-
; CHECK-NEXT: b.ne .LBB0_3
12-
; CHECK-NEXT: // %bb.1: // %entry
13-
; CHECK-NEXT: cmp w4, w5
14-
; CHECK-NEXT: b.lo .LBB0_3
15-
; CHECK-NEXT: // %bb.2:
16-
; CHECK-NEXT: mov w0, wzr
17-
; CHECK-NEXT: ret
18-
; CHECK-NEXT: .LBB0_3: // %if
9+
; CHECK-NEXT: cmp w2, w3
10+
; CHECK-NEXT: ccmp w0, w1, #0, ne
11+
; CHECK-NEXT: ccmp w4, w5, #0, ne
12+
; CHECK-NEXT: b.hs .LBB0_2
13+
; CHECK-NEXT: // %bb.1: // %if
1914
; CHECK-NEXT: mov w0, #1
2015
; CHECK-NEXT: str w0, [x6]
2116
; CHECK-NEXT: ret
17+
; CHECK-NEXT: .LBB0_2:
18+
; CHECK-NEXT: mov w0, wzr
19+
; CHECK-NEXT: ret
2220
entry:
2321
%c0 = icmp eq i32 %s0, %s1
2422
%c1 = icmp ne i32 %s2, %s3
@@ -38,19 +36,17 @@ else:
3836
define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
3937
; CHECK-LABEL: and_ne_ult_ule:
4038
; CHECK: // %bb.0: // %entry
41-
; CHECK-NEXT: cmp w0, w1
42-
; CHECK-NEXT: ccmp w2, w3, #2, ne
43-
; CHECK-NEXT: b.lo .LBB1_3
44-
; CHECK-NEXT: // %bb.1: // %entry
45-
; CHECK-NEXT: cmp w4, w5
46-
; CHECK-NEXT: b.ls .LBB1_3
47-
; CHECK-NEXT: // %bb.2:
48-
; CHECK-NEXT: mov w0, wzr
49-
; CHECK-NEXT: ret
50-
; CHECK-NEXT: .LBB1_3: // %if
39+
; CHECK-NEXT: cmp w2, w3
40+
; CHECK-NEXT: ccmp w0, w1, #4, lo
41+
; CHECK-NEXT: ccmp w4, w5, #0, eq
42+
; CHECK-NEXT: b.hi .LBB1_2
43+
; CHECK-NEXT: // %bb.1: // %if
5144
; CHECK-NEXT: mov w0, #1
5245
; CHECK-NEXT: str w0, [x6]
5346
; CHECK-NEXT: ret
47+
; CHECK-NEXT: .LBB1_2:
48+
; CHECK-NEXT: mov w0, wzr
49+
; CHECK-NEXT: ret
5450
entry:
5551
%c0 = icmp ne i32 %s0, %s1
5652
%c1 = icmp ult i32 %s2, %s3
@@ -70,19 +66,17 @@ else:
7066
define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
7167
; CHECK-LABEL: and_ult_ule_ugt:
7268
; CHECK: // %bb.0: // %entry
73-
; CHECK-NEXT: cmp w0, w1
74-
; CHECK-NEXT: ccmp w2, w3, #2, lo
75-
; CHECK-NEXT: b.ls .LBB2_3
76-
; CHECK-NEXT: // %bb.1: // %entry
77-
; CHECK-NEXT: cmp w4, w5
78-
; CHECK-NEXT: b.hi .LBB2_3
79-
; CHECK-NEXT: // %bb.2:
80-
; CHECK-NEXT: mov w0, wzr
81-
; CHECK-NEXT: ret
82-
; CHECK-NEXT: .LBB2_3: // %if
69+
; CHECK-NEXT: cmp w2, w3
70+
; CHECK-NEXT: ccmp w0, w1, #2, ls
71+
; CHECK-NEXT: ccmp w4, w5, #2, hs
72+
; CHECK-NEXT: b.ls .LBB2_2
73+
; CHECK-NEXT: // %bb.1: // %if
8374
; CHECK-NEXT: mov w0, #1
8475
; CHECK-NEXT: str w0, [x6]
8576
; CHECK-NEXT: ret
77+
; CHECK-NEXT: .LBB2_2:
78+
; CHECK-NEXT: mov w0, wzr
79+
; CHECK-NEXT: ret
8680
entry:
8781
%c0 = icmp ult i32 %s0, %s1
8882
%c1 = icmp ule i32 %s2, %s3
@@ -102,19 +96,17 @@ else:
10296
define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
10397
; CHECK-LABEL: and_ule_ugt_uge:
10498
; CHECK: // %bb.0: // %entry
105-
; CHECK-NEXT: cmp w0, w1
106-
; CHECK-NEXT: ccmp w2, w3, #0, ls
107-
; CHECK-NEXT: b.hi .LBB3_3
108-
; CHECK-NEXT: // %bb.1: // %entry
109-
; CHECK-NEXT: cmp w4, w5
110-
; CHECK-NEXT: b.hs .LBB3_3
111-
; CHECK-NEXT: // %bb.2:
112-
; CHECK-NEXT: mov w0, wzr
113-
; CHECK-NEXT: ret
114-
; CHECK-NEXT: .LBB3_3: // %if
99+
; CHECK-NEXT: cmp w2, w3
100+
; CHECK-NEXT: ccmp w0, w1, #2, hi
101+
; CHECK-NEXT: ccmp w4, w5, #2, hi
102+
; CHECK-NEXT: b.lo .LBB3_2
103+
; CHECK-NEXT: // %bb.1: // %if
115104
; CHECK-NEXT: mov w0, #1
116105
; CHECK-NEXT: str w0, [x6]
117106
; CHECK-NEXT: ret
107+
; CHECK-NEXT: .LBB3_2:
108+
; CHECK-NEXT: mov w0, wzr
109+
; CHECK-NEXT: ret
118110
entry:
119111
%c0 = icmp ule i32 %s0, %s1
120112
%c1 = icmp ugt i32 %s2, %s3
@@ -134,19 +126,17 @@ else:
134126
define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
135127
; CHECK-LABEL: and_ugt_uge_slt:
136128
; CHECK: // %bb.0: // %entry
137-
; CHECK-NEXT: cmp w0, w1
138-
; CHECK-NEXT: ccmp w2, w3, #0, hi
139-
; CHECK-NEXT: b.hs .LBB4_3
140-
; CHECK-NEXT: // %bb.1: // %entry
141-
; CHECK-NEXT: cmp w4, w5
142-
; CHECK-NEXT: b.lt .LBB4_3
143-
; CHECK-NEXT: // %bb.2:
144-
; CHECK-NEXT: mov w0, wzr
145-
; CHECK-NEXT: ret
146-
; CHECK-NEXT: .LBB4_3: // %if
129+
; CHECK-NEXT: cmp w2, w3
130+
; CHECK-NEXT: ccmp w0, w1, #0, hs
131+
; CHECK-NEXT: ccmp w4, w5, #8, ls
132+
; CHECK-NEXT: b.ge .LBB4_2
133+
; CHECK-NEXT: // %bb.1: // %if
147134
; CHECK-NEXT: mov w0, #1
148135
; CHECK-NEXT: str w0, [x6]
149136
; CHECK-NEXT: ret
137+
; CHECK-NEXT: .LBB4_2:
138+
; CHECK-NEXT: mov w0, wzr
139+
; CHECK-NEXT: ret
150140
entry:
151141
%c0 = icmp ugt i32 %s0, %s1
152142
%c1 = icmp uge i32 %s2, %s3
@@ -166,19 +156,17 @@ else:
166156
define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
167157
; CHECK-LABEL: and_uge_slt_sle:
168158
; CHECK: // %bb.0: // %entry
169-
; CHECK-NEXT: cmp w0, w1
170-
; CHECK-NEXT: ccmp w2, w3, #0, hs
171-
; CHECK-NEXT: b.lt .LBB5_3
172-
; CHECK-NEXT: // %bb.1: // %entry
173-
; CHECK-NEXT: cmp w4, w5
174-
; CHECK-NEXT: b.le .LBB5_3
175-
; CHECK-NEXT: // %bb.2:
176-
; CHECK-NEXT: mov w0, wzr
177-
; CHECK-NEXT: ret
178-
; CHECK-NEXT: .LBB5_3: // %if
159+
; CHECK-NEXT: cmp w2, w3
160+
; CHECK-NEXT: ccmp w0, w1, #0, lt
161+
; CHECK-NEXT: ccmp w4, w5, #4, lo
162+
; CHECK-NEXT: b.gt .LBB5_2
163+
; CHECK-NEXT: // %bb.1: // %if
179164
; CHECK-NEXT: mov w0, #1
180165
; CHECK-NEXT: str w0, [x6]
181166
; CHECK-NEXT: ret
167+
; CHECK-NEXT: .LBB5_2:
168+
; CHECK-NEXT: mov w0, wzr
169+
; CHECK-NEXT: ret
182170
entry:
183171
%c0 = icmp uge i32 %s0, %s1
184172
%c1 = icmp slt i32 %s2, %s3
@@ -198,19 +186,17 @@ else:
198186
define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
199187
; CHECK-LABEL: and_slt_sle_sgt:
200188
; CHECK: // %bb.0: // %entry
201-
; CHECK-NEXT: cmp w0, w1
202-
; CHECK-NEXT: ccmp w2, w3, #0, lt
203-
; CHECK-NEXT: b.le .LBB6_3
204-
; CHECK-NEXT: // %bb.1: // %entry
205-
; CHECK-NEXT: cmp w4, w5
206-
; CHECK-NEXT: b.gt .LBB6_3
207-
; CHECK-NEXT: // %bb.2:
208-
; CHECK-NEXT: mov w0, wzr
209-
; CHECK-NEXT: ret
210-
; CHECK-NEXT: .LBB6_3: // %if
189+
; CHECK-NEXT: cmp w2, w3
190+
; CHECK-NEXT: ccmp w0, w1, #0, le
191+
; CHECK-NEXT: ccmp w4, w5, #0, ge
192+
; CHECK-NEXT: b.le .LBB6_2
193+
; CHECK-NEXT: // %bb.1: // %if
211194
; CHECK-NEXT: mov w0, #1
212195
; CHECK-NEXT: str w0, [x6]
213196
; CHECK-NEXT: ret
197+
; CHECK-NEXT: .LBB6_2:
198+
; CHECK-NEXT: mov w0, wzr
199+
; CHECK-NEXT: ret
214200
entry:
215201
%c0 = icmp slt i32 %s0, %s1
216202
%c1 = icmp sle i32 %s2, %s3
@@ -230,19 +216,17 @@ else:
230216
define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
231217
; CHECK-LABEL: and_sle_sgt_sge:
232218
; CHECK: // %bb.0: // %entry
233-
; CHECK-NEXT: cmp w0, w1
234-
; CHECK-NEXT: ccmp w2, w3, #4, le
235-
; CHECK-NEXT: b.gt .LBB7_3
236-
; CHECK-NEXT: // %bb.1: // %entry
237-
; CHECK-NEXT: cmp w4, w5
238-
; CHECK-NEXT: b.ge .LBB7_3
239-
; CHECK-NEXT: // %bb.2:
240-
; CHECK-NEXT: mov w0, wzr
241-
; CHECK-NEXT: ret
242-
; CHECK-NEXT: .LBB7_3: // %if
219+
; CHECK-NEXT: cmp w2, w3
220+
; CHECK-NEXT: ccmp w0, w1, #0, gt
221+
; CHECK-NEXT: ccmp w4, w5, #0, gt
222+
; CHECK-NEXT: b.lt .LBB7_2
223+
; CHECK-NEXT: // %bb.1: // %if
243224
; CHECK-NEXT: mov w0, #1
244225
; CHECK-NEXT: str w0, [x6]
245226
; CHECK-NEXT: ret
227+
; CHECK-NEXT: .LBB7_2:
228+
; CHECK-NEXT: mov w0, wzr
229+
; CHECK-NEXT: ret
246230
entry:
247231
%c0 = icmp sle i32 %s0, %s1
248232
%c1 = icmp sgt i32 %s2, %s3

0 commit comments

Comments
 (0)