Skip to content

Commit fc93787

Browse files
committed
[MC][PowerPC] Make .reloc support arbitrary relocation types
Generalizes ad7199f (R_PPC_NONE/R_PPC64_NONE).
1 parent 09d4021 commit fc93787

File tree

4 files changed

+52
-19
lines changed

4 files changed

+52
-19
lines changed

llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp

+31-16
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
2828
switch (Kind) {
2929
default:
3030
llvm_unreachable("Unknown fixup kind!");
31-
case FK_NONE:
3231
case FK_Data_1:
3332
case FK_Data_2:
3433
case FK_Data_4:
@@ -52,8 +51,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
5251
switch (Kind) {
5352
default:
5453
llvm_unreachable("Unknown fixup kind!");
55-
case FK_NONE:
56-
return 0;
5754
case FK_Data_1:
5855
return 1;
5956
case FK_Data_2:
@@ -109,6 +106,11 @@ class PPCAsmBackend : public MCAsmBackend {
109106
{ "fixup_ppc_nofixup", 0, 0, 0 }
110107
};
111108

109+
// Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
110+
// do not require any extra processing.
111+
if (Kind >= FirstLiteralRelocationKind)
112+
return MCAsmBackend::getFixupKindInfo(FK_NONE);
113+
112114
if (Kind < FirstTargetFixupKind)
113115
return MCAsmBackend::getFixupKindInfo(Kind);
114116

@@ -123,11 +125,14 @@ class PPCAsmBackend : public MCAsmBackend {
123125
const MCValue &Target, MutableArrayRef<char> Data,
124126
uint64_t Value, bool IsResolved,
125127
const MCSubtargetInfo *STI) const override {
126-
Value = adjustFixupValue(Fixup.getKind(), Value);
128+
MCFixupKind Kind = Fixup.getKind();
129+
if (Kind >= FirstLiteralRelocationKind)
130+
return;
131+
Value = adjustFixupValue(Kind, Value);
127132
if (!Value) return; // Doesn't change encoding.
128133

129134
unsigned Offset = Fixup.getOffset();
130-
unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
135+
unsigned NumBytes = getFixupKindNumBytes(Kind);
131136

132137
// For each byte of the fragment that the fixup touches, mask in the bits
133138
// from the fixup value. The Value has been "split up" into the appropriate
@@ -140,11 +145,10 @@ class PPCAsmBackend : public MCAsmBackend {
140145

141146
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
142147
const MCValue &Target) override {
143-
switch ((unsigned)Fixup.getKind()) {
148+
MCFixupKind Kind = Fixup.getKind();
149+
switch ((unsigned)Kind) {
144150
default:
145-
return false;
146-
case FK_NONE:
147-
return true;
151+
return Kind >= FirstLiteralRelocationKind;
148152
case PPC::fixup_ppc_br24:
149153
case PPC::fixup_ppc_br24abs:
150154
// If the target symbol has a local entry point we must not attempt
@@ -228,14 +232,25 @@ class XCOFFPPCAsmBackend : public PPCAsmBackend {
228232
} // end anonymous namespace
229233

230234
Optional<MCFixupKind> ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
231-
if (TT.isPPC64()) {
232-
if (Name == "R_PPC64_NONE")
233-
return FK_NONE;
234-
} else {
235-
if (Name == "R_PPC_NONE")
236-
return FK_NONE;
235+
if (TT.isOSBinFormatELF()) {
236+
unsigned Type;
237+
if (TT.isPPC64()) {
238+
Type = llvm::StringSwitch<unsigned>(Name)
239+
#define ELF_RELOC(X, Y) .Case(#X, Y)
240+
#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
241+
#undef ELF_RELOC
242+
.Default(-1u);
243+
} else {
244+
Type = llvm::StringSwitch<unsigned>(Name)
245+
#define ELF_RELOC(X, Y) .Case(#X, Y)
246+
#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
247+
#undef ELF_RELOC
248+
.Default(-1u);
249+
}
250+
if (Type != -1u)
251+
return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
237252
}
238-
return MCAsmBackend::getFixupKind(Name);
253+
return None;
239254
}
240255

241256
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,

llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,9 @@ static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
7373
unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
7474
const MCFixup &Fixup,
7575
bool IsPCRel) const {
76+
MCFixupKind Kind = Fixup.getKind();
77+
if (Kind >= FirstLiteralRelocationKind)
78+
return Kind - FirstLiteralRelocationKind;
7679
MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup);
7780

7881
// determine the type of the relocation
@@ -133,9 +136,6 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
133136
} else {
134137
switch (Fixup.getTargetKind()) {
135138
default: llvm_unreachable("invalid fixup kind!");
136-
case FK_NONE:
137-
Type = ELF::R_PPC_NONE;
138-
break;
139139
case PPC::fixup_ppc_br24abs:
140140
Type = ELF::R_PPC_ADDR24;
141141
break;

llvm/test/MC/PowerPC/ppc32-reloc-directive.s

+9
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,16 @@
55
# PRINT: .reloc 8, R_PPC_NONE, .data
66
# PRINT: .reloc 4, R_PPC_NONE, foo+4
77
# PRINT: .reloc 0, R_PPC_NONE, 8
8+
# PRINT: .reloc 0, R_PPC_ADDR32, .data+2
9+
# PRINT: .reloc 0, R_PPC_REL16_HI, foo+3
10+
# PRINT: .reloc 0, R_PPC_REL16_HA, 5
811

912
# CHECK: 0x8 R_PPC_NONE .data 0x0
1013
# CHECK-NEXT: 0x4 R_PPC_NONE foo 0x4
1114
# CHECK-NEXT: 0x0 R_PPC_NONE - 0x8
15+
# CHECK-NEXT: 0x0 R_PPC_ADDR32 .data 0x2
16+
# CHECK-NEXT: 0x0 R_PPC_REL16_HI foo 0x3
17+
# CHECK-NEXT: 0x0 R_PPC_REL16_HA - 0x5
1218

1319
.text
1420
blr
@@ -17,6 +23,9 @@
1723
.reloc 8, R_PPC_NONE, .data
1824
.reloc 4, R_PPC_NONE, foo+4
1925
.reloc 0, R_PPC_NONE, 8
26+
.reloc 0, R_PPC_ADDR32, .data+2
27+
.reloc 0, R_PPC_REL16_HI, foo+3
28+
.reloc 0, R_PPC_REL16_HA, 5
2029

2130
.data
2231
.globl foo

llvm/test/MC/PowerPC/ppc64-reloc-directive.s

+9
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,16 @@
77
# PRINT: .reloc 8, R_PPC64_NONE, .data
88
# PRINT: .reloc 4, R_PPC64_NONE, foo+4
99
# PRINT: .reloc 0, R_PPC64_NONE, 8
10+
# PRINT: .reloc 0, R_PPC64_ADDR32, .data+2
11+
# PRINT: .reloc 0, R_PPC64_REL16_HI, foo+3
12+
# PRINT: .reloc 0, R_PPC64_REL16_HA, 5
1013

1114
# CHECK: 0x8 R_PPC64_NONE .data 0x0
1215
# CHECK-NEXT: 0x4 R_PPC64_NONE foo 0x4
1316
# CHECK-NEXT: 0x0 R_PPC64_NONE - 0x8
17+
# CHECK-NEXT: 0x0 R_PPC64_ADDR32 .data 0x2
18+
# CHECK-NEXT: 0x0 R_PPC64_REL16_HI foo 0x3
19+
# CHECK-NEXT: 0x0 R_PPC64_REL16_HA - 0x5
1420

1521
.text
1622
blr
@@ -19,6 +25,9 @@
1925
.reloc 8, R_PPC64_NONE, .data
2026
.reloc 4, R_PPC64_NONE, foo+4
2127
.reloc 0, R_PPC64_NONE, 8
28+
.reloc 0, R_PPC64_ADDR32, .data+2
29+
.reloc 0, R_PPC64_REL16_HI, foo+3
30+
.reloc 0, R_PPC64_REL16_HA, 5
2231

2332
.data
2433
.globl foo

0 commit comments

Comments
 (0)