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[PowerPC] The builtins load8r and store8r are Power 7 plus.
This patch makes sure that the builtins __builtin_ppc_load8r and __ builtin_ppc_store8r are only available for Power 7 and up. Currently the builtins seem to produce incorrect code if used for Power 6 or before. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D110653
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‎clang/lib/Basic/Targets/PPC.cpp

+10
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
7373
HasROPProtect = true;
7474
} else if (Feature == "+privileged") {
7575
HasPrivileged = true;
76+
} else if (Feature == "+isa-v206-instructions") {
77+
IsISA2_06 = true;
7678
} else if (Feature == "+isa-v207-instructions") {
7779
IsISA2_07 = true;
7880
} else if (Feature == "+isa-v30-instructions") {
@@ -526,6 +528,13 @@ bool PPCTargetInfo::initFeatureMap(
526528
.Case("e500", true)
527529
.Default(false);
528530

531+
Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
532+
.Case("ppc64le", true)
533+
.Case("pwr9", true)
534+
.Case("pwr8", true)
535+
.Case("pwr7", true)
536+
.Default(false);
537+
529538
Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
530539
.Case("ppc64le", true)
531540
.Case("pwr9", true)
@@ -622,6 +631,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
622631
.Case("mma", HasMMA)
623632
.Case("rop-protect", HasROPProtect)
624633
.Case("privileged", HasPrivileged)
634+
.Case("isa-v206-instructions", IsISA2_06)
625635
.Case("isa-v207-instructions", IsISA2_07)
626636
.Case("isa-v30-instructions", IsISA3_0)
627637
.Case("isa-v31-instructions", IsISA3_1)

‎clang/lib/Basic/Targets/PPC.h

+1
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
7474
bool HasP10Vector = false;
7575
bool HasPCRelativeMemops = false;
7676
bool HasPrefixInstrs = false;
77+
bool IsISA2_06 = false;
7778
bool IsISA2_07 = false;
7879
bool IsISA3_0 = false;
7980
bool IsISA3_1 = false;

‎clang/lib/Sema/SemaChecking.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -3512,6 +3512,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
35123512
diag::err_ppc_builtin_requires_vsx) ||
35133513
SemaBuiltinConstantArgRange(TheCall, 1, 0, 127);
35143514
}
3515+
case PPC::BI__builtin_ppc_load8r:
3516+
case PPC::BI__builtin_ppc_store8r:
3517+
return SemaFeatureCheck(*this, TheCall, "isa-v206-instructions",
3518+
diag::err_ppc_builtin_only_on_arch, "7");
35153519
#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
35163520
case PPC::BI__builtin_##Name: \
35173521
return SemaBuiltinPPCMMACall(TheCall, Types);

‎clang/test/Driver/ppc-isa-features.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,14 @@
1+
// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr6 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR6
12
// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr7 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR7
23
// RUN: %clang -target powerpc64le-unknown-unknown -mcpu=pwr8 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR8
34
// RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR9
45
// RUN: %clang -target powerpc-unknown-aix -mcpu=pwr10 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR10
56

7+
// CHECK-PWR6: -isa-v206-instructions
8+
// CHECK-PWR6: -isa-v207-instructions
9+
// CHECK-PWR6: -isa-v30-instructions
10+
11+
// CHECK-PWR7: +isa-v206-instructions
612
// CHECK-PWR7: -isa-v207-instructions
713
// CHECK-PWR7: -isa-v30-instructions
814

‎llvm/lib/Target/PowerPC/PPC.td

+5-1
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,9 @@ def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
213213
def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
214214
"Treat vector data stream cache control instructions as deprecated">;
215215

216+
def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
217+
"true",
218+
"Enable instructions in ISA 2.06.">;
216219
def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
217220
"true",
218221
"Enable instructions in ISA 2.07.">;
@@ -319,7 +322,8 @@ def ProcessorFeatures {
319322
FeatureMFTB,
320323
DeprecatedDST,
321324
FeatureTwoConstNR,
322-
FeatureUnalignedFloats];
325+
FeatureUnalignedFloats,
326+
FeatureISA2_06];
323327
list<SubtargetFeature> P7SpecificFeatures = [];
324328
list<SubtargetFeature> P7Features =
325329
!listconcat(P7InheritableFeatures, P7SpecificFeatures);

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

+6
Original file line numberDiff line numberDiff line change
@@ -1302,9 +1302,12 @@ def LDtocBA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
13021302
def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src),
13031303
"ldx $rD, $src", IIC_LdStLD,
13041304
[(set i64:$rD, (load XForm:$src))]>, isPPC64;
1305+
1306+
let Predicates = [IsISA2_06] in {
13051307
def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src),
13061308
"ldbrx $rD, $src", IIC_LdStLoad,
13071309
[(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64;
1310+
}
13081311

13091312
let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
13101313
def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src),
@@ -1538,10 +1541,13 @@ def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
15381541
"stdx $rS, $dst", IIC_LdStSTD,
15391542
[(store i64:$rS, XForm:$dst)]>, isPPC64,
15401543
PPC970_DGroup_Cracked;
1544+
1545+
let Predicates = [IsISA2_06] in {
15411546
def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
15421547
"stdbrx $rS, $dst", IIC_LdStStore,
15431548
[(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64,
15441549
PPC970_DGroup_Cracked;
1550+
}
15451551

15461552
let mayStore = 1, hasNoSchedulingInfo = 1 in {
15471553
// Normal 16-byte stores.

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

+1
Original file line numberDiff line numberDiff line change
@@ -1182,6 +1182,7 @@ def NaNsFPMath
11821182
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
11831183
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
11841184
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
1185+
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
11851186
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
11861187
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
11871188
def HasFPU : Predicate<"Subtarget->hasFPU()">;

‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -127,6 +127,7 @@ void PPCSubtarget::initializeEnvironment() {
127127
HasStoreFusion = false;
128128
HasAddiLoadFusion = false;
129129
HasAddisLoadFusion = false;
130+
IsISA2_06 = false;
130131
IsISA2_07 = false;
131132
IsISA3_0 = false;
132133
IsISA3_1 = false;

‎llvm/lib/Target/PowerPC/PPCSubtarget.h

+2
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
147147
bool HasStoreFusion;
148148
bool HasAddiLoadFusion;
149149
bool HasAddisLoadFusion;
150+
bool IsISA2_06;
150151
bool IsISA2_07;
151152
bool IsISA3_0;
152153
bool IsISA3_1;
@@ -322,6 +323,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
322323

323324
bool hasHTM() const { return HasHTM; }
324325
bool hasFloat128() const { return HasFloat128; }
326+
bool isISA2_06() const { return IsISA2_06; }
325327
bool isISA2_07() const { return IsISA2_07; }
326328
bool isISA3_0() const { return IsISA3_0; }
327329
bool isISA3_1() const { return IsISA3_1; }

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