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Richard Osborne
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Add instruction encodings / disassembler support for 2rus instructions.
llvm-svn: 172985
1 parent 3fb7395 commit f063fce

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4 files changed

+113
-23
lines changed

4 files changed

+113
-23
lines changed

‎llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

+57
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,16 @@ static DecodeStatus Decode3RInstruction(MCInst &Inst,
137137
uint64_t Address,
138138
const void *Decoder);
139139

140+
static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
141+
unsigned Insn,
142+
uint64_t Address,
143+
const void *Decoder);
144+
145+
static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
146+
unsigned Insn,
147+
uint64_t Address,
148+
const void *Decoder);
149+
140150
#include "XCoreGenDisassemblerTables.inc"
141151

142152
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@@ -202,6 +212,12 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
202212
// Try and decode as a 3R instruction.
203213
unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
204214
switch (Opcode) {
215+
case 0x0:
216+
Inst.setOpcode(XCore::STW_2rus);
217+
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
218+
case 0x1:
219+
Inst.setOpcode(XCore::LDW_2rus);
220+
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
205221
case 0x2:
206222
Inst.setOpcode(XCore::ADD_3r);
207223
return Decode3RInstruction(Inst, Insn, Address, Decoder);
@@ -232,6 +248,21 @@ Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
232248
case 0x11:
233249
Inst.setOpcode(XCore::LD8U_3r);
234250
return Decode3RInstruction(Inst, Insn, Address, Decoder);
251+
case 0x12:
252+
Inst.setOpcode(XCore::ADD_2rus);
253+
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
254+
case 0x13:
255+
Inst.setOpcode(XCore::SUB_2rus);
256+
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
257+
case 0x14:
258+
Inst.setOpcode(XCore::SHL_2rus);
259+
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
260+
case 0x15:
261+
Inst.setOpcode(XCore::SHR_2rus);
262+
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
263+
case 0x16:
264+
Inst.setOpcode(XCore::EQ_2rus);
265+
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
235266
case 0x18:
236267
Inst.setOpcode(XCore::LSS_3r);
237268
return Decode3RInstruction(Inst, Insn, Address, Decoder);
@@ -361,6 +392,32 @@ Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
361392
return S;
362393
}
363394

395+
static DecodeStatus
396+
Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
397+
const void *Decoder) {
398+
unsigned Op1, Op2, Op3;
399+
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
400+
if (S == MCDisassembler::Success) {
401+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
402+
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
403+
Inst.addOperand(MCOperand::CreateImm(Op3));
404+
}
405+
return S;
406+
}
407+
408+
static DecodeStatus
409+
Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
410+
const void *Decoder) {
411+
unsigned Op1, Op2, Op3;
412+
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
413+
if (S == MCDisassembler::Success) {
414+
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
415+
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
416+
DecodeBitpOperand(Inst, Op3, Address, Decoder);
417+
}
418+
return S;
419+
}
420+
364421
MCDisassembler::DecodeStatus
365422
XCoreDisassembler::getInstruction(MCInst &instr,
366423
uint64_t &Size,

‎llvm/lib/Target/XCore/XCoreInstrFormats.td

+10-1
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,17 @@ class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
4343
: InstXCore<4, outs, ins, asmstr, pattern> {
4444
}
4545

46-
class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
46+
class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
4747
: InstXCore<2, outs, ins, asmstr, pattern> {
48+
let Inst{15-11} = opc;
49+
let DecoderMethod = "Decode2RUSInstruction";
50+
}
51+
52+
// 2RUS with bitp operand
53+
class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
54+
list<dag> pattern>
55+
: _F2RUS<opc, outs, ins, asmstr, pattern> {
56+
let DecoderMethod = "Decode2RUSBitpInstruction";
4857
}
4958

5059
class _FL2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>

‎llvm/lib/Target/XCore/XCoreInstrInfo.td

+23-22
Original file line numberDiff line numberDiff line change
@@ -200,30 +200,30 @@ def InlineJT32 : Operand<i32> {
200200

201201
// Three operand short
202202

203-
multiclass F3R_2RUS<bits<5> opc, string OpcStr, SDNode OpNode> {
204-
def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
203+
multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
204+
def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
205205
!strconcat(OpcStr, " $dst, $b, $c"),
206206
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
207-
def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
207+
def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
208208
!strconcat(OpcStr, " $dst, $b, $c"),
209209
[(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
210210
}
211211

212-
multiclass F3R_2RUS_np<bits<5> opc, string OpcStr> {
213-
def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
212+
multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
213+
def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
214214
!strconcat(OpcStr, " $dst, $b, $c"), []>;
215-
def _2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
215+
def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
216216
!strconcat(OpcStr, " $dst, $b, $c"), []>;
217217
}
218218

219-
multiclass F3R_2RBITP<bits<5> opc, string OpcStr, SDNode OpNode> {
220-
def _3r: _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
219+
multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
220+
SDNode OpNode> {
221+
def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
221222
!strconcat(OpcStr, " $dst, $b, $c"),
222223
[(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
223-
def _2rus : _F2RUS<
224-
(outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
225-
!strconcat(OpcStr, " $dst, $b, $c"),
226-
[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
224+
def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
225+
!strconcat(OpcStr, " $dst, $b, $c"),
226+
[(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
227227
}
228228

229229
class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
@@ -382,10 +382,10 @@ let usesCustomInserter = 1 in {
382382
//===----------------------------------------------------------------------===//
383383

384384
// Three operand short
385-
defm ADD : F3R_2RUS<0b00010, "add", add>;
386-
defm SUB : F3R_2RUS<0b00011, "sub", sub>;
385+
defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
386+
defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
387387
let neverHasSideEffects = 1 in {
388-
defm EQ : F3R_2RUS_np<0b00110, "eq">;
388+
defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
389389
def LSS_3r : F3R_np<0b11000, "lss">;
390390
def LSU_3r : F3R_np<0b11001, "lsu">;
391391
}
@@ -397,9 +397,9 @@ def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
397397
(ins GRRegs:$addr, GRRegs:$offset),
398398
"ldw $dst, $addr[$offset]", []>;
399399

400-
def LDW_2rus : _F2RUS<(outs GRRegs:$dst), (ins GRRegs:$addr, i32imm:$offset),
401-
"ldw $dst, $addr[$offset]",
402-
[]>;
400+
def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
401+
(ins GRRegs:$addr, i32imm:$offset),
402+
"ldw $dst, $addr[$offset]", []>;
403403

404404
def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
405405
(ins GRRegs:$addr, GRRegs:$offset),
@@ -414,12 +414,13 @@ let mayStore=1 in {
414414
def STW_3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
415415
"stw $val, $addr[$offset]", []>;
416416

417-
def STW_2rus : _F2RUS<(outs), (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
418-
"stw $val, $addr[$offset]", []>;
417+
def STW_2rus : _F2RUS<0b0000, (outs),
418+
(ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
419+
"stw $val, $addr[$offset]", []>;
419420
}
420421

421-
defm SHL : F3R_2RBITP<0b00100, "shl", shl>;
422-
defm SHR : F3R_2RBITP<0b00101, "shr", srl>;
422+
defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
423+
defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
423424
// TODO tsetr
424425

425426
// Three operand long

‎llvm/test/MC/Disassembler/XCore/xcore.txt

+23
Original file line numberDiff line numberDiff line change
@@ -234,3 +234,26 @@
234234

235235
# CHECK: sub r4, r2, r5
236236
0x89 0x1a
237+
238+
# 2rus instructions
239+
240+
# CHECK: add r10, r2, 5
241+
0xe9 0x92
242+
243+
# CHECK: eq r2, r1, 0
244+
0x24 0xb0
245+
246+
# CHECK: ldw r5, r6[1]
247+
0x19 0x09
248+
249+
# CHECK: shl r6, r5, 24
250+
0xa6 0xa5
251+
252+
# CHECK: shr r3, r8, 5
253+
0xf1 0xab
254+
255+
# CHECK: stw r3, r2[0]
256+
0x38 0x00
257+
258+
# CHECK: sub r2, r4, 11
259+
0x63 0x9d

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