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Evan Cheng
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- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
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54 files changed

+277
-232
lines changed

‎llvm/include/llvm/ExecutionEngine/ExecutionEngine.h

+4-2
Original file line numberDiff line numberDiff line change
@@ -480,7 +480,7 @@ class EngineBuilder {
480480
JMM = NULL;
481481
AllocateGVsWithCode = false;
482482
RelocModel = Reloc::Default;
483-
CMModel = CodeModel::Default;
483+
CMModel = CodeModel::JITDefault;
484484
UseMCJIT = false;
485485
}
486486

@@ -529,7 +529,8 @@ class EngineBuilder {
529529
}
530530

531531
/// setCodeModel - Set the CodeModel that the ExecutionEngine target
532-
/// data is using. Defaults to target specific default "CodeModel::Default".
532+
/// data is using. Defaults to target specific default
533+
/// "CodeModel::JITDefault".
533534
EngineBuilder &setCodeModel(CodeModel::Model M) {
534535
CMModel = M;
535536
return *this;
@@ -581,6 +582,7 @@ class EngineBuilder {
581582
StringRef MCPU,
582583
const SmallVectorImpl<std::string>& MAttrs,
583584
Reloc::Model RM,
585+
CodeModel::Model CM,
584586
std::string *Err);
585587

586588
ExecutionEngine *create();

‎llvm/include/llvm/MC/MCCodeGenInfo.h

+14-1
Original file line numberDiff line numberDiff line change
@@ -16,20 +16,33 @@
1616
#define LLVM_MC_MCCODEGENINFO_H
1717

1818
namespace llvm {
19+
1920
// Relocation model types.
2021
namespace Reloc {
2122
enum Model { Default, Static, PIC_, DynamicNoPIC };
2223
}
2324

25+
// Code model types.
26+
namespace CodeModel {
27+
enum Model { Default, JITDefault, Small, Kernel, Medium, Large };
28+
}
29+
2430
class MCCodeGenInfo {
2531
/// RelocationModel - Relocation model: statcic, pic, etc.
2632
///
2733
Reloc::Model RelocationModel;
2834

35+
/// CMModel - Code model.
36+
///
37+
CodeModel::Model CMModel;
38+
2939
public:
30-
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default);
40+
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
41+
CodeModel::Model CM = CodeModel::Default);
3142

3243
Reloc::Model getRelocationModel() const { return RelocationModel; }
44+
45+
CodeModel::Model getCodeModel() const { return CMModel; }
3346
};
3447
} // namespace llvm
3548

‎llvm/include/llvm/Target/TargetMachine.h

+3-21
Original file line numberDiff line numberDiff line change
@@ -43,17 +43,6 @@ class TargetSubtargetInfo;
4343
class formatted_raw_ostream;
4444
class raw_ostream;
4545

46-
// Code model types.
47-
namespace CodeModel {
48-
enum Model {
49-
Default,
50-
Small,
51-
Kernel,
52-
Medium,
53-
Large
54-
};
55-
}
56-
5746
// Code generation optimization level.
5847
namespace CodeGenOpt {
5948
enum Level {
@@ -101,7 +90,6 @@ class TargetMachine {
10190
std::string TargetFS;
10291

10392
/// CodeGenInfo - Low level target information such as relocation model.
104-
///
10593
const MCCodeGenInfo *CodeGenInfo;
10694

10795
/// AsmInfo - Contains target specific asm information.
@@ -214,11 +202,7 @@ class TargetMachine {
214202

215203
/// getCodeModel - Returns the code model. The choices are small, kernel,
216204
/// medium, large, and target default.
217-
static CodeModel::Model getCodeModel();
218-
219-
/// setCodeModel - Sets the code model.
220-
///
221-
static void setCodeModel(CodeModel::Model Model);
205+
CodeModel::Model getCodeModel() const;
222206

223207
/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
224208
///
@@ -301,7 +285,8 @@ class TargetMachine {
301285
class LLVMTargetMachine : public TargetMachine {
302286
protected: // Can only create subclasses.
303287
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
304-
StringRef CPU, StringRef FS, Reloc::Model RM);
288+
StringRef CPU, StringRef FS,
289+
Reloc::Model RM, CodeModel::Model CM);
305290

306291
private:
307292
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
@@ -310,9 +295,6 @@ class LLVMTargetMachine : public TargetMachine {
310295
bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
311296
bool DisableVerify, MCContext *&OutCtx);
312297

313-
virtual void setCodeModelForJIT();
314-
virtual void setCodeModelForStatic();
315-
316298
public:
317299
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
318300
/// specified file emitted. Typically this will involve several steps of code

‎llvm/include/llvm/Target/TargetRegistry.h

+17-10
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,9 @@ namespace llvm {
7070

7171
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
7272
StringRef TT);
73-
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M);
73+
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
74+
Reloc::Model RM,
75+
CodeModel::Model CM);
7476
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
7577
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
7678
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
@@ -80,7 +82,8 @@ namespace llvm {
8082
StringRef TT,
8183
StringRef CPU,
8284
StringRef Features,
83-
Reloc::Model RM);
85+
Reloc::Model RM,
86+
CodeModel::Model CM);
8487
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
8588
MCStreamer &Streamer);
8689
typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T,
@@ -263,10 +266,11 @@ namespace llvm {
263266

264267
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
265268
///
266-
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const {
269+
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
270+
CodeModel::Model CM) const {
267271
if (!MCCodeGenInfoCtorFn)
268272
return 0;
269-
return MCCodeGenInfoCtorFn(Triple, M);
273+
return MCCodeGenInfoCtorFn(Triple, RM, CM);
270274
}
271275

272276
/// createMCInstrInfo - Create a MCInstrInfo implementation.
@@ -309,11 +313,12 @@ namespace llvm {
309313
/// either the target triple from the module, or the target triple of the
310314
/// host if that does not exist.
311315
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
312-
StringRef Features,
313-
Reloc::Model RM = Reloc::Default) const {
316+
StringRef Features,
317+
Reloc::Model RM = Reloc::Default,
318+
CodeModel::Model CM = CodeModel::Default) const {
314319
if (!TargetMachineCtorFn)
315320
return 0;
316-
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM);
321+
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM, CM);
317322
}
318323

319324
/// createAsmBackend - Create a target specific assembly parser.
@@ -802,7 +807,8 @@ namespace llvm {
802807
TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
803808
}
804809
private:
805-
static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) {
810+
static MCCodeGenInfo *Allocator(StringRef TT,
811+
Reloc::Model RM, CodeModel::Model CM) {
806812
return new MCCodeGenInfoImpl();
807813
}
808814
};
@@ -938,8 +944,9 @@ namespace llvm {
938944
private:
939945
static TargetMachine *Allocator(const Target &T, StringRef TT,
940946
StringRef CPU, StringRef FS,
941-
Reloc::Model RM) {
942-
return new TargetMachineImpl(T, TT, CPU, FS, RM);
947+
Reloc::Model RM,
948+
CodeModel::Model CM) {
949+
return new TargetMachineImpl(T, TT, CPU, FS, RM, CM);
943950
}
944951
};
945952

‎llvm/lib/CodeGen/LLVMTargetMachine.cpp

+2-21
Original file line numberDiff line numberDiff line change
@@ -105,23 +105,12 @@ EnableFastISelOption("fast-isel", cl::Hidden,
105105

106106
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
107107
StringRef CPU, StringRef FS,
108-
Reloc::Model RM)
108+
Reloc::Model RM, CodeModel::Model CM)
109109
: TargetMachine(T, Triple, CPU, FS) {
110-
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM);
110+
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
111111
AsmInfo = T.createMCAsmInfo(Triple);
112112
}
113113

114-
// Set the default code model for the JIT for a generic target.
115-
// FIXME: Is small right here? or .is64Bit() ? Large : Small?
116-
void LLVMTargetMachine::setCodeModelForJIT() {
117-
setCodeModel(CodeModel::Small);
118-
}
119-
120-
// Set the default code model for static compilation for a generic target.
121-
void LLVMTargetMachine::setCodeModelForStatic() {
122-
setCodeModel(CodeModel::Small);
123-
}
124-
125114
bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
126115
formatted_raw_ostream &Out,
127116
CodeGenFileType FileType,
@@ -201,8 +190,6 @@ bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
201190

202191
PM.add(Printer);
203192

204-
// Make sure the code model is set.
205-
setCodeModelForStatic();
206193
PM.add(createGCInfoDeleter());
207194
return false;
208195
}
@@ -217,9 +204,6 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
217204
JITCodeEmitter &JCE,
218205
CodeGenOpt::Level OptLevel,
219206
bool DisableVerify) {
220-
// Make sure the code model is set.
221-
setCodeModelForJIT();
222-
223207
// Add common CodeGen passes.
224208
MCContext *Ctx = 0;
225209
if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
@@ -273,9 +257,6 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
273257

274258
PM.add(Printer);
275259

276-
// Make sure the code model is set.
277-
setCodeModelForJIT();
278-
279260
return false; // success!
280261
}
281262

‎llvm/lib/ExecutionEngine/ExecutionEngine.cpp

+3-5
Original file line numberDiff line numberDiff line change
@@ -437,9 +437,8 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M,
437437
SmallVector<std::string, 1> MAttrs;
438438

439439
TargetMachine *TM =
440-
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr);
440+
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, CMM, ErrorStr);
441441
if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0;
442-
TM->setCodeModel(CMM);
443442

444443
return ExecutionEngine::JITCtor(M, ErrorStr, JMM, OptLevel, GVsWithCode, TM);
445444
}
@@ -467,9 +466,8 @@ ExecutionEngine *EngineBuilder::create() {
467466
// try making a JIT.
468467
if (WhichEngine & EngineKind::JIT) {
469468
if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs,
470-
RelocModel, ErrorStr)) {
471-
TM->setCodeModel(CMModel);
472-
469+
RelocModel, CMModel,
470+
ErrorStr)) {
473471
if (UseMCJIT && ExecutionEngine::MCJITCtor) {
474472
ExecutionEngine *EE =
475473
ExecutionEngine::MCJITCtor(M, ErrorStr, JMM, OptLevel,

‎llvm/lib/ExecutionEngine/JIT/JIT.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ class JIT : public ExecutionEngine {
101101
CodeGenOpt::Default,
102102
bool GVsWithCode = true,
103103
Reloc::Model RM = Reloc::Default,
104-
CodeModel::Model CMM = CodeModel::Default) {
104+
CodeModel::Model CMM = CodeModel::JITDefault) {
105105
return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode,
106106
RM, CMM);
107107
}

‎llvm/lib/ExecutionEngine/TargetSelect.cpp

+3-1
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
3131
StringRef MCPU,
3232
const SmallVectorImpl<std::string>& MAttrs,
3333
Reloc::Model RM,
34+
CodeModel::Model CM,
3435
std::string *ErrorStr) {
3536
Triple TheTriple(Mod->getTargetTriple());
3637
if (TheTriple.getTriple().empty())
@@ -85,7 +86,8 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
8586

8687
// Allocate a target...
8788
TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
88-
MCPU, FeaturesStr, RM);
89+
MCPU, FeaturesStr,
90+
RM, CM);
8991
assert(Target && "Could not allocate target machine!");
9092
return Target;
9193
}

‎llvm/lib/MC/MCCodeGenInfo.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "llvm/MC/MCCodeGenInfo.h"
1616
using namespace llvm;
1717

18-
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) {
18+
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM) {
1919
RelocationModel = RM;
20+
CMModel = CM;
2021
}

‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,8 @@ extern "C" void LLVMInitializeARMTarget() {
6464
///
6565
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
6666
StringRef CPU, StringRef FS,
67-
Reloc::Model RM)
68-
: LLVMTargetMachine(T, TT, CPU, FS, RM),
67+
Reloc::Model RM, CodeModel::Model CM)
68+
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
6969
Subtarget(TT, CPU, FS),
7070
JITInfo(),
7171
InstrItins(Subtarget.getInstrItineraryData()) {
@@ -76,8 +76,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
7676

7777
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
7878
StringRef CPU, StringRef FS,
79-
Reloc::Model RM)
80-
: ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget),
79+
Reloc::Model RM, CodeModel::Model CM)
80+
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
8181
DataLayout(Subtarget.isAPCS_ABI() ?
8282
std::string("e-p:32:32-f64:32:64-i64:32:64-"
8383
"v128:32:128-v64:32:64-n32") :
@@ -94,8 +94,8 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
9494

9595
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
9696
StringRef CPU, StringRef FS,
97-
Reloc::Model RM)
98-
: ARMBaseTargetMachine(T, TT, CPU, FS, RM),
97+
Reloc::Model RM, CodeModel::Model CM)
98+
: ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
9999
InstrInfo(Subtarget.hasThumb2()
100100
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
101101
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),

‎llvm/lib/Target/ARM/ARMTargetMachine.h

+6-3
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ class ARMBaseTargetMachine : public LLVMTargetMachine {
4040

4141
public:
4242
ARMBaseTargetMachine(const Target &T, StringRef TT,
43-
StringRef CPU, StringRef FS, Reloc::Model RM);
43+
StringRef CPU, StringRef FS,
44+
Reloc::Model RM, CodeModel::Model CM);
4445

4546
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
4647
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
@@ -69,7 +70,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
6970
ARMFrameLowering FrameLowering;
7071
public:
7172
ARMTargetMachine(const Target &T, StringRef TT,
72-
StringRef CPU, StringRef FS, Reloc::Model RM);
73+
StringRef CPU, StringRef FS,
74+
Reloc::Model RM, CodeModel::Model CM);
7375

7476
virtual const ARMRegisterInfo *getRegisterInfo() const {
7577
return &InstrInfo.getRegisterInfo();
@@ -108,7 +110,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine {
108110
OwningPtr<ARMFrameLowering> FrameLowering;
109111
public:
110112
ThumbTargetMachine(const Target &T, StringRef TT,
111-
StringRef CPU, StringRef FS, Reloc::Model RM);
113+
StringRef CPU, StringRef FS,
114+
Reloc::Model RM, CodeModel::Model CM);
112115

113116
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
114117
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -143,11 +143,12 @@ extern "C" void LLVMInitializeARMMCAsmInfo() {
143143
RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
144144
}
145145

146-
MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
146+
MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
147+
CodeModel::Model CM) {
147148
MCCodeGenInfo *X = new MCCodeGenInfo();
148149
if (RM == Reloc::Default)
149150
RM = Reloc::DynamicNoPIC;
150-
X->InitMCCodeGenInfo(RM);
151+
X->InitMCCodeGenInfo(RM, CM);
151152
return X;
152153
}
153154

‎llvm/lib/Target/Alpha/AlphaTargetMachine.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,9 @@ extern "C" void LLVMInitializeAlphaTarget() {
2323
}
2424

2525
AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT,
26-
StringRef CPU,
27-
StringRef FS, Reloc::Model RM)
28-
: LLVMTargetMachine(T, TT, CPU, FS, RM),
26+
StringRef CPU, StringRef FS,
27+
Reloc::Model RM, CodeModel::Model CM)
28+
: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
2929
DataLayout("e-f128:128:128-n64"),
3030
FrameLowering(Subtarget),
3131
Subtarget(TT, CPU, FS),

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