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[WebAssembly] Add simd128-unimplemented subtarget feature
This is a second attempt at r350778, which was reverted in r350789. The only change is that the unimplemented-simd128 feature has been renamed simd128-unimplemented, since naming it unimplemented-simd128 somehow made the simd128 feature flag enable the unimplemented-simd128 feature on Windows. llvm-svn: 350791
1 parent 4d9ecaa commit eb6f9ab

21 files changed

+88
-82
lines changed

‎llvm/lib/Target/WebAssembly/WebAssembly.td

+7
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,13 @@ include "llvm/Target/Target.td"
2525

2626
def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true",
2727
"Enable 128-bit SIMD">;
28+
29+
def FeatureSIMD128Unimplemented :
30+
SubtargetFeature<"simd128-unimplemented",
31+
"HasSIMD128Unimplemented", "true",
32+
"Enable 128-bit SIMD not yet implemented in engines",
33+
[FeatureSIMD128]>;
34+
2835
def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
2936
"Enable Atomics">;
3037
def FeatureNontrappingFPToInt :

‎llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

+1-3
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,6 @@ using namespace PatternMatch;
4444

4545
#define DEBUG_TYPE "wasm-fastisel"
4646

47-
extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
48-
4947
namespace {
5048

5149
class WebAssemblyFastISel final : public FastISel {
@@ -145,7 +143,7 @@ class WebAssemblyFastISel final : public FastISel {
145143
break;
146144
case MVT::v2i64:
147145
case MVT::v2f64:
148-
if (Subtarget->hasSIMD128() && EnableUnimplementedWasmSIMDInstrs)
146+
if (Subtarget->hasSIMD128Unimplemented())
149147
return VT;
150148
break;
151149
default:

‎llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp

-2
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,6 @@ using namespace llvm;
2525

2626
#define DEBUG_TYPE "wasm-isel"
2727

28-
extern cl::opt<bool> EnableUnimplementedWasmSIMDInstrs;
29-
3028
//===--------------------------------------------------------------------===//
3129
/// WebAssembly-specific code to select WebAssembly machine instructions for
3230
/// SelectionDAG operations.

‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

+28-14
Original file line numberDiff line numberDiff line change
@@ -37,12 +37,6 @@ using namespace llvm;
3737

3838
#define DEBUG_TYPE "wasm-lower"
3939

40-
// Emit proposed instructions that may not have been implemented in engines
41-
cl::opt<bool> EnableUnimplementedWasmSIMDInstrs(
42-
"wasm-enable-unimplemented-simd",
43-
cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"),
44-
cl::init(false));
45-
4640
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
4741
const TargetMachine &TM, const WebAssemblySubtarget &STI)
4842
: TargetLowering(TM), Subtarget(&STI) {
@@ -70,7 +64,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
7064
addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
7165
addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
7266
addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
73-
if (EnableUnimplementedWasmSIMDInstrs) {
67+
if (Subtarget->hasSIMD128Unimplemented()) {
7468
addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
7569
addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
7670
}
@@ -135,7 +129,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
135129
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) {
136130
setOperationAction(Op, T, Expand);
137131
}
138-
if (EnableUnimplementedWasmSIMDInstrs) {
132+
if (Subtarget->hasSIMD128Unimplemented()) {
139133
setOperationAction(Op, MVT::v2i64, Expand);
140134
}
141135
}
@@ -149,7 +143,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
149143
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32}) {
150144
setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
151145
}
152-
if (EnableUnimplementedWasmSIMDInstrs) {
146+
if (Subtarget->hasSIMD128Unimplemented()) {
153147
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
154148
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
155149
}
@@ -160,7 +154,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
160154
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
161155
for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
162156
setOperationAction(Op, T, Custom);
163-
if (EnableUnimplementedWasmSIMDInstrs)
157+
if (Subtarget->hasSIMD128Unimplemented())
164158
for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
165159
setOperationAction(Op, MVT::v2i64, Custom);
166160
}
@@ -170,7 +164,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
170164
for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
171165
for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
172166
setOperationAction(Op, T, Expand);
173-
if (EnableUnimplementedWasmSIMDInstrs)
167+
if (Subtarget->hasSIMD128Unimplemented())
174168
for (auto T : {MVT::v2i64, MVT::v2f64})
175169
setOperationAction(Op, T, Expand);
176170
}
@@ -179,8 +173,10 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
179173
// sign-extend from.
180174
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
181175
if (!Subtarget->hasSignExt()) {
176+
// Sign extends are legal only when extending a vector extract
177+
auto Action = Subtarget->hasSIMD128() ? Custom : Expand;
182178
for (auto T : {MVT::i8, MVT::i16, MVT::i32})
183-
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
179+
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action);
184180
}
185181
for (auto T : MVT::integer_vector_valuetypes())
186182
setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
@@ -225,7 +221,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
225221
}
226222

227223
// Expand additional SIMD ops that V8 hasn't implemented yet
228-
if (Subtarget->hasSIMD128() && !EnableUnimplementedWasmSIMDInstrs) {
224+
if (Subtarget->hasSIMD128() && !Subtarget->hasSIMD128Unimplemented()) {
229225
setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
230226
setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
231227
}
@@ -236,7 +232,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
236232
setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
237233
setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
238234
}
239-
if (EnableUnimplementedWasmSIMDInstrs) {
235+
if (Subtarget->hasSIMD128Unimplemented()) {
240236
for (auto T : {MVT::v2i64, MVT::v2f64}) {
241237
setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom);
242238
setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom);
@@ -900,6 +896,8 @@ SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
900896
return LowerAccessVectorElement(Op, DAG);
901897
case ISD::INTRINSIC_VOID:
902898
return LowerINTRINSIC_VOID(Op, DAG);
899+
case ISD::SIGN_EXTEND_INREG:
900+
return LowerSIGN_EXTEND_INREG(Op, DAG);
903901
case ISD::VECTOR_SHUFFLE:
904902
return LowerVECTOR_SHUFFLE(Op, DAG);
905903
case ISD::SHL:
@@ -1101,6 +1099,22 @@ WebAssemblyTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
11011099
}
11021100
}
11031101

1102+
SDValue
1103+
WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1104+
SelectionDAG &DAG) const {
1105+
// If sign extension operations are disabled, allow sext_inreg only if operand
1106+
// is a vector extract. SIMD does not depend on sign extension operations, but
1107+
// allowing sext_inreg in this context lets us have simple patterns to select
1108+
// extract_lane_s instructions. Expanding sext_inreg everywhere would be
1109+
// simpler in this file, but would necessitate large and brittle patterns to
1110+
// undo the expansion and select extract_lane_s instructions.
1111+
assert(!Subtarget->hasSignExt() && Subtarget->hasSIMD128());
1112+
if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT)
1113+
return Op;
1114+
// Otherwise expand
1115+
return SDValue();
1116+
}
1117+
11041118
SDValue
11051119
WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
11061120
SelectionDAG &DAG) const {

‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h

+1
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@ class WebAssemblyTargetLowering final : public TargetLowering {
9999
SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
100100
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
101101
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
102+
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
102103
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
103104
SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
104105
SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

+3-1
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,9 @@ def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
2020
def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
2121
def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
2222
AssemblerPredicate<"FeatureSIMD128", "simd128">;
23-
def HasUnimplementedSIMD : Predicate<"EnableUnimplementedWasmSIMDInstrs">;
23+
def HasUnimplementedSIMD :
24+
Predicate<"Subtarget->hasSIMD128Unimplemented()">,
25+
AssemblerPredicate<"FeatureSIMD128Unimplemented", "simd128-unimplemented">;
2426
def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
2527
AssemblerPredicate<"FeatureAtomics", "atomics">;
2628
def HasNontrappingFPToInt :

‎llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h

+2
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ namespace llvm {
3030

3131
class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
3232
bool HasSIMD128;
33+
bool HasSIMD128Unimplemented;
3334
bool HasAtomics;
3435
bool HasNontrappingFPToInt;
3536
bool HasSignExt;
@@ -78,6 +79,7 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
7879
// Predicates used by WebAssemblyInstrInfo.td.
7980
bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
8081
bool hasSIMD128() const { return HasSIMD128; }
82+
bool hasSIMD128Unimplemented() const { return HasSIMD128Unimplemented; }
8183
bool hasAtomics() const { return HasAtomics; }
8284
bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; }
8385
bool hasSignExt() const { return HasSignExt; }

‎llvm/test/CodeGen/WebAssembly/simd-arith.ll

+20-36
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
1-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
2-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
1+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-SLOW
2+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128,SIMD128-FAST
33
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
44
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
5-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
6-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
5+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s --check-prefixes CHECK,NO-SIMD128
6+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
77

88
; check that a non-test run (including explicit locals pass) at least finishes
9-
; RUN: llc < %s -O0 -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext
10-
; RUN: llc < %s -O2 -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext
9+
; RUN: llc < %s -O0 -mattr=+simd128-unimplemented
10+
; RUN: llc < %s -O2 -mattr=+simd128-unimplemented
1111

1212
; Test that basic SIMD128 arithmetic operations assemble as expected.
1313

@@ -122,22 +122,14 @@ define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) {
122122
; NO-SIMD128-NOT: i8x16
123123
; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}}
124124
; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
125-
; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 24{{$}}
126-
; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
127-
; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 24{{$}}
128-
; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
129-
; SIMD128-NEXT: i8x16.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
130-
; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
131-
; SIMD128-NEXT: i8x16.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}
125+
; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
126+
; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
127+
; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
132128
; Skip 14 lanes
133-
; SIMD128: i8x16.extract_lane_s $push[[L7:[0-9]+]]=, $0, 15{{$}}
134-
; SIMD128-NEXT: i32.const $push[[L8:[0-9]+]]=, 24{{$}}
135-
; SIMD128-NEXT: i32.shl $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
136-
; SIMD128-NEXT: i32.const $push[[L10:[0-9]+]]=, 24{{$}}
137-
; SIMD128-NEXT: i32.shr_s $push[[L11:[0-9]+]]=, $pop[[L9]], $pop[[L10]]{{$}}
138-
; SIMD128-NEXT: i8x16.extract_lane_u $push[[L12:[0-9]+]]=, $1, 15{{$}}
139-
; SIMD128-NEXT: i32.shr_s $push[[L13:[0-9]+]]=, $pop[[L11]], $pop[[L12]]{{$}}
140-
; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop[[L14:[0-9]+]], 15, $pop[[L13]]{{$}}
129+
; SIMD128: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 15{{$}}
130+
; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 15{{$}}
131+
; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
132+
; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $pop{{[0-9]+}}, 15, $pop[[L2]]{{$}}
141133
; SIMD128-NEXT: return $pop[[R]]{{$}}
142134
define <16 x i8> @shr_s_vec_v16i8(<16 x i8> %v, <16 x i8> %x) {
143135
%a = ashr <16 x i8> %v, %x
@@ -343,22 +335,14 @@ define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) {
343335
; NO-SIMD128-NOT: i16x8
344336
; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}}
345337
; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
346-
; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
347-
; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
348-
; SIMD128-NEXT: i32.const $push[[L3:[0-9]+]]=, 16{{$}}
349-
; SIMD128-NEXT: i32.shr_s $push[[L4:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
350-
; SIMD128-NEXT: i16x8.extract_lane_u $push[[L5:[0-9]+]]=, $1, 0{{$}}
351-
; SIMD128-NEXT: i32.shr_s $push[[L6:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
352-
; SIMD128-NEXT: i16x8.splat $push[[L7:[0-9]+]]=, $pop[[L6]]{{$}}
338+
; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
339+
; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
340+
; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
353341
; Skip 6 lanes
354-
; SIMD128: i16x8.extract_lane_s $push[[L7:[0-9]+]]=, $0, 7{{$}}
355-
; SIMD128-NEXT: i32.const $push[[L8:[0-9]+]]=, 16{{$}}
356-
; SIMD128-NEXT: i32.shl $push[[L9:[0-9]+]]=, $pop[[L7]], $pop[[L8]]{{$}}
357-
; SIMD128-NEXT: i32.const $push[[L10:[0-9]+]]=, 16{{$}}
358-
; SIMD128-NEXT: i32.shr_s $push[[L11:[0-9]+]]=, $pop[[L9]], $pop[[L10]]{{$}}
359-
; SIMD128-NEXT: i16x8.extract_lane_u $push[[L12:[0-9]+]]=, $1, 7{{$}}
360-
; SIMD128-NEXT: i32.shr_s $push[[L13:[0-9]+]]=, $pop[[L11]], $pop[[L12]]{{$}}
361-
; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop[[L14:[0-9]+]], 7, $pop[[L13]]{{$}}
342+
; SIMD128: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 7{{$}}
343+
; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 7{{$}}
344+
; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
345+
; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $pop{{[0-9]+}}, 7, $pop[[L2]]{{$}}
362346
; SIMD128-NEXT: return $pop[[R]]{{$}}
363347
define <8 x i16> @shr_s_vec_v8i16(<8 x i16> %v, <8 x i16> %x) {
364348
%a = ashr <8 x i16> %v, %x

‎llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
2-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
1+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
2+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
44

55
; Test that bitcasts between vector types are lowered to zero instructions
66

‎llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
2-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
1+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
2+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
44

55
; Test SIMD comparison operators
66

‎llvm/test/CodeGen/WebAssembly/simd-conversions.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
2-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
1+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128-unimplemented | FileCheck %s --check-prefixes CHECK,SIMD128
2+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -wasm-keep-registers -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
44

55
; Test that vector float-to-int and int-to-float instructions lower correctly
66

‎llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s
1+
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128-unimplemented | FileCheck %s
22

33
; Check that store in memory with smaller lanes are loaded and stored
44
; as expected. This is a regression test for part of bug 39275.

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