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Commit e9119e4

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Jim Grosbach
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MC: Modernize MCOperand API naming. NFC.
MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
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55 files changed

+1190
-1191
lines changed

‎llvm/include/llvm/MC/MCInst.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -108,31 +108,31 @@ class MCOperand {
108108
InstVal = Val;
109109
}
110110

111-
static MCOperand CreateReg(unsigned Reg) {
111+
static MCOperand createReg(unsigned Reg) {
112112
MCOperand Op;
113113
Op.Kind = kRegister;
114114
Op.RegVal = Reg;
115115
return Op;
116116
}
117-
static MCOperand CreateImm(int64_t Val) {
117+
static MCOperand createImm(int64_t Val) {
118118
MCOperand Op;
119119
Op.Kind = kImmediate;
120120
Op.ImmVal = Val;
121121
return Op;
122122
}
123-
static MCOperand CreateFPImm(double Val) {
123+
static MCOperand createFPImm(double Val) {
124124
MCOperand Op;
125125
Op.Kind = kFPImmediate;
126126
Op.FPImmVal = Val;
127127
return Op;
128128
}
129-
static MCOperand CreateExpr(const MCExpr *Val) {
129+
static MCOperand createExpr(const MCExpr *Val) {
130130
MCOperand Op;
131131
Op.Kind = kExpr;
132132
Op.ExprVal = Val;
133133
return Op;
134134
}
135-
static MCOperand CreateInst(const MCInst *Val) {
135+
static MCOperand createInst(const MCInst *Val) {
136136
MCOperand Op;
137137
Op.Kind = kInst;
138138
Op.InstVal = Val;

‎llvm/include/llvm/MC/MCInstBuilder.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -30,31 +30,31 @@ class MCInstBuilder {
3030

3131
/// \brief Add a new register operand.
3232
MCInstBuilder &addReg(unsigned Reg) {
33-
Inst.addOperand(MCOperand::CreateReg(Reg));
33+
Inst.addOperand(MCOperand::createReg(Reg));
3434
return *this;
3535
}
3636

3737
/// \brief Add a new integer immediate operand.
3838
MCInstBuilder &addImm(int64_t Val) {
39-
Inst.addOperand(MCOperand::CreateImm(Val));
39+
Inst.addOperand(MCOperand::createImm(Val));
4040
return *this;
4141
}
4242

4343
/// \brief Add a new floating point immediate operand.
4444
MCInstBuilder &addFPImm(double Val) {
45-
Inst.addOperand(MCOperand::CreateFPImm(Val));
45+
Inst.addOperand(MCOperand::createFPImm(Val));
4646
return *this;
4747
}
4848

4949
/// \brief Add a new MCExpr operand.
5050
MCInstBuilder &addExpr(const MCExpr *Val) {
51-
Inst.addOperand(MCOperand::CreateExpr(Val));
51+
Inst.addOperand(MCOperand::createExpr(Val));
5252
return *this;
5353
}
5454

5555
/// \brief Add a new MCInst operand.
5656
MCInstBuilder &addInst(const MCInst *Val) {
57-
Inst.addOperand(MCOperand::CreateInst(Val));
57+
Inst.addOperand(MCOperand::createInst(Val));
5858
return *this;
5959
}
6060

‎llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ bool MCExternalSymbolizer::tryAddingSymbolicOperand(MCInst &MI,
136136
if (!Expr)
137137
return false;
138138

139-
MI.addOperand(MCOperand::CreateExpr(Expr));
139+
MI.addOperand(MCOperand::createExpr(Expr));
140140
return true;
141141
}
142142

‎llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

+9-9
Original file line numberDiff line numberDiff line change
@@ -467,7 +467,7 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
467467
case AArch64::TCRETURNri: {
468468
MCInst TmpInst;
469469
TmpInst.setOpcode(AArch64::BR);
470-
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
470+
TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
471471
EmitToStreamer(*OutStreamer, TmpInst);
472472
return;
473473
}
@@ -500,24 +500,24 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
500500

501501
MCInst Adrp;
502502
Adrp.setOpcode(AArch64::ADRP);
503-
Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
503+
Adrp.addOperand(MCOperand::createReg(AArch64::X0));
504504
Adrp.addOperand(SymTLSDesc);
505505
EmitToStreamer(*OutStreamer, Adrp);
506506

507507
MCInst Ldr;
508508
Ldr.setOpcode(AArch64::LDRXui);
509-
Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
510-
Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
509+
Ldr.addOperand(MCOperand::createReg(AArch64::X1));
510+
Ldr.addOperand(MCOperand::createReg(AArch64::X0));
511511
Ldr.addOperand(SymTLSDescLo12);
512-
Ldr.addOperand(MCOperand::CreateImm(0));
512+
Ldr.addOperand(MCOperand::createImm(0));
513513
EmitToStreamer(*OutStreamer, Ldr);
514514

515515
MCInst Add;
516516
Add.setOpcode(AArch64::ADDXri);
517-
Add.addOperand(MCOperand::CreateReg(AArch64::X0));
518-
Add.addOperand(MCOperand::CreateReg(AArch64::X0));
517+
Add.addOperand(MCOperand::createReg(AArch64::X0));
518+
Add.addOperand(MCOperand::createReg(AArch64::X0));
519519
Add.addOperand(SymTLSDescLo12);
520-
Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
520+
Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
521521
EmitToStreamer(*OutStreamer, Add);
522522

523523
// Emit a relocation-annotation. This expands to no code, but requests
@@ -529,7 +529,7 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
529529

530530
MCInst Blr;
531531
Blr.setOpcode(AArch64::BLR);
532-
Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
532+
Blr.addOperand(MCOperand::createReg(AArch64::X1));
533533
EmitToStreamer(*OutStreamer, Blr);
534534

535535
return;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -2366,7 +2366,7 @@ bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
23662366

23672367
void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
23682368
NopInst.setOpcode(AArch64::HINT);
2369-
NopInst.addOperand(MCOperand::CreateImm(0));
2369+
NopInst.addOperand(MCOperand::createImm(0));
23702370
}
23712371
/// useMachineCombiner - return true when a target supports MachineCombiner
23722372
bool AArch64InstrInfo::useMachineCombiner() const {

‎llvm/lib/Target/AArch64/AArch64MCInstLower.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO,
7373
if (!MO.isJTI() && MO.getOffset())
7474
Expr = MCBinaryExpr::CreateAdd(
7575
Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), Ctx);
76-
return MCOperand::CreateExpr(Expr);
76+
return MCOperand::createExpr(Expr);
7777
}
7878

7979
MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
@@ -148,7 +148,7 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
148148
RefKind = static_cast<AArch64MCExpr::VariantKind>(RefFlags);
149149
Expr = AArch64MCExpr::Create(Expr, RefKind, Ctx);
150150

151-
return MCOperand::CreateExpr(Expr);
151+
return MCOperand::createExpr(Expr);
152152
}
153153

154154
MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
@@ -169,16 +169,16 @@ bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
169169
// Ignore all implicit register operands.
170170
if (MO.isImplicit())
171171
return false;
172-
MCOp = MCOperand::CreateReg(MO.getReg());
172+
MCOp = MCOperand::createReg(MO.getReg());
173173
break;
174174
case MachineOperand::MO_RegisterMask:
175175
// Regmasks are like implicit defs.
176176
return false;
177177
case MachineOperand::MO_Immediate:
178-
MCOp = MCOperand::CreateImm(MO.getImm());
178+
MCOp = MCOperand::createImm(MO.getImm());
179179
break;
180180
case MachineOperand::MO_MachineBasicBlock:
181-
MCOp = MCOperand::CreateExpr(
181+
MCOp = MCOperand::createExpr(
182182
MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), Ctx));
183183
break;
184184
case MachineOperand::MO_GlobalAddress:

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