[AMDGPU][MC][DOC] Updated AMD GPU assembler description.

Minor bugfixing and improvements.

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 350120

Author: dpreobra

llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst

@@ -12,6 +12,6 @@ fx
 
 This is an *f32* or *f16* operand depending on instruction modifiers:
 
-* Operand size is controlled by :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
-* Location of 16-bit operand is controlled by :ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
 

llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst

@@ -12,8 +12,8 @@ vaddr
 
 A 64-bit flat global address or a 32-bit offset depending on addressing mode:
 
-* Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`flat_offset13<amdgpu_synid_flat_offset13>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
-* Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`flat_offset13<amdgpu_synid_flat_offset13>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
+* Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
 
 .. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
 

llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst

@@ -73,7 +73,7 @@ Where:
     :dst           An input operand which may also serve as a destination
                    if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
     :fx            This is an *f32* or *f16* operand depending on
-                   :ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
+                   :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
     :<type>        Operand *type* differs from *type*
                    :ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
                    This tag specifies actual operand *type*.

llvm/docs/AMDGPU/gfx9_mad_type_dev.rst

@@ -27,8 +27,8 @@ DS Modifiers
 
 .. _amdgpu_synid_ds_offset8:
 
-ds_offset8
-~~~~~~~~~~
+offset8
+~~~~~~~
 
 Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.
 
@@ -50,8 +50,8 @@ Examples:
 
 .. _amdgpu_synid_ds_offset16:
 
-ds_offset16
-~~~~~~~~~~~
+offset16
+~~~~~~~~
 
 Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.
 
@@ -73,8 +73,8 @@ Examples:
 
 .. _amdgpu_synid_sw_offset16:
 
-sw_offset16
-~~~~~~~~~~~
+pattern
+~~~~~~~
 
 This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
 It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.
@@ -205,8 +205,8 @@ FLAT Modifiers
 
 .. _amdgpu_synid_flat_offset12:
 
-flat_offset12
-~~~~~~~~~~~~~
+offset12
+~~~~~~~~
 
 Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
 
@@ -226,10 +226,10 @@ Examples:
   offset:4095
   offset:0xff
 
-.. _amdgpu_synid_flat_offset13:
+.. _amdgpu_synid_flat_offset13s:
 
-flat_offset13
-~~~~~~~~~~~~~
+offset13s
+~~~~~~~~~
 
 Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
 
@@ -238,7 +238,7 @@ Can be used with *global/scratch* opcodes only. GFX9 only.
     ============================ =======================================================
     Syntax                       Description
     ============================ =======================================================
-    offset:{-4096..+4095}        Specifies a 13-bit signed offset as an
+    offset:{-4096..4095}         Specifies a 13-bit signed offset as an
                                  :ref:`integer number <amdgpu_synid_integer_number>`.
     ============================ =======================================================
 
@@ -353,7 +353,7 @@ GFX7 and GFX8 only.
     r128                Specifies 128 bits texture resource size.
     =================== ================================================
 
-.. WARNING:: Using this modifier should descrease *rsrc* register size from 8 to 4 dwords, but assembler does not currently support this feature.
+.. WARNING:: Using this modifier should descrease *rsrc* operand size from 8 to 4 dwords, but assembler does not currently support this feature.
 
 tfe
 ~~~
@@ -545,8 +545,8 @@ GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
 
 .. _amdgpu_synid_buf_offset12:
 
-buf_offset12
-~~~~~~~~~~~~
+offset12
+~~~~~~~~
 
 Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
 
@@ -889,8 +889,8 @@ VOP3 Modifiers
 
 .. _amdgpu_synid_vop3_op_sel:
 
-vop3_op_sel
-~~~~~~~~~~~
+op_sel
+~~~~~~
 
 Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
 By default, low bits are used for all operands.
@@ -1177,11 +1177,11 @@ GFX9 only.
 
 .. _amdgpu_synid_mad_mix_op_sel:
 
-mad_mix_op_sel
-~~~~~~~~~~~~~~
+m_op_sel
+~~~~~~~~
 
 This operand has meaning only for 16-bit source operands as indicated by
-:ref:`mad_mix_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
+:ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 It specifies to select either the low [15:0] or high [31:16] operand bits
 as input to the operation.
 
@@ -1206,8 +1206,8 @@ Examples:
 
 .. _amdgpu_synid_mad_mix_op_sel_hi:
 
-mad_mix_op_sel_hi
-~~~~~~~~~~~~~~~~~
+m_op_sel_hi
+~~~~~~~~~~~
 
 Selects the size of source operands: either 32 bits or 16 bits.
 By default, 32 bits are used for all source operands.
@@ -1218,7 +1218,7 @@ operands. First value controls src0, second value controls src1 and so on.
 The value 0 indicates 32 bits, the value 1 indicates 16 bits.
 
 The location of 16 bits in the operand may be specified by
-:ref:`mad_mix_op_sel<amdgpu_synid_mad_mix_op_sel>`.
+:ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
 
     ======================================== ====================================
     Syntax                                   Description

llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst

@@ -950,13 +950,13 @@ When used as operands they are converted to
     ============== ============== =============== ====================================================================
     Expected type  Condition      Result          Note
     ============== ============== =============== ====================================================================
-    i16, u16, b16  cond(num, 16)  num.u16         Truncate to 16 bits.
-    i32, u32, b32  cond(num, 32)  num.u32         Truncate to 32 bits.
-    i64            cond(num, 32)  {-1, num.i32}   Truncate to 32 bits and then sign-extend the result to 64 bits.
-    u64, b64       cond(num, 32)  { 0, num.u32}   Truncate to 32 bits and then zero-extend the result to 64 bits.
-    f16            cond(num, 16)  num.u16         Use low 16 bits as an f16 value.
-    f32            cond(num, 32)  num.u32         Use low 32 bits as an f32 value.
-    f64            cond(num, 32)  {num.u32, 0}    Use low 32 bits of the number as high 32 bits
+    i16, u16, b16  cond(num,16)   num.u16         Truncate to 16 bits.
+    i32, u32, b32  cond(num,32)   num.u32         Truncate to 32 bits.
+    i64            cond(num,32)   {-1,num.i32}    Truncate to 32 bits and then sign-extend the result to 64 bits.
+    u64, b64       cond(num,32)   { 0,num.u32}    Truncate to 32 bits and then zero-extend the result to 64 bits.
+    f16            cond(num,16)   num.u16         Use low 16 bits as an f16 value.
+    f32            cond(num,32)   num.u32         Use low 32 bits as an f32 value.
+    f64            cond(num,32)   {num.u32,0}     Use low 32 bits of the number as high 32 bits
                                                   of the result; low 32 bits of the result are zeroed.
     ============== ============== =============== ====================================================================
 
@@ -972,23 +972,23 @@ Examples of valid literals:
 .. parsed-literal::
 
     // GFX9
-
-    v_add_u16 v0, 0xff00, v0                     // value after conversion: 0xff00
-    v_add_u16 v0, 0xffffffffffffff00, v0         // value after conversion: 0xff00
-    v_add_u16 v0, -256, v0                       // value after conversion: 0xff00
-
-    s_bfe_i64 s[0:1], 0xffefffff, s3             // value after conversion: 0xffffffffffefffff
-    s_bfe_u64 s[0:1], 0xffefffff, s3             // value after conversion: 0x00000000ffefffff
-    v_ceil_f64_e32 v[0:1], 0xffefffff            // value after conversion: 0xffefffff00000000 (-1.7976922776554302e308)
+                                             // Literal value after conversion:
+    v_add_u16 v0, 0xff00, v0                 //   0xff00
+    v_add_u16 v0, 0xffffffffffffff00, v0     //   0xff00
+    v_add_u16 v0, -256, v0                   //   0xff00
+                                             // Literal value after conversion:
+    s_bfe_i64 s[0:1], 0xffefffff, s3         //   0xffffffffffefffff
+    s_bfe_u64 s[0:1], 0xffefffff, s3         //   0x00000000ffefffff
+    v_ceil_f64_e32 v[0:1], 0xffefffff        //   0xffefffff00000000 (-1.7976922776554302e308)
 
 Examples of invalid literals:
 
 .. parsed-literal::
 
     // GFX9
 
-    v_add_u16 v0, 0x1ff00, v0               // conversion is not possible as truncated bits are not all 0 or 1
-    v_add_u16 v0, 0xffffffffffff00ff, v0    // conversion is not possible as truncated bits do not match MSB of the result
+    v_add_u16 v0, 0x1ff00, v0               // truncated bits are not all 0 or 1
+    v_add_u16 v0, 0xffffffffffff00ff, v0    // truncated bits do not match MSB of the result
 
 .. _amdgpu_synid_fp_lit_conv:
 
@@ -1004,12 +1004,12 @@ When used as operands they are converted to
     ============== ============== ================= =================================================================
     Expected type  Condition      Result            Note
     ============== ============== ================= =================================================================
-    i16, u16, b16  cond(num, 16)  f16(num)          Convert to f16 and use bits of the result as an integer value.
-    i32, u32, b32  cond(num, 32)  f32(num)          Convert to f32 and use bits of the result as an integer value.
+    i16, u16, b16  cond(num,16)   f16(num)          Convert to f16 and use bits of the result as an integer value.
+    i32, u32, b32  cond(num,32)   f32(num)          Convert to f32 and use bits of the result as an integer value.
     i64, u64, b64  false          \-                Conversion disabled because of an unclear semantics.
-    f16            cond(num, 16)  f16(num)          Convert to f16.
-    f32            cond(num, 32)  f32(num)          Convert to f32.
-    f64            true           {num.u32.hi, 0}   Use high 32 bits of the number as high 32 bits of the result;
+    f16            cond(num,16)   f16(num)          Convert to f16.
+    f32            cond(num,32)   f32(num)          Convert to f32.
+    f64            true           {num.u32.hi,0}    Use high 32 bits of the number as high 32 bits of the result;
                                                     zero-fill low 32 bits of the result.
 
                                                     Note that the result may differ from the original number.
@@ -1028,16 +1028,17 @@ Examples of valid literals:
     v_add_f16 v1, 65500.0, v2
     v_add_f32 v1, 65600.0, v2
 
-                                                 // value before conversion: 0x7fefffffffffffff (1.7976931348623157e308)
-    v_ceil_f64 v[0:1], 1.7976931348623157e308    // value after conversion:  0x7fefffff00000000 (1.7976922776554302e308)
+    // Literal value before conversion: 1.7976931348623157e308 (0x7fefffffffffffff)
+    // Literal value after conversion:  1.7976922776554302e308 (0x7fefffff00000000)
+    v_ceil_f64 v[0:1], 1.7976931348623157e308
 
 Examples of invalid literals:
 
 .. parsed-literal::
 
     // GFX9
 
-    v_add_f16 v1, 65600.0, v2                    // cannot be converted to f16 because of overflow
+    v_add_f16 v1, 65600.0, v2    // overflow
 
 .. _amdgpu_synid_exp_conv: