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Evan Cheng
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Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc. llvm-svn: 133922
1 parent 1e256d2 commit d9997ac

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71 files changed

+295
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lines changed

‎llvm/lib/Target/ARM/ARMBaseInfo.h

+2-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,8 @@
2525
// Defines symbolic names for ARM registers. This defines a mapping from
2626
// register name to register number.
2727
//
28-
#include "ARMGenRegisterNames.inc"
28+
#define GET_REGINFO_ENUM
29+
#include "ARMGenRegisterInfo.inc"
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3031
// Defines symbolic names for the ARM instructions.
3132
//

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

+3-1
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@@ -39,7 +39,9 @@
3939
#include "llvm/ADT/BitVector.h"
4040
#include "llvm/ADT/SmallVector.h"
4141
#include "llvm/Support/CommandLine.h"
42-
#include "ARMGenRegisterDesc.inc"
42+
43+
#define GET_REGINFO_MC_DESC
44+
#define GET_REGINFO_TARGET_DESC
4345
#include "ARMGenRegisterInfo.inc"
4446

4547
using namespace llvm;

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

+3-1
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@@ -16,7 +16,9 @@
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1717
#include "ARM.h"
1818
#include "llvm/Target/TargetRegisterInfo.h"
19-
#include "ARMGenRegisterInfo.h.inc"
19+
20+
#define GET_REGINFO_HEADER
21+
#include "ARMGenRegisterInfo.inc"
2022

2123
namespace llvm {
2224
class ARMSubtarget;

‎llvm/lib/Target/ARM/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
11
set(LLVM_TARGET_DEFINITIONS ARM.td)
22

3-
tablegen(ARMGenRegisterNames.inc -gen-register-enums)
4-
tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
5-
tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
63
tablegen(ARMGenRegisterInfo.inc -gen-register-info)
74
tablegen(ARMGenInstrNames.inc -gen-instr-enums)
85
tablegen(ARMGenInstrInfo.inc -gen-instr-desc)

‎llvm/lib/Target/ARM/Makefile

+1-2
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,7 @@ LIBRARYNAME = LLVMARMCodeGen
1212
TARGET = ARM
1313

1414
# Make sure that tblgen is run, first thing.
15-
BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
16-
ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
15+
BUILT_SOURCES = ARMGenRegisterInfo.inc \
1716
ARMGenInstrNames.inc ARMGenInstrInfo.inc \
1817
ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
1918
ARMGenDAGISel.inc ARMGenSubtarget.inc \

‎llvm/lib/Target/Alpha/Alpha.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,9 @@ namespace llvm {
4444
// Defines symbolic names for Alpha registers. This defines a mapping from
4545
// register name to register number.
4646
//
47-
#include "AlphaGenRegisterNames.inc"
47+
48+
#define GET_REGINFO_ENUM
49+
#include "AlphaGenRegisterInfo.inc"
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4951
// Defines symbolic names for the Alpha instructions.
5052
//

‎llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -33,8 +33,11 @@
3333
#include "llvm/ADT/BitVector.h"
3434
#include "llvm/ADT/STLExtras.h"
3535
#include <cstdlib>
36-
#include "AlphaGenRegisterDesc.inc"
36+
37+
#define GET_REGINFO_MC_DESC
38+
#define GET_REGINFO_TARGET_DESC
3739
#include "AlphaGenRegisterInfo.inc"
40+
3841
using namespace llvm;
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4043
AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)

‎llvm/lib/Target/Alpha/AlphaRegisterInfo.h

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@@ -15,7 +15,9 @@
1515
#define ALPHAREGISTERINFO_H
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1717
#include "llvm/Target/TargetRegisterInfo.h"
18-
#include "AlphaGenRegisterInfo.h.inc"
18+
19+
#define GET_REGINFO_HEADER
20+
#include "AlphaGenRegisterInfo.inc"
1921

2022
namespace llvm {
2123

‎llvm/lib/Target/Alpha/CMakeLists.txt

-3
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
11
set(LLVM_TARGET_DEFINITIONS Alpha.td)
22

3-
tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
4-
tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
5-
tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
63
tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
74
tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
85
tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)

‎llvm/lib/Target/Alpha/Makefile

+1-2
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,7 @@ LIBRARYNAME = LLVMAlphaCodeGen
1212
TARGET = Alpha
1313

1414
# Make sure that tblgen is run, first thing.
15-
BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
16-
AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
15+
BUILT_SOURCES = AlphaGenRegisterInfo.inc \
1716
AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
1817
AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1918
AlphaGenCallingConv.inc AlphaGenSubtarget.inc

‎llvm/lib/Target/Blackfin/Blackfin.h

+2-1
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@@ -30,7 +30,8 @@ namespace llvm {
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3131
// Defines symbolic names for Blackfin registers. This defines a mapping from
3232
// register name to register number.
33-
#include "BlackfinGenRegisterNames.inc"
33+
#define GET_REGINFO_ENUM
34+
#include "BlackfinGenRegisterInfo.inc"
3435

3536
// Defines symbolic names for the Blackfin instructions.
3637
#include "BlackfinGenInstrNames.inc"

‎llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp

+4-1
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@@ -29,8 +29,11 @@
2929
#include "llvm/Type.h"
3030
#include "llvm/ADT/BitVector.h"
3131
#include "llvm/ADT/STLExtras.h"
32-
#include "BlackfinGenRegisterDesc.inc"
32+
33+
#define GET_REGINFO_MC_DESC
34+
#define GET_REGINFO_TARGET_DESC
3335
#include "BlackfinGenRegisterInfo.inc"
36+
3437
using namespace llvm;
3538

3639
BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,

‎llvm/lib/Target/Blackfin/BlackfinRegisterInfo.h

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@@ -16,7 +16,9 @@
1616
#define BLACKFINREGISTERINFO_H
1717

1818
#include "llvm/Target/TargetRegisterInfo.h"
19-
#include "BlackfinGenRegisterInfo.h.inc"
19+
20+
#define GET_REGINFO_HEADER
21+
#include "BlackfinGenRegisterInfo.inc"
2022

2123
namespace llvm {
2224

‎llvm/lib/Target/Blackfin/CMakeLists.txt

-3
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
11
set(LLVM_TARGET_DEFINITIONS Blackfin.td)
22

3-
tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
4-
tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
5-
tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
63
tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
74
tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
85
tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)

‎llvm/lib/Target/Blackfin/Makefile

+1-3
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@@ -12,9 +12,7 @@ LIBRARYNAME = LLVMBlackfinCodeGen
1212
TARGET = Blackfin
1313

1414
# Make sure that tblgen is run, first thing.
15-
BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
16-
BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
17-
BlackfinGenInstrNames.inc \
15+
BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
1816
BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
1917
BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
2018
BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc

‎llvm/lib/Target/CellSPU/CMakeLists.txt

-3
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@@ -1,11 +1,8 @@
11
set(LLVM_TARGET_DEFINITIONS SPU.td)
22

33
tablegen(SPUGenInstrNames.inc -gen-instr-enums)
4-
tablegen(SPUGenRegisterNames.inc -gen-register-enums)
54
tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
65
tablegen(SPUGenCodeEmitter.inc -gen-emitter)
7-
tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
8-
tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
96
tablegen(SPUGenRegisterInfo.inc -gen-register-info)
107
tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
118
tablegen(SPUGenDAGISel.inc -gen-dag-isel)

‎llvm/lib/Target/CellSPU/Makefile

+1-3
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@@ -10,10 +10,8 @@
1010
LEVEL = ../../..
1111
LIBRARYNAME = LLVMCellSPUCodeGen
1212
TARGET = SPU
13-
BUILT_SOURCES = SPUGenInstrNames.inc \
13+
BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
1414
SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
15-
SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
16-
SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
1715
SPUGenInstrInfo.inc SPUGenDAGISel.inc \
1816
SPUGenSubtarget.inc SPUGenCallingConv.inc
1917

‎llvm/lib/Target/CellSPU/SPURegisterInfo.cpp

+3-1
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@@ -42,7 +42,9 @@
4242
#include "llvm/ADT/BitVector.h"
4343
#include "llvm/ADT/STLExtras.h"
4444
#include <cstdlib>
45-
#include "SPUGenRegisterDesc.inc"
45+
46+
#define GET_REGINFO_MC_DESC
47+
#define GET_REGINFO_TARGET_DESC
4648
#include "SPUGenRegisterInfo.inc"
4749

4850
using namespace llvm;

‎llvm/lib/Target/CellSPU/SPURegisterInfo.h

+3-1
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@@ -16,7 +16,9 @@
1616
#define SPU_REGISTERINFO_H
1717

1818
#include "SPU.h"
19-
#include "SPUGenRegisterInfo.h.inc"
19+
20+
#define GET_REGINFO_HEADER
21+
#include "SPUGenRegisterInfo.inc"
2022

2123
namespace llvm {
2224
class SPUSubtarget;

‎llvm/lib/Target/CellSPU/SPURegisterNames.h

+2-1
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@@ -13,6 +13,7 @@
1313
// Define symbolic names for Cell registers. This defines a mapping from
1414
// register name to register number.
1515
//
16-
#include "SPUGenRegisterNames.inc"
16+
#define GET_REGINFO_ENUM
17+
#include "SPUGenRegisterInfo.inc"
1718

1819
#endif

‎llvm/lib/Target/MBlaze/CMakeLists.txt

-3
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@@ -1,9 +1,6 @@
11
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
22

3-
tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
4-
tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
53
tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
6-
tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
74
tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
85
tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
96
tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)

‎llvm/lib/Target/MBlaze/MBlaze.h

+2-1
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@@ -39,7 +39,8 @@ namespace llvm {
3939

4040
// Defines symbolic names for MBlaze registers. This defines a mapping from
4141
// register name to register number.
42-
#include "MBlazeGenRegisterNames.inc"
42+
#define GET_REGINFO_ENUM
43+
#include "MBlazeGenRegisterInfo.inc"
4344

4445
// Defines symbolic names for the MBlaze instructions.
4546
#include "MBlazeGenInstrNames.inc"

‎llvm/lib/Target/MBlaze/MBlazeRegisterInfo.cpp

+4-1
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,11 @@
3636
#include "llvm/Support/raw_ostream.h"
3737
#include "llvm/ADT/BitVector.h"
3838
#include "llvm/ADT/STLExtras.h"
39-
#include "MBlazeGenRegisterDesc.inc"
39+
40+
#define GET_REGINFO_MC_DESC
41+
#define GET_REGINFO_TARGET_DESC
4042
#include "MBlazeGenRegisterInfo.inc"
43+
4144
using namespace llvm;
4245

4346
MBlazeRegisterInfo::

‎llvm/lib/Target/MBlaze/MBlazeRegisterInfo.h

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@@ -17,7 +17,9 @@
1717

1818
#include "MBlaze.h"
1919
#include "llvm/Target/TargetRegisterInfo.h"
20-
#include "MBlazeGenRegisterInfo.h.inc"
20+
21+
#define GET_REGINFO_HEADER
22+
#include "MBlazeGenRegisterInfo.inc"
2123

2224
namespace llvm {
2325
class MBlazeSubtarget;

‎llvm/lib/Target/MBlaze/Makefile

+1-3
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@@ -11,9 +11,7 @@ LIBRARYNAME = LLVMMBlazeCodeGen
1111
TARGET = MBlaze
1212

1313
# Make sure that tblgen is run, first thing.
14-
BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
15-
MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
16-
MBlazeGenInstrNames.inc \
14+
BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
1715
MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
1816
MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
1917
MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \

‎llvm/lib/Target/MSP430/CMakeLists.txt

-3
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@@ -1,8 +1,5 @@
11
set(LLVM_TARGET_DEFINITIONS MSP430.td)
22

3-
tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
4-
tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
5-
tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
63
tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
74
tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
85
tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)

‎llvm/lib/Target/MSP430/MSP430.h

+2-1
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@@ -47,7 +47,8 @@ namespace llvm {
4747

4848
// Defines symbolic names for MSP430 registers.
4949
// This defines a mapping from register name to register number.
50-
#include "MSP430GenRegisterNames.inc"
50+
#define GET_REGINFO_ENUM
51+
#include "MSP430GenRegisterInfo.inc"
5152

5253
// Defines symbolic names for the MSP430 instructions.
5354
#include "MSP430GenInstrNames.inc"

‎llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp

+3-1
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@@ -25,7 +25,9 @@
2525
#include "llvm/Target/TargetOptions.h"
2626
#include "llvm/ADT/BitVector.h"
2727
#include "llvm/Support/ErrorHandling.h"
28-
#include "MSP430GenRegisterDesc.inc"
28+
29+
#define GET_REGINFO_MC_DESC
30+
#define GET_REGINFO_TARGET_DESC
2931
#include "MSP430GenRegisterInfo.inc"
3032

3133
using namespace llvm;

‎llvm/lib/Target/MSP430/MSP430RegisterInfo.h

+3-1
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@@ -15,7 +15,9 @@
1515
#define LLVM_TARGET_MSP430REGISTERINFO_H
1616

1717
#include "llvm/Target/TargetRegisterInfo.h"
18-
#include "MSP430GenRegisterInfo.h.inc"
18+
19+
#define GET_REGINFO_HEADER
20+
#include "MSP430GenRegisterInfo.inc"
1921

2022
namespace llvm {
2123

‎llvm/lib/Target/MSP430/Makefile

+1-3
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@@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMSP430CodeGen
1212
TARGET = MSP430
1313

1414
# Make sure that tblgen is run, first thing.
15-
BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
16-
MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
17-
MSP430GenInstrNames.inc \
15+
BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
1816
MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
1917
MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
2018
MSP430GenSubtarget.inc

‎llvm/lib/Target/Mips/CMakeLists.txt

-3
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@@ -1,8 +1,5 @@
11
set(LLVM_TARGET_DEFINITIONS Mips.td)
22

3-
tablegen(MipsGenRegisterNames.inc -gen-register-enums)
4-
tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
5-
tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
63
tablegen(MipsGenRegisterInfo.inc -gen-register-info)
74
tablegen(MipsGenInstrNames.inc -gen-instr-enums)
85
tablegen(MipsGenInstrInfo.inc -gen-instr-desc)

‎llvm/lib/Target/Mips/Makefile

+1-3
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@@ -12,9 +12,7 @@ LIBRARYNAME = LLVMMipsCodeGen
1212
TARGET = Mips
1313

1414
# Make sure that tblgen is run, first thing.
15-
BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
16-
MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
17-
MipsGenInstrNames.inc \
15+
BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
1816
MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
1917
MipsGenDAGISel.inc MipsGenCallingConv.inc \
2018
MipsGenSubtarget.inc

‎llvm/lib/Target/Mips/Mips.h

+2-1
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@@ -35,7 +35,8 @@ namespace llvm {
3535

3636
// Defines symbolic names for Mips registers. This defines a mapping from
3737
// register name to register number.
38-
#include "MipsGenRegisterNames.inc"
38+
#define GET_REGINFO_ENUM
39+
#include "MipsGenRegisterInfo.inc"
3940

4041
// Defines symbolic names for the Mips instructions.
4142
#include "MipsGenInstrNames.inc"

‎llvm/lib/Target/Mips/MipsRegisterInfo.cpp

+3-1
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@@ -35,7 +35,9 @@
3535
#include "llvm/Support/raw_ostream.h"
3636
#include "llvm/ADT/BitVector.h"
3737
#include "llvm/ADT/STLExtras.h"
38-
#include "MipsGenRegisterDesc.inc"
38+
39+
#define GET_REGINFO_MC_DESC
40+
#define GET_REGINFO_TARGET_DESC
3941
#include "MipsGenRegisterInfo.inc"
4042

4143
using namespace llvm;

‎llvm/lib/Target/Mips/MipsRegisterInfo.h

+3-1
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@@ -16,7 +16,9 @@
1616

1717
#include "Mips.h"
1818
#include "llvm/Target/TargetRegisterInfo.h"
19-
#include "MipsGenRegisterInfo.h.inc"
19+
20+
#define GET_REGINFO_HEADER
21+
#include "MipsGenRegisterInfo.inc"
2022

2123
namespace llvm {
2224
class MipsSubtarget;

‎llvm/lib/Target/PTX/CMakeLists.txt

-3
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@@ -5,10 +5,7 @@ tablegen(PTXGenCallingConv.inc -gen-callingconv)
55
tablegen(PTXGenDAGISel.inc -gen-dag-isel)
66
tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
77
tablegen(PTXGenInstrNames.inc -gen-instr-enums)
8-
tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
98
tablegen(PTXGenRegisterInfo.inc -gen-register-info)
10-
tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
11-
tablegen(PTXGenRegisterNames.inc -gen-register-enums)
129
tablegen(PTXGenSubtarget.inc -gen-subtarget)
1310

1411
add_llvm_target(PTXCodeGen

‎llvm/lib/Target/PTX/Makefile

-3
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@@ -17,10 +17,7 @@ BUILT_SOURCES = PTXGenAsmWriter.inc \
1717
PTXGenDAGISel.inc \
1818
PTXGenInstrInfo.inc \
1919
PTXGenInstrNames.inc \
20-
PTXGenRegisterDesc.inc \
2120
PTXGenRegisterInfo.inc \
22-
PTXGenRegisterInfo.h.inc \
23-
PTXGenRegisterNames.inc \
2421
PTXGenSubtarget.inc
2522

2623
DIRS = TargetInfo

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