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[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
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‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -4095,12 +4095,12 @@ void X86AsmParser::applyLVICFIMitigation(MCInst &Inst, MCStreamer &Out) {
40954095
// be found here:
40964096
// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
40974097
switch (Inst.getOpcode()) {
4098-
case X86::RETW:
4099-
case X86::RETL:
4100-
case X86::RETQ:
4101-
case X86::RETIL:
4102-
case X86::RETIQ:
4103-
case X86::RETIW: {
4098+
case X86::RET16:
4099+
case X86::RET32:
4100+
case X86::RET64:
4101+
case X86::RETI16:
4102+
case X86::RETI32:
4103+
case X86::RETI64: {
41044104
MCInst ShlInst, FenceInst;
41054105
bool Parse32 = is32BitMode() || Code16GCC;
41064106
unsigned Basereg =

‎llvm/lib/Target/X86/X86ExpandPseudo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -394,10 +394,10 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
394394
MachineInstrBuilder MIB;
395395
if (StackAdj == 0) {
396396
MIB = BuildMI(MBB, MBBI, DL,
397-
TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
397+
TII->get(STI->is64Bit() ? X86::RET64 : X86::RET32));
398398
} else if (isUInt<16>(StackAdj)) {
399399
MIB = BuildMI(MBB, MBBI, DL,
400-
TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
400+
TII->get(STI->is64Bit() ? X86::RETI64 : X86::RETI32))
401401
.addImm(StackAdj);
402402
} else {
403403
assert(!STI->is64Bit() &&
@@ -407,7 +407,7 @@ bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
407407
BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
408408
X86FL->emitSPUpdate(MBB, MBBI, DL, StackAdj, /*InEpilogue=*/true);
409409
BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
410-
MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
410+
MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RET32));
411411
}
412412
for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
413413
MIB.add(MBBI->getOperand(I));

‎llvm/lib/Target/X86/X86FastISel.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1304,11 +1304,11 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
13041304
MachineInstrBuilder MIB;
13051305
if (X86MFInfo->getBytesToPopOnReturn()) {
13061306
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1307-
TII.get(Subtarget->is64Bit() ? X86::RETIQ : X86::RETIL))
1307+
TII.get(Subtarget->is64Bit() ? X86::RETI64 : X86::RETI32))
13081308
.addImm(X86MFInfo->getBytesToPopOnReturn());
13091309
} else {
13101310
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1311-
TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1311+
TII.get(Subtarget->is64Bit() ? X86::RET64 : X86::RET32));
13121312
}
13131313
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
13141314
MIB.addReg(RetRegs[i], RegState::Implicit);

‎llvm/lib/Target/X86/X86IndirectThunks.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -212,7 +212,7 @@ void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
212212
MF.push_back(CallTarget);
213213

214214
const unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
215-
const unsigned RetOpc = Is64Bit ? X86::RETQ : X86::RETL;
215+
const unsigned RetOpc = Is64Bit ? X86::RET64 : X86::RET32;
216216

217217
Entry->addLiveIn(ThunkReg);
218218
BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym);

‎llvm/lib/Target/X86/X86InstrControl.td

+15-15
Original file line numberDiff line numberDiff line change
@@ -20,30 +20,30 @@
2020
// ST1 arguments when returning values on the x87 stack.
2121
let isTerminator = 1, isReturn = 1, isBarrier = 1,
2222
hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
23-
def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
23+
def RET32 : I <0xC3, RawFrm, (outs), (ins variable_ops),
2424
"ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
25-
def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
25+
def RET64 : I <0xC3, RawFrm, (outs), (ins variable_ops),
2626
"ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
27-
def RETW : I <0xC3, RawFrm, (outs), (ins),
27+
def RET16 : I <0xC3, RawFrm, (outs), (ins),
2828
"ret{w}", []>, OpSize16;
29-
def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
29+
def RETI32 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
3030
"ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
31-
def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
31+
def RETI64 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
3232
"ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
33-
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
33+
def RETI16 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
3434
"ret{w}\t$amt", []>, OpSize16;
35-
def LRETL : I <0xCB, RawFrm, (outs), (ins),
35+
def LRET32 : I <0xCB, RawFrm, (outs), (ins),
3636
"{l}ret{l|f}", []>, OpSize32;
37-
def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
37+
def LRET64 : RI <0xCB, RawFrm, (outs), (ins),
3838
"{l}ret{|f}q", []>, Requires<[In64BitMode]>;
39-
def LRETW : I <0xCB, RawFrm, (outs), (ins),
39+
def LRET16 : I <0xCB, RawFrm, (outs), (ins),
4040
"{l}ret{w|f}", []>, OpSize16;
41-
def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42-
"{l}ret{l|f}\t$amt", []>, OpSize32;
43-
def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
44-
"{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
45-
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
46-
"{l}ret{w|f}\t$amt", []>, OpSize16;
41+
def LRETI32 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42+
"{l}ret{l|f}\t$amt", []>, OpSize32;
43+
def LRETI64 : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
44+
"{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
45+
def LRETI16 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
46+
"{l}ret{w|f}\t$amt", []>, OpSize16;
4747

4848
// The machine return from interrupt instruction, but sometimes we need to
4949
// perform a post-epilogue stack adjustment. Codegen emits the pseudo form

‎llvm/lib/Target/X86/X86InstrInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
8282
(STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
8383
: X86::ADJCALLSTACKUP32),
8484
X86::CATCHRET,
85-
(STI.is64Bit() ? X86::RETQ : X86::RETL)),
85+
(STI.is64Bit() ? X86::RET64 : X86::RET32)),
8686
Subtarget(STI), RI(STI.getTargetTriple()) {
8787
}
8888

@@ -9363,7 +9363,7 @@ void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
93639363

93649364
// We're a normal call, so our sequence doesn't have a return instruction.
93659365
// Add it in.
9366-
MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
9366+
MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
93679367
MBB.insert(MBB.end(), retq);
93689368
}
93699369

‎llvm/lib/Target/X86/X86LoadValueInjectionRetHardening.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ bool X86LoadValueInjectionRetHardeningPass::runOnMachineFunction(
7676
bool Modified = false;
7777
for (auto &MBB : MF) {
7878
for (auto MBBI = MBB.begin(); MBBI != MBB.end(); ++MBBI) {
79-
if (MBBI->getOpcode() != X86::RETQ)
79+
if (MBBI->getOpcode() != X86::RET64)
8080
continue;
8181

8282
unsigned ClobberReg = TRI->findDeadCallerSavedReg(MBB, MBBI);

‎llvm/lib/Target/X86/X86MCInstLower.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -421,7 +421,7 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
421421
}
422422

423423
static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
424-
return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
424+
return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
425425
}
426426

427427
Optional<MCOperand>

‎llvm/lib/Target/X86/X86RegisterInfo.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -816,10 +816,10 @@ unsigned X86RegisterInfo::findDeadCallerSavedReg(
816816
return 0;
817817
case TargetOpcode::PATCHABLE_RET:
818818
case X86::RET:
819-
case X86::RETL:
820-
case X86::RETQ:
821-
case X86::RETIL:
822-
case X86::RETIQ:
819+
case X86::RET32:
820+
case X86::RET64:
821+
case X86::RETI32:
822+
case X86::RETI64:
823823
case X86::TCRETURNdi:
824824
case X86::TCRETURNri:
825825
case X86::TCRETURNmi:

‎llvm/lib/Target/X86/X86SchedBroadwell.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -1110,7 +1110,7 @@ def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
11101110
let NumMicroOps = 3;
11111111
let ResourceCycles = [1,1,1];
11121112
}
1113-
def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1113+
def: InstRW<[BWWriteResGroup84], (instrs LRET64, RET64)>;
11141114

11151115
def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
11161116
let Latency = 7;

‎llvm/lib/Target/X86/X86SchedHaswell.td

+2-2
Original file line numberDiff line numberDiff line change
@@ -710,7 +710,7 @@ def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
710710
let NumMicroOps = 4;
711711
let ResourceCycles = [1, 2, 1];
712712
}
713-
def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
713+
def : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>;
714714

715715
// BOUND.
716716
// r,m.
@@ -1188,7 +1188,7 @@ def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
11881188
let NumMicroOps = 3;
11891189
let ResourceCycles = [1,1,1];
11901190
}
1191-
def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>;
1191+
def: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>;
11921192

11931193
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
11941194
let Latency = 3;

‎llvm/lib/Target/X86/X86SchedIceLake.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -1444,7 +1444,7 @@ def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> {
14441444
let NumMicroOps = 3;
14451445
let ResourceCycles = [1,1,1];
14461446
}
1447-
def: InstRW<[ICXWriteResGroup104], (instrs LRETQ, RETQ)>;
1447+
def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>;
14481448

14491449
def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> {
14501450
let Latency = 7;

‎llvm/lib/Target/X86/X86SchedSandyBridge.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -606,7 +606,7 @@ def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
606606
def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
607607
LD_Frr, ST_Frr, ST_FPrr)>;
608608
def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
609-
def: InstRW<[SBWriteResGroup2], (instrs RETQ)>;
609+
def: InstRW<[SBWriteResGroup2], (instrs RET64)>;
610610

611611
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
612612
let Latency = 1;

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -1175,7 +1175,7 @@ def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
11751175
let NumMicroOps = 3;
11761176
let ResourceCycles = [1,1,1];
11771177
}
1178-
def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1178+
def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
11791179

11801180
def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
11811181
let Latency = 7;

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -1436,7 +1436,7 @@ def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
14361436
let NumMicroOps = 3;
14371437
let ResourceCycles = [1,1,1];
14381438
}
1439-
def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1439+
def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>;
14401440

14411441
def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
14421442
let Latency = 7;

‎llvm/lib/Target/X86/X86ScheduleAtom.td

+3-3
Original file line numberDiff line numberDiff line change
@@ -540,7 +540,7 @@ def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
540540
PUSH16rmr, PUSH32rmr, PUSH64rmr,
541541
PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
542542
XCH_F)>;
543-
def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
543+
def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
544544
"IRET(16|32|64)?")>;
545545

546546
def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
@@ -819,8 +819,8 @@ def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
819819
let Latency = 79;
820820
let ResourceCycles = [79];
821821
}
822-
def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$",
823-
"LRETI?(L|Q|W)")>;
822+
def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",
823+
"LRETI?(16|32|64)")>;
824824

825825
def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
826826
let Latency = 92;

‎llvm/lib/Target/X86/X86ScheduleZnver1.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,7 @@ def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
697697
def ZnWriteRET : SchedWriteRes<[ZnALU03]> {
698698
let NumMicroOps = 2;
699699
}
700-
def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
700+
def : InstRW<[ZnWriteRET], (instregex "RET(16|32|64)", "LRET(16|32|64)",
701701
"IRET(16|32|64)")>;
702702

703703
//-- Logic instructions --//

‎llvm/lib/Target/X86/X86ScheduleZnver2.td

+1-1
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,7 @@ def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>;
697697
def Zn2WriteRET : SchedWriteRes<[Zn2ALU03]> {
698698
let NumMicroOps = 2;
699699
}
700-
def : InstRW<[Zn2WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)",
700+
def : InstRW<[Zn2WriteRET], (instregex "RET(16|32|64)", "LRET(16|32|64)",
701701
"IRET(16|32|64)")>;
702702

703703
//-- Logic instructions --//

‎llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir

+1-1
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ body: |
6262
MOV32mr $noreg, 1, $noreg, @ga, $noreg, killed %8 :: (store (s32) into @ga)
6363
%5:gr32 = MOV32rm %stack.2.c, 1, $noreg, 0, $noreg :: (load (s32) from %ir.c)
6464
$eax = COPY %5
65-
RETQ implicit $eax
65+
RET64 implicit $eax
6666
6767
;CHECK: WARNING: Missing line 9
6868
;CHECK-NEXT: Machine IR debug info check: FAIL

‎llvm/test/CodeGen/MIR/X86/auto-successor.mir

+4-4
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
# CHECK-NOT: successors
1313
# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
1414
# CHECK: bb.3:
15-
# CHECK: RETQ undef $eax
15+
# CHECK: RET64 undef $eax
1616
name: func0
1717
body: |
1818
bb.0:
@@ -28,7 +28,7 @@ body: |
2828
JCC_1 %bb.4, 4, implicit undef $eflags ; condjump+fallthrough to same block
2929
3030
bb.4:
31-
RETQ undef $eax
31+
RET64 undef $eax
3232
...
3333
---
3434
# Some cases that need explicit successors:
@@ -56,6 +56,6 @@ body: |
5656
5757
bb.3:
5858
; CHECK: bb.3:
59-
; CHECK: RETQ undef $eax
60-
RETQ undef $eax
59+
; CHECK: RET64 undef $eax
60+
RET64 undef $eax
6161
...

‎llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir

+3-3
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ body: |
3131
liveins: $edi, $esi
3232
3333
$eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
34-
RETQ $eax
34+
RET64 $eax
3535
...
3636
---
3737
name: test2
@@ -47,7 +47,7 @@ body: |
4747
liveins: $esi
4848
4949
$eax = LEA64_32r killed $rdi, 1, killed $rsi, 0, _
50-
RETQ $eax
50+
RET64 $eax
5151
...
5252
---
5353
name: test3
@@ -61,5 +61,5 @@ body: |
6161
liveins:
6262
6363
$eax = MOV32r0 implicit-def dead $eflags
64-
RETQ killed $eax
64+
RET64 killed $eax
6565
...

‎llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -31,11 +31,11 @@ body: |
3131
; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
3232
less bb.1:
3333
$eax = MOV32r0 implicit-def dead $eflags
34-
RETQ killed $eax
34+
RET64 killed $eax
3535
3636
bb.2.exit:
3737
liveins: $edi
3838
3939
$eax = COPY killed $edi
40-
RETQ killed $eax
40+
RET64 killed $eax
4141
...

‎llvm/test/CodeGen/MIR/X86/block-address-operands.mir

+5-5
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ body: |
6363
JMP64m $rip, 1, _, @addr, _
6464
6565
bb.1.block (address-taken):
66-
RETQ
66+
RET64
6767
...
6868
---
6969
name: test2
@@ -77,7 +77,7 @@ body: |
7777
JMP64m $rip, 1, _, @addr, _
7878
7979
bb.1 (address-taken):
80-
RETQ
80+
RET64
8181
...
8282
---
8383
name: slot_in_other_function
@@ -89,7 +89,7 @@ body: |
8989
; CHECK: $rax = LEA64r $rip, 1, $noreg, blockaddress(@test3, %ir-block.0), $noreg
9090
$rax = LEA64r $rip, 1, _, blockaddress(@test3, %ir-block.0), _
9191
MOV64mr killed $rdi, 1, _, 0, _, killed $rax
92-
RETQ
92+
RET64
9393
...
9494
---
9595
name: test3
@@ -104,7 +104,7 @@ body: |
104104
JMP64m $rip, 1, _, @addr, _
105105
106106
bb.1 (address-taken):
107-
RETQ
107+
RET64
108108
...
109109
---
110110
name: test4
@@ -117,5 +117,5 @@ body: |
117117
JMP64m $rip, 1, _, @addr, _
118118
119119
bb.1.block (address-taken):
120-
RETQ
120+
RET64
121121
...

‎llvm/test/CodeGen/MIR/X86/branch-probabilities.mir

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,5 +14,5 @@ body: |
1414
NOOP
1515
1616
bb.2:
17-
RETQ undef $eax
17+
RET64 undef $eax
1818
...

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