Revert "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values"

This reverts commit d07f106.

Author: SLTozer

llvm/docs/LangRef.rst

@@ -5311,14 +5311,6 @@ The current supported opcode vocabulary is limited:
   ``AsmPrinter`` pass when a call site parameter value
   (``DW_AT_call_site_parameter_value``) is represented as entry value
   of the parameter.
-- ``DW_OP_LLVM_arg, N`` is used in debug intrinsics that refer to more than one
-  value, such as one that calculates the sum of two registers. This is always
-  used in combination with an ordered list of values, such that
-  ``DW_OP_LLVM_arg, N`` refers to the ``N``th element in that list. For
-  example, ``!DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_minus,
-  DW_OP_stack_value)`` used with the list ``(%reg1, %reg2)`` would evaluate to
-  ``%reg1 - reg2``. This list of values should be provided by the containing
-  intrinsic/instruction.
 - ``DW_OP_breg`` (or ``DW_OP_bregx``) represents a content on the provided
   signed offset of the specified register. The opcode is only generated by the
   ``AsmPrinter`` pass to describe call site parameter value which requires an

llvm/docs/SourceLevelDebugging.rst

@@ -576,15 +576,13 @@ the equivalent location is used.
 
 After MIR locations are assigned to each variable, machine pseudo-instructions
 corresponding to each ``llvm.dbg.value`` and ``llvm.dbg.addr`` intrinsic are
-inserted. There are two forms of this type of instruction.
-
-The first form, ``DBG_VALUE``, appears thus:
+inserted. These ``DBG_VALUE`` instructions appear thus:
 
 .. code-block:: text
 
   DBG_VALUE %1, $noreg, !123, !DIExpression()
 
-And has the following operands:
+And have the following operands:
  * The first operand can record the variable location as a register,
    a frame index, an immediate, or the base address register if the original
    debug intrinsic referred to memory. ``$noreg`` indicates the variable
@@ -596,22 +594,6 @@ And has the following operands:
  * Operand 3 is the Variable field of the original debug intrinsic.
  * Operand 4 is the Expression field of the original debug intrinsic.
 
-The second form, ``DBG_VALUE_LIST``, appears thus:
-
-.. code-block:: text
-
-  DBG_VALUE_LIST !123, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus), %1, %2
-
-And has the following operands:
- * The first operand is the Variable field of the original debug intrinsic.
- * The second operand is the Expression field of the original debug intrinsic.
- * Any number of operands, from the 3rd onwards, record a sequence of variable
-   location operands, which may take any of the same values as the first
-   operand of the ``DBG_VALUE`` instruction above. These variable location
-   operands are inserted into the final DWARF Expression in positions indicated
-   by the DW_OP_LLVM_arg operator in the DIExpression, as described in
-   :ref:`DIExpression<_DIExpression>`.
-
 The position at which the DBG_VALUEs are inserted should correspond to the
 positions of their matching ``llvm.dbg.value`` intrinsics in the IR block.  As
 with optimization, LLVM aims to preserve the order in which variable

llvm/include/llvm/BinaryFormat/Dwarf.h

@@ -144,7 +144,6 @@ enum LocationAtom {
   DW_OP_LLVM_tag_offset = 0x1002,       ///< Only used in LLVM metadata.
   DW_OP_LLVM_entry_value = 0x1003,      ///< Only used in LLVM metadata.
   DW_OP_LLVM_implicit_pointer = 0x1004, ///< Only used in LLVM metadata.
-  DW_OP_LLVM_arg = 0x1005,              ///< Only used in LLVM metadata.
 };
 
 enum TypeKind : uint8_t {

llvm/include/llvm/CodeGen/MachineInstr.h

@@ -420,11 +420,11 @@ class MachineInstr
   /// instruction is indirect; will be an invalid register if this value is
   /// not indirect, and an immediate with value 0 otherwise.
   const MachineOperand &getDebugOffset() const {
-    assert(isNonListDebugValue() && "not a DBG_VALUE");
+    assert(isDebugValue() && "not a DBG_VALUE");
     return getOperand(1);
   }
   MachineOperand &getDebugOffset() {
-    assert(isNonListDebugValue() && "not a DBG_VALUE");
+    assert(isDebugValue() && "not a DBG_VALUE");
     return getOperand(1);
   }
 
@@ -439,7 +439,6 @@ class MachineInstr
 
   /// Return the operand for the complex address expression referenced by
   /// this DBG_VALUE instruction.
-  const MachineOperand &getDebugExpressionOp() const;
   MachineOperand &getDebugExpressionOp();
 
   /// Return the complex address expression referenced by
@@ -502,43 +501,26 @@ class MachineInstr
     return *(debug_operands().begin() + Index);
   }
 
-  /// Returns whether this debug value has at least one debug operand with the
-  /// register \p Reg.
-  bool hasDebugOperandForReg(Register Reg) const {
-    return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
-      return Op.isReg() && Op.getReg() == Reg;
-    });
+  /// Returns a pointer to the operand corresponding to a debug use of Reg, or
+  /// nullptr if Reg is not used in any debug operand.
+  const MachineOperand *getDebugOperandForReg(Register Reg) const {
+    const MachineOperand *RegOp =
+        find_if(debug_operands(), [Reg](const MachineOperand &Op) {
+          return Op.isReg() && Op.getReg() == Reg;
+        });
+    return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
   }
-
-  /// Returns a range of all of the operands that correspond to a debug use of
-  /// \p Reg.
-  template <typename Operand, typename Instruction>
-  static iterator_range<
-      filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
-  getDebugOperandsForReg(Instruction *MI, Register Reg) {
-    std::function<bool(Operand & Op)> OpUsesReg(
-        [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
-    return make_filter_range(MI->debug_operands(), OpUsesReg);
-  }
-  iterator_range<filter_iterator<const MachineOperand *,
-                                 std::function<bool(const MachineOperand &Op)>>>
-  getDebugOperandsForReg(Register Reg) const {
-    return MachineInstr::getDebugOperandsForReg<const MachineOperand,
-                                                const MachineInstr>(this, Reg);
-  }
-  iterator_range<filter_iterator<MachineOperand *,
-                                 std::function<bool(MachineOperand &Op)>>>
-  getDebugOperandsForReg(Register Reg) {
-    return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
-        this, Reg);
-  }
-
-  bool isDebugOperand(const MachineOperand *Op) const {
-    return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
+  MachineOperand *getDebugOperandForReg(Register Reg) {
+    MachineOperand *RegOp =
+        find_if(debug_operands(), [Reg](const MachineOperand &Op) {
+          return Op.isReg() && Op.getReg() == Reg;
+        });
+    return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
   }
 
   unsigned getDebugOperandIndex(const MachineOperand *Op) const {
-    assert(isDebugOperand(Op) && "Expected a debug operand.");
+    assert(Op >= adl_begin(debug_operands()) &&
+           Op <= adl_end(debug_operands()) && "Expected a debug operand.");
     return std::distance(adl_begin(debug_operands()), Op);
   }
 
@@ -618,16 +600,12 @@ class MachineInstr
   /// location for this DBG_VALUE instruction.
   iterator_range<mop_iterator> debug_operands() {
     assert(isDebugValue() && "Must be a debug value instruction.");
-    return isDebugValueList()
-               ? make_range(operands_begin() + 2, operands_end())
-               : make_range(operands_begin(), operands_begin() + 1);
+    return make_range(operands_begin(), operands_begin() + 1);
   }
   /// \copydoc debug_operands()
   iterator_range<const_mop_iterator> debug_operands() const {
     assert(isDebugValue() && "Must be a debug value instruction.");
-    return isDebugValueList()
-               ? make_range(operands_begin() + 2, operands_end())
-               : make_range(operands_begin(), operands_begin() + 1);
+    return make_range(operands_begin(), operands_begin() + 1);
   }
   /// Returns a range over all explicit operands that are register definitions.
   /// Implicit definition are not included!
@@ -1186,15 +1164,7 @@ class MachineInstr
   // True if the instruction represents a position in the function.
   bool isPosition() const { return isLabel() || isCFIInstruction(); }
 
-  bool isNonListDebugValue() const {
-    return getOpcode() == TargetOpcode::DBG_VALUE;
-  }
-  bool isDebugValueList() const {
-    return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
-  }
-  bool isDebugValue() const {
-    return isNonListDebugValue() || isDebugValueList();
-  }
+  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
   bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
   bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
   bool isDebugInstr() const {
@@ -1204,14 +1174,12 @@ class MachineInstr
     return isDebugInstr() || isPseudoProbe();
   }
 
-  bool isDebugOffsetImm() const {
-    return isNonListDebugValue() && getDebugOffset().isImm();
-  }
+  bool isDebugOffsetImm() const { return getDebugOffset().isImm(); }
 
   /// A DBG_VALUE is indirect iff the location operand is a register and
   /// the offset operand is an immediate.
   bool isIndirectDebugValue() const {
-    return isDebugOffsetImm() && getDebugOperand(0).isReg();
+    return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm();
   }
 
   /// A DBG_VALUE is an entry value iff its debug expression contains the
@@ -1221,13 +1189,8 @@ class MachineInstr
   /// Return true if the instruction is a debug value which describes a part of
   /// a variable as unavailable.
   bool isUndefDebugValue() const {
-    if (!isDebugValue())
-      return false;
-    // If any $noreg locations are given, this DV is undef.
-    for (const MachineOperand &Op : debug_operands())
-      if (Op.isReg() && !Op.getReg().isValid())
-        return true;
-    return false;
+    return isDebugValue() && getDebugOperand(0).isReg() &&
+           !getDebugOperand(0).getReg().isValid();
   }
 
   bool isPHI() const {
@@ -1302,7 +1265,6 @@ class MachineInstr
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::GC_LABEL:
     case TargetOpcode::DBG_VALUE:
-    case TargetOpcode::DBG_VALUE_LIST:
     case TargetOpcode::DBG_INSTR_REF:
     case TargetOpcode::DBG_LABEL:
     case TargetOpcode::LIFETIME_START:

llvm/include/llvm/CodeGen/MachineInstrBuilder.h

@@ -451,16 +451,9 @@ MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
 /// for a MachineOperand.
 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                             const MCInstrDesc &MCID, bool IsIndirect,
-                            const MachineOperand &MO, const MDNode *Variable,
+                            MachineOperand &MO, const MDNode *Variable,
                             const MDNode *Expr);
 
-/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
-/// for a MachineOperand.
-MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
-                            const MCInstrDesc &MCID, bool IsIndirect,
-                            ArrayRef<MachineOperand> MOs,
-                            const MDNode *Variable, const MDNode *Expr);
-
 /// This version of the builder builds a DBG_VALUE intrinsic
 /// for either a value in a register or a register-indirect
 /// address and inserts it at position I.
@@ -478,23 +471,14 @@ MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                             MachineOperand &MO, const MDNode *Variable,
                             const MDNode *Expr);
 
-/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
-/// for a machine operand and inserts it at position I.
-MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
-                            MachineBasicBlock::iterator I, const DebugLoc &DL,
-                            const MCInstrDesc &MCID, bool IsIndirect,
-                            ArrayRef<MachineOperand> MOs,
-                            const MDNode *Variable, const MDNode *Expr);
-
 /// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
                                     MachineBasicBlock::iterator I,
-                                    const MachineInstr &Orig, int FrameIndex,
-                                    Register SpillReg);
+                                    const MachineInstr &Orig, int FrameIndex);
 
 /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
 /// modifying an instruction in place while iterating over a basic block.
-void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
+void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex);
 
 inline unsigned getDefRegState(bool B) {
   return B ? RegState::Define : 0;

llvm/include/llvm/IR/DebugInfoMetadata.h

@@ -2775,14 +2775,6 @@ class DIExpression : public MDNode {
   static DIExpression *appendToStack(const DIExpression *Expr,
                                      ArrayRef<uint64_t> Ops);
 
-  /// Create a copy of \p Expr by appending the given list of \p Ops to each
-  /// instance of the operand `DW_OP_LLVM_arg, \p ArgNo`. This is used to
-  /// modify a specific location used by \p Expr, such as when salvaging that
-  /// location.
-  static DIExpression *appendOpsToArg(const DIExpression *Expr,
-                                      ArrayRef<uint64_t> Ops, unsigned ArgNo,
-                                      bool StackValue = false);
-
   /// Create a DIExpression to describe one part of an aggregate variable that
   /// is fragmented across multiple Values. The DW_OP_LLVM_fragment operation
   /// will be appended to the elements of \c Expr. If \c Expr already contains

llvm/include/llvm/Support/TargetOpcodes.def

@@ -77,10 +77,6 @@ HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
 HANDLE_TARGET_OPCODE(DBG_VALUE)
 
-/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic
-/// list of locations
-HANDLE_TARGET_OPCODE(DBG_VALUE_LIST)
-
 /// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction
 /// that defines the value, rather than a virtual register.
 HANDLE_TARGET_OPCODE(DBG_INSTR_REF)

llvm/include/llvm/Target/Target.td

@@ -1107,12 +1107,6 @@ def DBG_VALUE : StandardPseudoInstruction {
   let AsmString = "DBG_VALUE";
   let hasSideEffects = false;
 }
-def DBG_VALUE_LIST : StandardPseudoInstruction {
-  let OutOperandList = (outs);
-  let InOperandList = (ins variable_ops);
-  let AsmString = "DBG_VALUE_LIST";
-  let hasSideEffects = 0;
-}
 def DBG_INSTR_REF : StandardPseudoInstruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);

llvm/lib/BinaryFormat/Dwarf.cpp

@@ -153,8 +153,6 @@ StringRef llvm::dwarf::OperationEncodingString(unsigned Encoding) {
     return "DW_OP_LLVM_entry_value";
   case DW_OP_LLVM_implicit_pointer:
     return "DW_OP_LLVM_implicit_pointer";
-  case DW_OP_LLVM_arg:
-    return "DW_OP_LLVM_arg";
   }
 }
 
@@ -168,7 +166,6 @@ unsigned llvm::dwarf::getOperationEncoding(StringRef OperationEncodingString) {
       .Case("DW_OP_LLVM_tag_offset", DW_OP_LLVM_tag_offset)
       .Case("DW_OP_LLVM_entry_value", DW_OP_LLVM_entry_value)
       .Case("DW_OP_LLVM_implicit_pointer", DW_OP_LLVM_implicit_pointer)
-      .Case("DW_OP_LLVM_arg", DW_OP_LLVM_arg)
       .Default(0);
 }
 

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

@@ -905,7 +905,7 @@ static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
 /// means the target will need to handle MI in EmitInstruction.
 static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) {
   // This code handles only the 4-operand target-independent form.
-  if (MI->isNonListDebugValue() && MI->getNumOperands() != 4)
+  if (MI->getNumOperands() != 4)
     return false;
 
   SmallString<128> Str;
@@ -1228,7 +1228,6 @@ void AsmPrinter::emitFunctionBody() {
         emitInlineAsm(&MI);
         break;
       case TargetOpcode::DBG_VALUE:
-      case TargetOpcode::DBG_VALUE_LIST:
         if (isVerbose()) {
           if (!emitDebugValueComment(&MI, *this))
             emitInstruction(&MI);

llvm/lib/CodeGen/InlineSpiller.cpp

@@ -1048,7 +1048,7 @@ void InlineSpiller::spillAroundUses(Register Reg) {
       // Modify DBG_VALUE now that the value is in a spill slot.
       MachineBasicBlock *MBB = MI->getParent();
       LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
-      buildDbgValueForSpill(*MBB, MI, *MI, StackSlot, Reg);
+      buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
       MBB->erase(MI);
       continue;
     }

llvm/lib/CodeGen/LiveRangeShrink.cpp

@@ -235,7 +235,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
         MachineBasicBlock::iterator EndIter = std::next(MI.getIterator());
         if (MI.getOperand(0).isReg())
           for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
-                 EndIter->hasDebugOperandForReg(MI.getOperand(0).getReg());
+                 EndIter->getDebugOperandForReg(MI.getOperand(0).getReg());
                ++EndIter, ++Next)
             IOM[&*EndIter] = NewOrder;
         MBB.splice(I, &MBB, MI.getIterator(), EndIter);

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -987,9 +987,7 @@ bool MIParser::parse(MachineInstr *&MI) {
     Optional<unsigned> TiedDefIdx;
     if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx))
       return true;
-    if ((OpCode == TargetOpcode::DBG_VALUE ||
-         OpCode == TargetOpcode::DBG_VALUE_LIST) &&
-        MO.isReg())
+    if (OpCode == TargetOpcode::DBG_VALUE && MO.isReg())
       MO.setIsDebug();
     Operands.push_back(
         ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));