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[NFC] Use [MC]Register in Live-ness tracking
Differential Revision: https://reviews.llvm.org/D90611
1 parent 2e15f4a commit b68994b

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5 files changed

+87
-88
lines changed

5 files changed

+87
-88
lines changed

llvm/include/llvm/CodeGen/LiveIntervals.h

+8-8
Original file line numberDiff line numberDiff line change
@@ -114,8 +114,8 @@ class VirtRegMap;
114114
LiveInterval &getInterval(Register Reg) {
115115
if (hasInterval(Reg))
116116
return *VirtRegIntervals[Reg.id()];
117-
else
118-
return createAndComputeVirtRegInterval(Reg);
117+
118+
return createAndComputeVirtRegInterval(Reg);
119119
}
120120

121121
const LiveInterval &getInterval(Register Reg) const {
@@ -142,14 +142,14 @@ class VirtRegMap;
142142
}
143143

144144
/// Interval removal.
145-
void removeInterval(unsigned Reg) {
145+
void removeInterval(Register Reg) {
146146
delete VirtRegIntervals[Reg];
147147
VirtRegIntervals[Reg] = nullptr;
148148
}
149149

150150
/// Given a register and an instruction, adds a live segment from that
151151
/// instruction to the end of its MBB.
152-
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
152+
LiveInterval::Segment addSegmentToEndOfBlock(Register Reg,
153153
MachineInstr &startInst);
154154

155155
/// After removing some uses of a register, shrink its live range to just
@@ -167,7 +167,7 @@ class VirtRegMap;
167167
/// the lane mask of the subregister range.
168168
/// This may leave the subrange empty which needs to be cleaned up with
169169
/// LiveInterval::removeEmptySubranges() afterwards.
170-
void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
170+
void shrinkToUses(LiveInterval::SubRange &SR, Register Reg);
171171

172172
/// Extend the live range \p LR to reach all points in \p Indices. The
173173
/// points in the \p Indices array must be jointly dominated by the union
@@ -463,7 +463,7 @@ class VirtRegMap;
463463
bool computeDeadValues(LiveInterval &LI,
464464
SmallVectorImpl<MachineInstr*> *dead);
465465

466-
static LiveInterval* createInterval(unsigned Reg);
466+
static LiveInterval *createInterval(Register Reg);
467467

468468
void printInstrs(raw_ostream &O) const;
469469
void dumpInstrs() const;
@@ -474,7 +474,7 @@ class VirtRegMap;
474474

475475
using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
476476
void extendSegmentsToUses(LiveRange &Segments,
477-
ShrinkToUsesWorkList &WorkList, unsigned Reg,
477+
ShrinkToUsesWorkList &WorkList, Register Reg,
478478
LaneBitmask LaneMask);
479479

480480
/// Helper function for repairIntervalsInRange(), walks backwards and
@@ -484,7 +484,7 @@ class VirtRegMap;
484484
void repairOldRegInRange(MachineBasicBlock::iterator Begin,
485485
MachineBasicBlock::iterator End,
486486
const SlotIndex endIdx, LiveRange &LR,
487-
unsigned Reg,
487+
Register Reg,
488488
LaneBitmask LaneMask = LaneBitmask::getAll());
489489

490490
class HMEditor;

llvm/include/llvm/CodeGen/LiveVariables.h

+24-25
Original file line numberDiff line numberDiff line change
@@ -105,8 +105,7 @@ class LiveVariables : public MachineFunctionPass {
105105
/// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
106106
/// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
107107
/// MBB, it is not considered live in.
108-
bool isLiveIn(const MachineBasicBlock &MBB,
109-
unsigned Reg,
108+
bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
110109
MachineRegisterInfo &MRI);
111110

112111
void dump() const;
@@ -149,25 +148,25 @@ class LiveVariables : public MachineFunctionPass {
149148
/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
150149
/// uses. Pay special attention to the sub-register uses which may come below
151150
/// the last use of the whole register.
152-
bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
151+
bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
153152

154153
/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
155154
void HandleRegMask(const MachineOperand&);
156155

157-
void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
158-
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
156+
void HandlePhysRegUse(Register Reg, MachineInstr &MI);
157+
void HandlePhysRegDef(Register Reg, MachineInstr *MI,
159158
SmallVectorImpl<unsigned> &Defs);
160159
void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
161160

162161
/// FindLastRefOrPartRef - Return the last reference or partial reference of
163162
/// the specified register.
164-
MachineInstr *FindLastRefOrPartRef(unsigned Reg);
163+
MachineInstr *FindLastRefOrPartRef(Register Reg);
165164

166165
/// FindLastPartialDef - Return the last partial def of the specified
167166
/// register. Also returns the sub-registers that're defined by the
168167
/// instruction.
169-
MachineInstr *FindLastPartialDef(unsigned Reg,
170-
SmallSet<unsigned,4> &PartDefRegs);
168+
MachineInstr *FindLastPartialDef(Register Reg,
169+
SmallSet<unsigned, 4> &PartDefRegs);
171170

172171
/// analyzePHINodes - Gather information about the PHI nodes in here. In
173172
/// particular, we want to map the variable information of a virtual
@@ -184,21 +183,21 @@ class LiveVariables : public MachineFunctionPass {
184183

185184
/// RegisterDefIsDead - Return true if the specified instruction defines the
186185
/// specified register, but that definition is dead.
187-
bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const;
186+
bool RegisterDefIsDead(MachineInstr &MI, Register Reg) const;
188187

189188
//===--------------------------------------------------------------------===//
190189
// API to update live variable information
191190

192191
/// replaceKillInstruction - Update register kill info by replacing a kill
193192
/// instruction with a new one.
194-
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
193+
void replaceKillInstruction(Register Reg, MachineInstr &OldMI,
195194
MachineInstr &NewMI);
196195

197196
/// addVirtualRegisterKilled - Add information about the fact that the
198197
/// specified register is killed after being used by the specified
199198
/// instruction. If AddIfNotFound is true, add a implicit operand if it's
200199
/// not found.
201-
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI,
200+
void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI,
202201
bool AddIfNotFound = false) {
203202
if (MI.addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
204203
getVarInfo(IncomingReg).Kills.push_back(&MI);
@@ -208,14 +207,14 @@ class LiveVariables : public MachineFunctionPass {
208207
/// register from the live variable information. Returns true if the
209208
/// variable was marked as killed by the specified instruction,
210209
/// false otherwise.
211-
bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) {
212-
if (!getVarInfo(reg).removeKill(MI))
210+
bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI) {
211+
if (!getVarInfo(Reg).removeKill(MI))
213212
return false;
214213

215214
bool Removed = false;
216215
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
217216
MachineOperand &MO = MI.getOperand(i);
218-
if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
217+
if (MO.isReg() && MO.isKill() && MO.getReg() == Reg) {
219218
MO.setIsKill(false);
220219
Removed = true;
221220
break;
@@ -234,7 +233,7 @@ class LiveVariables : public MachineFunctionPass {
234233
/// addVirtualRegisterDead - Add information about the fact that the specified
235234
/// register is dead after being used by the specified instruction. If
236235
/// AddIfNotFound is true, add a implicit operand if it's not found.
237-
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI,
236+
void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI,
238237
bool AddIfNotFound = false) {
239238
if (MI.addRegisterDead(IncomingReg, TRI, AddIfNotFound))
240239
getVarInfo(IncomingReg).Kills.push_back(&MI);
@@ -244,14 +243,14 @@ class LiveVariables : public MachineFunctionPass {
244243
/// register from the live variable information. Returns true if the
245244
/// variable was marked dead at the specified instruction, false
246245
/// otherwise.
247-
bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) {
248-
if (!getVarInfo(reg).removeKill(MI))
246+
bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI) {
247+
if (!getVarInfo(Reg).removeKill(MI))
249248
return false;
250249

251250
bool Removed = false;
252251
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
253252
MachineOperand &MO = MI.getOperand(i);
254-
if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
253+
if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
255254
MO.setIsDead(false);
256255
Removed = true;
257256
break;
@@ -270,25 +269,25 @@ class LiveVariables : public MachineFunctionPass {
270269

271270
/// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
272271
/// register.
273-
VarInfo &getVarInfo(unsigned RegIdx);
272+
VarInfo &getVarInfo(Register Reg);
274273

275274
void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
276275
MachineBasicBlock *BB);
277276
void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *DefBlock,
278277
MachineBasicBlock *BB,
279278
SmallVectorImpl<MachineBasicBlock *> &WorkList);
280279

281-
void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
282-
void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);
280+
void HandleVirtRegDef(Register reg, MachineInstr &MI);
281+
void HandleVirtRegUse(Register reg, MachineBasicBlock *MBB, MachineInstr &MI);
283282

284-
bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
283+
bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) {
285284
return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
286285
}
287286

288287
/// isLiveOut - Determine if Reg is live out from MBB, when not considering
289288
/// PHI nodes. This means that Reg is either killed by a successor block or
290289
/// passed through one.
291-
bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
290+
bool isLiveOut(Register Reg, const MachineBasicBlock &MBB);
292291

293292
/// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
294293
/// variables that are live out of DomBB and live into SuccBB will be marked
@@ -304,10 +303,10 @@ class LiveVariables : public MachineFunctionPass {
304303
std::vector<SparseBitVector<>> &LiveInSets);
305304

306305
/// isPHIJoin - Return true if Reg is a phi join register.
307-
bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
306+
bool isPHIJoin(Register Reg) { return PHIJoins.test(Reg.id()); }
308307

309308
/// setPHIJoin - Mark Reg as a phi join register.
310-
void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
309+
void setPHIJoin(Register Reg) { PHIJoins.set(Reg.id()); }
311310
};
312311

313312
} // End llvm namespace

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