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MachineBasicBlock: Add liveins() method returning an iterator_range
llvm-svn: 245895
1 parent 008ff14 commit b2b7ef1

20 files changed

+65
-91
lines changed

‎llvm/include/llvm/CodeGen/MachineBasicBlock.h

+3
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,9 @@ class MachineBasicBlock : public ilist_node<MachineBasicBlock> {
336336
livein_iterator livein_begin() const { return LiveIns.begin(); }
337337
livein_iterator livein_end() const { return LiveIns.end(); }
338338
bool livein_empty() const { return LiveIns.empty(); }
339+
iterator_range<livein_iterator> liveins() const {
340+
return make_range(livein_begin(), livein_end());
341+
}
339342

340343
/// Return alignment of the basic block. The alignment is specified as
341344
/// log2(bytes).

‎llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -149,9 +149,8 @@ void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
149149
// Examine the live-in regs of all successors.
150150
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
151151
SE = BB->succ_end(); SI != SE; ++SI)
152-
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
153-
E = (*SI)->livein_end(); I != E; ++I) {
154-
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
152+
for (unsigned LI : (*SI)->liveins()) {
153+
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
155154
unsigned Reg = *AI;
156155
State->UnionGroups(Reg, 0);
157156
KillIndices[Reg] = BB->size();

‎llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,8 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
5757
// Examine the live-in regs of all successors.
5858
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
5959
SE = BB->succ_end(); SI != SE; ++SI)
60-
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
61-
E = (*SI)->livein_end(); I != E; ++I) {
62-
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
60+
for (unsigned LI : (*SI)->liveins()) {
61+
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI) {
6362
unsigned Reg = *AI;
6463
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
6564
KillIndices[Reg] = BBSize;

‎llvm/lib/CodeGen/DeadMachineInstructionElim.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -110,9 +110,8 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
110110
// block.
111111
for (MachineBasicBlock::succ_iterator S = MBB.succ_begin(),
112112
E = MBB.succ_end(); S != E; S++)
113-
for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
114-
LI != (*S)->livein_end(); LI++)
115-
LivePhysRegs.set(*LI);
113+
for (unsigned LI : (*S)->liveins())
114+
LivePhysRegs.set(LI);
116115

117116
// Now scan the instructions and delete dead ones, tracking physreg
118117
// liveness as we go.

‎llvm/lib/CodeGen/ExecutionDepsFix.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -375,9 +375,8 @@ void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
375375

376376
// This is the entry block.
377377
if (MBB->pred_empty()) {
378-
for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
379-
e = MBB->livein_end(); i != e; ++i) {
380-
for (int rx : regIndices(*i)) {
378+
for (unsigned LI : MBB->liveins()) {
379+
for (int rx : regIndices(LI)) {
381380
// Treat function live-ins as if they were defined just before the first
382381
// instruction. Usually, function arguments are set up immediately
383382
// before the call.

‎llvm/lib/CodeGen/LiveIntervalAnalysis.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -305,9 +305,8 @@ void LiveIntervals::computeLiveInRegUnits() {
305305
// Create phi-defs at Begin for all live-in registers.
306306
SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
307307
DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
308-
for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
309-
LIE = MBB->livein_end(); LII != LIE; ++LII) {
310-
for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
308+
for (unsigned LI : MBB->liveins()) {
309+
for (MCRegUnitIterator Units(LI, TRI); Units.isValid(); ++Units) {
311310
unsigned Unit = *Units;
312311
LiveRange *LR = RegUnitRanges[Unit];
313312
if (!LR) {

‎llvm/lib/CodeGen/LivePhysRegs.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -128,8 +128,8 @@ void LivePhysRegs::dump() const {
128128

129129
/// Add live-in registers of basic block \p MBB to \p LiveRegs.
130130
static void addLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB) {
131-
for (unsigned Reg : make_range(MBB.livein_begin(), MBB.livein_end()))
132-
LiveRegs.addReg(Reg);
131+
for (unsigned LI : MBB.liveins())
132+
LiveRegs.addReg(LI);
133133
}
134134

135135
/// Add pristine registers to the given \p LiveRegs. This function removes

‎llvm/lib/CodeGen/LiveVariables.cpp

+6-9
Original file line numberDiff line numberDiff line change
@@ -559,11 +559,10 @@ void LiveVariables::runOnInstr(MachineInstr *MI,
559559
void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
560560
// Mark live-in registers as live-in.
561561
SmallVector<unsigned, 4> Defs;
562-
for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
563-
EE = MBB->livein_end(); II != EE; ++II) {
564-
assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
562+
for (unsigned LI : MBB->liveins()) {
563+
assert(TargetRegisterInfo::isPhysicalRegister(LI) &&
565564
"Cannot have a live-in virtual register!");
566-
HandlePhysRegDef(*II, nullptr, Defs);
565+
HandlePhysRegDef(LI, nullptr, Defs);
567566
}
568567

569568
// Loop over all of the instructions, processing them.
@@ -601,12 +600,10 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
601600
MachineBasicBlock *SuccMBB = *SI;
602601
if (SuccMBB->isLandingPad())
603602
continue;
604-
for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
605-
LE = SuccMBB->livein_end(); LI != LE; ++LI) {
606-
unsigned LReg = *LI;
607-
if (!TRI->isInAllocatableClass(LReg))
603+
for (unsigned LI : SuccMBB->liveins()) {
604+
if (!TRI->isInAllocatableClass(LI))
608605
// Ignore other live-ins, e.g. those that are live into landing pads.
609-
LiveOuts.insert(LReg);
606+
LiveOuts.insert(LI);
610607
}
611608
}
612609

‎llvm/lib/CodeGen/MIRPrinter.cpp

+5-3
Original file line numberDiff line numberDiff line change
@@ -473,10 +473,12 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
473473
assert(TRI && "Expected target register info");
474474
if (!MBB.livein_empty()) {
475475
OS.indent(2) << "liveins: ";
476-
for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
477-
if (I != MBB.livein_begin())
476+
bool First = true;
477+
for (unsigned LI : MBB.liveins()) {
478+
if (!First)
478479
OS << ", ";
479-
printReg(*I, OS, TRI);
480+
First = false;
481+
printReg(LI, OS, TRI);
480482
}
481483
OS << "\n";
482484
HasLineAttributes = true;

‎llvm/lib/CodeGen/MachineBasicBlock.cpp

+6-7
Original file line numberDiff line numberDiff line change
@@ -278,8 +278,9 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
278278
if (!livein_empty()) {
279279
if (Indexes) OS << '\t';
280280
OS << " Live Ins:";
281-
for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
282-
OS << ' ' << PrintReg(*I, TRI);
281+
for (unsigned LI : make_range(livein_begin(), livein_end())) {
282+
OS << ' ' << PrintReg(LI, TRI);
283+
}
283284
OS << '\n';
284285
}
285286
// Print the preds of this block according to the CFG.
@@ -322,8 +323,7 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
322323
}
323324

324325
void MachineBasicBlock::removeLiveIn(unsigned Reg) {
325-
std::vector<unsigned>::iterator I =
326-
std::find(LiveIns.begin(), LiveIns.end(), Reg);
326+
livein_iterator I = std::find(LiveIns.begin(), LiveIns.end(), Reg);
327327
if (I != LiveIns.end())
328328
LiveIns.erase(I);
329329
}
@@ -804,9 +804,8 @@ MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
804804
i->getOperand(ni+1).setMBB(NMBB);
805805

806806
// Inherit live-ins from the successor
807-
for (MachineBasicBlock::livein_iterator I = Succ->livein_begin(),
808-
E = Succ->livein_end(); I != E; ++I)
809-
NMBB->addLiveIn(*I);
807+
for (unsigned LI : Succ->liveins())
808+
NMBB->addLiveIn(LI);
810809

811810
// Update LiveVariables.
812811
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();

‎llvm/lib/CodeGen/MachineLICM.cpp

+2-4
Original file line numberDiff line numberDiff line change
@@ -534,10 +534,8 @@ void MachineLICM::HoistRegionPostRA() {
534534
// Conservatively treat live-in's as an external def.
535535
// FIXME: That means a reload that're reused in successor block(s) will not
536536
// be LICM'ed.
537-
for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
538-
E = BB->livein_end(); I != E; ++I) {
539-
unsigned Reg = *I;
540-
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
537+
for (unsigned LI : BB->liveins()) {
538+
for (MCRegAliasIterator AI(LI, TRI, true); AI.isValid(); ++AI)
541539
PhysRegDefs.set(*AI);
542540
}
543541

‎llvm/lib/CodeGen/MachineVerifier.cpp

+5-9
Original file line numberDiff line numberDiff line change
@@ -507,11 +507,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
507507
if (MRI->isSSA()) {
508508
// If this block has allocatable physical registers live-in, check that
509509
// it is an entry block or landing pad.
510-
for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
511-
LE = MBB->livein_end();
512-
LI != LE; ++LI) {
513-
unsigned reg = *LI;
514-
if (isAllocatable(reg) && !MBB->isLandingPad() &&
510+
for (unsigned LI : MBB->liveins()) {
511+
if (isAllocatable(LI) && !MBB->isLandingPad() &&
515512
MBB != MBB->getParent()->begin()) {
516513
report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
517514
}
@@ -680,13 +677,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
680677
}
681678

682679
regsLive.clear();
683-
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
684-
E = MBB->livein_end(); I != E; ++I) {
685-
if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
680+
for (unsigned LI : MBB->liveins()) {
681+
if (!TargetRegisterInfo::isPhysicalRegister(LI)) {
686682
report("MBB live-in list contains non-physical register", MBB);
687683
continue;
688684
}
689-
for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
685+
for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true);
690686
SubRegs.isValid(); ++SubRegs)
691687
regsLive.insert(*SubRegs);
692688
}

‎llvm/lib/CodeGen/RegAllocFast.cpp

+3-4
Original file line numberDiff line numberDiff line change
@@ -799,10 +799,9 @@ void RAFast::AllocateBasicBlock() {
799799
MachineBasicBlock::iterator MII = MBB->begin();
800800

801801
// Add live-in registers as live.
802-
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
803-
E = MBB->livein_end(); I != E; ++I)
804-
if (MRI->isAllocatable(*I))
805-
definePhysReg(MII, *I, regReserved);
802+
for (unsigned LI : MBB->liveins())
803+
if (MRI->isAllocatable(LI))
804+
definePhysReg(MII, LI, regReserved);
806805

807806
SmallVector<unsigned, 8> VirtDead;
808807
SmallVector<MachineInstr*, 32> Coalesced;

‎llvm/lib/CodeGen/RegisterScavenging.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,8 @@ void RegScavenger::initRegState() {
5050
return;
5151

5252
// Live-in registers are in use.
53-
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
54-
E = MBB->livein_end(); I != E; ++I)
55-
setRegUsed(*I);
53+
for (unsigned LI : MBB->liveins())
54+
setRegUsed(LI);
5655

5756
// Pristine CSRs are also unavailable.
5857
const MachineFunction &MF = *MBB->getParent();

‎llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

+5-9
Original file line numberDiff line numberDiff line change
@@ -242,11 +242,9 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
242242
assert(Uses.empty() && "Uses in set before adding deps?");
243243
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
244244
SE = BB->succ_end(); SI != SE; ++SI)
245-
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
246-
E = (*SI)->livein_end(); I != E; ++I) {
247-
unsigned Reg = *I;
248-
if (!Uses.contains(Reg))
249-
Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg));
245+
for (unsigned LI : (*SI)->liveins()) {
246+
if (!Uses.contains(LI))
247+
Uses.insert(PhysRegSUOper(&ExitSU, -1, LI));
250248
}
251249
}
252250
}
@@ -1080,11 +1078,9 @@ void ScheduleDAGInstrs::startBlockForKills(MachineBasicBlock *BB) {
10801078
// Examine the live-in regs of all successors.
10811079
for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
10821080
SE = BB->succ_end(); SI != SE; ++SI) {
1083-
for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
1084-
E = (*SI)->livein_end(); I != E; ++I) {
1085-
unsigned Reg = *I;
1081+
for (unsigned LI : (*SI)->liveins()) {
10861082
// Repeat, for reg and all subregs.
1087-
for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
1083+
for (MCSubRegIterator SubRegs(LI, TRI, /*IncludeSelf=*/true);
10881084
SubRegs.isValid(); ++SubRegs)
10891085
LiveRegs.set(*SubRegs);
10901086
}

‎llvm/lib/CodeGen/TailDuplication.cpp

+3-4
Original file line numberDiff line numberDiff line change
@@ -791,13 +791,12 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB,
791791
RS->enterBasicBlock(PredBB);
792792
if (!PredBB->empty())
793793
RS->forward(std::prev(PredBB->end()));
794-
for (MachineBasicBlock::livein_iterator I = TailBB->livein_begin(),
795-
E = TailBB->livein_end(); I != E; ++I) {
796-
if (!RS->isRegUsed(*I, false))
794+
for (unsigned LI : TailBB->liveins()) {
795+
if (!RS->isRegUsed(LI, false))
797796
// If a register is previously livein to the tail but it's not live
798797
// at the end of predecessor BB, then it should be added to its
799798
// livein list.
800-
PredBB->addLiveIn(*I);
799+
PredBB->addLiveIn(LI);
801800
}
802801
}
803802

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

+2-4
Original file line numberDiff line numberDiff line change
@@ -1885,11 +1885,9 @@ void ARMFrameLowering::adjustForSegmentedStacks(
18851885
for (int Idx = 0; Idx < NbAddedBlocks; ++Idx)
18861886
BeforePrologueRegion.insert(AddedBlocks[Idx]);
18871887

1888-
for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1889-
e = PrologueMBB.livein_end();
1890-
i != e; ++i) {
1888+
for (unsigned LI : PrologueMBB.liveins()) {
18911889
for (MachineBasicBlock *PredBB : BeforePrologueRegion)
1892-
PredBB->addLiveIn(*i);
1890+
PredBB->addLiveIn(LI);
18931891
}
18941892

18951893
// Remove the newly added blocks from the list, since we know

‎llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -355,9 +355,8 @@ void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
355355
for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
356356
SE = MBB.succ_end(); SI != SE; ++SI)
357357
if (*SI != &SuccBB)
358-
for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(),
359-
LE = (*SI)->livein_end(); LI != LE; ++LI)
360-
Uses.set(*LI);
358+
for (unsigned LI : (*SI)->liveins())
359+
Uses.set(LI);
361360
}
362361

363362
bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {

‎llvm/lib/Target/X86/X86FloatingPoint.cpp

+3-5
Original file line numberDiff line numberDiff line change
@@ -120,12 +120,10 @@ namespace {
120120
// Return a bitmask of FP registers in block's live-in list.
121121
static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
122122
unsigned Mask = 0;
123-
for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
124-
E = MBB->livein_end(); I != E; ++I) {
125-
unsigned Reg = *I;
126-
if (Reg < X86::FP0 || Reg > X86::FP6)
123+
for (unsigned LI : MBB->liveins()) {
124+
if (LI < X86::FP0 || LI > X86::FP6)
127125
continue;
128-
Mask |= 1 << (Reg - X86::FP0);
126+
Mask |= 1 << (LI - X86::FP0);
129127
}
130128
return Mask;
131129
}

‎llvm/lib/Target/X86/X86FrameLowering.cpp

+6-10
Original file line numberDiff line numberDiff line change
@@ -1518,11 +1518,9 @@ void X86FrameLowering::adjustForSegmentedStacks(
15181518
// The MOV R10, RAX needs to be in a different block, since the RET we emit in
15191519
// allocMBB needs to be last (terminating) instruction.
15201520

1521-
for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1522-
e = PrologueMBB.livein_end();
1523-
i != e; i++) {
1524-
allocMBB->addLiveIn(*i);
1525-
checkMBB->addLiveIn(*i);
1521+
for (unsigned LI : PrologueMBB.liveins()) {
1522+
allocMBB->addLiveIn(LI);
1523+
checkMBB->addLiveIn(LI);
15261524
}
15271525

15281526
if (IsNested)
@@ -1792,11 +1790,9 @@ void X86FrameLowering::adjustForHiPEPrologue(
17921790
MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
17931791
MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
17941792

1795-
for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
1796-
E = PrologueMBB.livein_end();
1797-
I != E; I++) {
1798-
stackCheckMBB->addLiveIn(*I);
1799-
incStackMBB->addLiveIn(*I);
1793+
for (unsigned LI : PrologueMBB.liveins()) {
1794+
stackCheckMBB->addLiveIn(LI);
1795+
incStackMBB->addLiveIn(LI);
18001796
}
18011797

18021798
MF.push_front(incStackMBB);

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