@@ -11,6 +11,15 @@ define i1 @tautological_ule(i8 %x) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @tautological_ule_vec (<2 x i8 > %x ) {
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+ ; CHECK-LABEL: @tautological_ule_vec(
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ule <2 x i8> %x, <i8 -1, i8 -1>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %cmp = icmp ule <2 x i8 > %x , <i8 255 , i8 255 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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define i1 @tautological_ugt (i8 %x ) {
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; CHECK-LABEL: @tautological_ugt(
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; CHECK-NEXT: ret i1 false
@@ -19,6 +28,15 @@ define i1 @tautological_ugt(i8 %x) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @tautological_ugt_vec (<2 x i8 > %x ) {
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+ ; CHECK-LABEL: @tautological_ugt_vec(
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> %x, <i8 -1, i8 -1>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %cmp = icmp ugt <2 x i8 > %x , <i8 255 , i8 255 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'urem x, C2' produces [0, C2)
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define i1 @urem3 (i32 %X ) {
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; CHECK-LABEL: @urem3(
@@ -29,6 +47,17 @@ define i1 @urem3(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @urem3_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @urem3_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = urem <2 x i32> %X, <i32 10, i32 10>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 15, i32 15>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = urem <2 x i32 > %X , <i32 10 , i32 10 >
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+ %B = icmp ult <2 x i32 > %A , <i32 15 , i32 15 >
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+ ret <2 x i1 > %B
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+ }
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+
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;'srem x, C2' produces (-|C2|, |C2|)
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define i1 @srem1 (i32 %X ) {
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; CHECK-LABEL: @srem1(
@@ -39,6 +68,17 @@ define i1 @srem1(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @srem1_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @srem1_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = srem <2 x i32> %X, <i32 -5, i32 -5>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp sgt <2 x i32> [[A]], <i32 5, i32 5>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = srem <2 x i32 > %X , <i32 -5 , i32 -5 >
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+ %B = icmp sgt <2 x i32 > %A , <i32 5 , i32 5 >
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+ ret <2 x i1 > %B
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+ }
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+
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;'udiv C2, x' produces [0, C2]
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define i1 @udiv5 (i32 %X ) {
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; CHECK-LABEL: @udiv5(
@@ -49,6 +89,17 @@ define i1 @udiv5(i32 %X) {
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ret i1 %C
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}
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+ define <2 x i1 > @udiv5_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @udiv5_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = udiv <2 x i32> <i32 123, i32 123>, %X
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+ ; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A]], <i32 124, i32 124>
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+ ; CHECK-NEXT: ret <2 x i1> [[C]]
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+ ;
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+ %A = udiv <2 x i32 > <i32 123 , i32 123 >, %X
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+ %C = icmp ugt <2 x i32 > %A , <i32 124 , i32 124 >
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+ ret <2 x i1 > %C
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+ }
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+
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; 'udiv x, C2' produces [0, UINT_MAX / C2]
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define i1 @udiv1 (i32 %X ) {
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; CHECK-LABEL: @udiv1(
@@ -59,6 +110,17 @@ define i1 @udiv1(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @udiv1_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @udiv1_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = udiv <2 x i32> %X, <i32 1000000, i32 1000000>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 5000, i32 5000>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = udiv <2 x i32 > %X , <i32 1000000 , i32 1000000 >
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+ %B = icmp ult <2 x i32 > %A , <i32 5000 , i32 5000 >
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+ ret <2 x i1 > %B
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+ }
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+
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; 'sdiv C2, x' produces [-|C2|, |C2|]
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define i1 @compare_dividend (i32 %a ) {
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; CHECK-LABEL: @compare_dividend(
@@ -69,6 +131,17 @@ define i1 @compare_dividend(i32 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @compare_dividend_vec (<2 x i32 > %a ) {
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+ ; CHECK-LABEL: @compare_dividend_vec(
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+ ; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i32> <i32 2, i32 2>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[DIV]], <i32 3, i32 3>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %div = sdiv <2 x i32 > <i32 2 , i32 2 >, %a
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+ %cmp = icmp eq <2 x i32 > %div , <i32 3 , i32 3 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'sdiv x, C2' produces [INT_MIN / C2, INT_MAX / C2]
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; where C2 != -1 and C2 != 0 and C2 != 1
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define i1 @sdiv1 (i32 %X ) {
@@ -80,6 +153,17 @@ define i1 @sdiv1(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @sdiv1_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @sdiv1_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = sdiv <2 x i32> %X, <i32 1000000, i32 1000000>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp slt <2 x i32> [[A]], <i32 3000, i32 3000>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = sdiv <2 x i32 > %X , <i32 1000000 , i32 1000000 >
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+ %B = icmp slt <2 x i32 > %A , <i32 3000 , i32 3000 >
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+ ret <2 x i1 > %B
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+ }
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+
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; 'shl nuw C2, x' produces [C2, C2 << CLZ(C2)]
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define i1 @shl5 (i32 %X ) {
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; CHECK-LABEL: @shl5(
@@ -90,6 +174,17 @@ define i1 @shl5(i32 %X) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @shl5_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @shl5_vec(
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+ ; CHECK-NEXT: [[SUB:%.*]] = shl nuw <2 x i32> <i32 4, i32 4>, %X
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[SUB]], <i32 3, i32 3>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %sub = shl nuw <2 x i32 > <i32 4 , i32 4 >, %X
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+ %cmp = icmp ugt <2 x i32 > %sub , <i32 3 , i32 3 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2]
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define i1 @shl2 (i32 %X ) {
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; CHECK-LABEL: @shl2(
@@ -100,6 +195,17 @@ define i1 @shl2(i32 %X) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @shl2_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @shl2_vec(
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+ ; CHECK-NEXT: [[SUB:%.*]] = shl nsw <2 x i32> <i32 -1, i32 -1>, %X
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[SUB]], <i32 31, i32 31>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %sub = shl nsw <2 x i32 > <i32 -1 , i32 -1 >, %X
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+ %cmp = icmp eq <2 x i32 > %sub , <i32 31 , i32 31 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2]
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define i1 @shl4 (i32 %X ) {
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; CHECK-LABEL: @shl4(
@@ -110,6 +216,17 @@ define i1 @shl4(i32 %X) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @shl4_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @shl4_vec(
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+ ; CHECK-NEXT: [[SUB:%.*]] = shl nsw <2 x i32> <i32 -1, i32 -1>, %X
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sle <2 x i32> [[SUB]], <i32 -1, i32 -1>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %sub = shl nsw <2 x i32 > <i32 -1 , i32 -1 >, %X
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+ %cmp = icmp sle <2 x i32 > %sub , <i32 -1 , i32 -1 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'shl nsw C2, x' produces [C2, C2 << CLZ(C2)-1]
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define i1 @icmp_shl_nsw_1 (i64 %a ) {
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; CHECK-LABEL: @icmp_shl_nsw_1(
@@ -120,6 +237,17 @@ define i1 @icmp_shl_nsw_1(i64 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @icmp_shl_nsw_1_vec (<2 x i64 > %a ) {
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+ ; CHECK-LABEL: @icmp_shl_nsw_1_vec(
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+ ; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i64> <i64 1, i64 1>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i64> [[SHL]], zeroinitializer
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shl = shl nsw <2 x i64 > <i64 1 , i64 1 >, %a
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+ %cmp = icmp sge <2 x i64 > %shl , zeroinitializer
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2]
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define i1 @icmp_shl_nsw_neg1 (i64 %a ) {
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; CHECK-LABEL: @icmp_shl_nsw_neg1(
@@ -130,6 +258,17 @@ define i1 @icmp_shl_nsw_neg1(i64 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @icmp_shl_nsw_neg1_vec (<2 x i64 > %a ) {
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+ ; CHECK-LABEL: @icmp_shl_nsw_neg1_vec(
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+ ; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i64> <i64 -1, i64 -1>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i64> [[SHL]], <i64 3, i64 3>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shl = shl nsw <2 x i64 > <i64 -1 , i64 -1 >, %a
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+ %cmp = icmp sge <2 x i64 > %shl , <i64 3 , i64 3 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'lshr x, C2' produces [0, UINT_MAX >> C2]
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define i1 @lshr2 (i32 %x ) {
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; CHECK-LABEL: @lshr2(
@@ -140,6 +279,17 @@ define i1 @lshr2(i32 %x) {
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ret i1 %c
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}
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+ define <2 x i1 > @lshr2_vec (<2 x i32 > %x ) {
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+ ; CHECK-LABEL: @lshr2_vec(
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+ ; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> %x, <i32 30, i32 30>
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+ ; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[S]], <i32 8, i32 8>
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+ ; CHECK-NEXT: ret <2 x i1> [[C]]
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+ ;
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+ %s = lshr <2 x i32 > %x , <i32 30 , i32 30 >
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+ %c = icmp ugt <2 x i32 > %s , <i32 8 , i32 8 >
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+ ret <2 x i1 > %c
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+ }
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+
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; 'lshr C2, x' produces [C2 >> (Width-1), C2]
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define i1 @exact_lshr_ugt_false (i32 %a ) {
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; CHECK-LABEL: @exact_lshr_ugt_false(
@@ -150,6 +300,17 @@ define i1 @exact_lshr_ugt_false(i32 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @exact_lshr_ugt_false_vec (<2 x i32 > %a ) {
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+ ; CHECK-LABEL: @exact_lshr_ugt_false_vec(
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+ ; CHECK-NEXT: [[SHR:%.*]] = lshr exact <2 x i32> <i32 30, i32 30>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[SHR]], <i32 15, i32 15>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shr = lshr exact <2 x i32 > <i32 30 , i32 30 >, %a
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+ %cmp = icmp ult <2 x i32 > %shr , <i32 15 , i32 15 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'lshr C2, x' produces [C2 >> (Width-1), C2]
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define i1 @lshr_sgt_false (i32 %a ) {
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; CHECK-LABEL: @lshr_sgt_false(
@@ -160,6 +321,17 @@ define i1 @lshr_sgt_false(i32 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @lshr_sgt_false_vec (<2 x i32 > %a ) {
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+ ; CHECK-LABEL: @lshr_sgt_false_vec(
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+ ; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> <i32 1, i32 1>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 1, i32 1>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shr = lshr <2 x i32 > <i32 1 , i32 1 >, %a
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+ %cmp = icmp sgt <2 x i32 > %shr , <i32 1 , i32 1 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'ashr x, C2' produces [INT_MIN >> C2, INT_MAX >> C2]
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define i1 @ashr2 (i32 %x ) {
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; CHECK-LABEL: @ashr2(
@@ -170,6 +342,17 @@ define i1 @ashr2(i32 %x) {
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ret i1 %c
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}
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+ define <2 x i1 > @ashr2_vec (<2 x i32 > %x ) {
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+ ; CHECK-LABEL: @ashr2_vec(
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+ ; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> %x, <i32 30, i32 30>
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+ ; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[S]], <i32 -5, i32 -5>
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+ ; CHECK-NEXT: ret <2 x i1> [[C]]
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+ ;
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+ %s = ashr <2 x i32 > %x , <i32 30 , i32 30 >
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+ %c = icmp slt <2 x i32 > %s , <i32 -5 , i32 -5 >
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+ ret <2 x i1 > %c
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+ }
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+
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; 'ashr C2, x' produces [C2, C2 >> (Width-1)]
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define i1 @ashr_sgt_false (i32 %a ) {
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; CHECK-LABEL: @ashr_sgt_false(
@@ -180,6 +363,17 @@ define i1 @ashr_sgt_false(i32 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @ashr_sgt_false_vec (<2 x i32 > %a ) {
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+ ; CHECK-LABEL: @ashr_sgt_false_vec(
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+ ; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i32> <i32 -30, i32 -30>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 -1, i32 -1>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shr = ashr <2 x i32 > <i32 -30 , i32 -30 >, %a
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+ %cmp = icmp sgt <2 x i32 > %shr , <i32 -1 , i32 -1 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'ashr C2, x' produces [C2, C2 >> (Width-1)]
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define i1 @exact_ashr_sgt_false (i32 %a ) {
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; CHECK-LABEL: @exact_ashr_sgt_false(
@@ -190,6 +384,17 @@ define i1 @exact_ashr_sgt_false(i32 %a) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @exact_ashr_sgt_false_vec (<2 x i32 > %a ) {
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+ ; CHECK-LABEL: @exact_ashr_sgt_false_vec(
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+ ; CHECK-NEXT: [[SHR:%.*]] = ashr exact <2 x i32> <i32 -30, i32 -30>, %a
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 -15, i32 -15>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %shr = ashr exact <2 x i32 > <i32 -30 , i32 -30 >, %a
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+ %cmp = icmp sgt <2 x i32 > %shr , <i32 -15 , i32 -15 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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; 'or x, C2' produces [C2, UINT_MAX]
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define i1 @or1 (i32 %X ) {
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; CHECK-LABEL: @or1(
@@ -200,6 +405,17 @@ define i1 @or1(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @or1_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @or1_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = or <2 x i32> %X, <i32 62, i32 62>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 50, i32 50>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = or <2 x i32 > %X , <i32 62 , i32 62 >
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+ %B = icmp ult <2 x i32 > %A , <i32 50 , i32 50 >
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+ ret <2 x i1 > %B
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+ }
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+
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; 'and x, C2' produces [0, C2]
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define i1 @and1 (i32 %X ) {
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; CHECK-LABEL: @and1(
@@ -210,6 +426,17 @@ define i1 @and1(i32 %X) {
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ret i1 %B
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}
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+ define <2 x i1 > @and1_vec (<2 x i32 > %X ) {
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+ ; CHECK-LABEL: @and1_vec(
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+ ; CHECK-NEXT: [[A:%.*]] = and <2 x i32> %X, <i32 62, i32 62>
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+ ; CHECK-NEXT: [[B:%.*]] = icmp ugt <2 x i32> [[A]], <i32 70, i32 70>
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+ ; CHECK-NEXT: ret <2 x i1> [[B]]
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+ ;
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+ %A = and <2 x i32 > %X , <i32 62 , i32 62 >
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+ %B = icmp ugt <2 x i32 > %A , <i32 70 , i32 70 >
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+ ret <2 x i1 > %B
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+ }
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+
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; 'add nuw x, C2' produces [C2, UINT_MAX]
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define i1 @tautological9 (i32 %x ) {
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; CHECK-LABEL: @tautological9(
@@ -220,3 +447,14 @@ define i1 @tautological9(i32 %x) {
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ret i1 %cmp
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}
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+ define <2 x i1 > @tautological9_vec (<2 x i32 > %x ) {
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+ ; CHECK-LABEL: @tautological9_vec(
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+ ; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i32> %x, <i32 13, i32 13>
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[ADD]], <i32 12, i32 12>
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+ ; CHECK-NEXT: ret <2 x i1> [[CMP]]
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+ ;
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+ %add = add nuw <2 x i32 > %x , <i32 13 , i32 13 >
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+ %cmp = icmp ne <2 x i32 > %add , <i32 12 , i32 12 >
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+ ret <2 x i1 > %cmp
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+ }
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+
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