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[ARM][SchedModels] Convert IsPredicatedPred to MCSchedPredicate
Differential revision: https://reviews.llvm.org/D89553
1 parent dfb2266 commit 8a7ca14

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13 files changed

+107
-50
lines changed

13 files changed

+107
-50
lines changed

‎llvm/include/llvm/MC/MCSubtargetInfo.h

+4-3
Original file line numberDiff line numberDiff line change
@@ -213,9 +213,10 @@ class MCSubtargetInfo {
213213
void initInstrItins(InstrItineraryData &InstrItins) const;
214214

215215
/// Resolve a variant scheduling class for the given MCInst and CPU.
216-
virtual unsigned
217-
resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
218-
unsigned CPUID) const {
216+
virtual unsigned resolveVariantSchedClass(unsigned SchedClass,
217+
const MCInst *MI,
218+
const MCInstrInfo *MCII,
219+
unsigned CPUID) const {
219220
return 0;
220221
}
221222

‎llvm/include/llvm/Target/TargetInstrPredicate.td

+14
Original file line numberDiff line numberDiff line change
@@ -254,6 +254,20 @@ class CheckFunctionPredicate<string MCInstFn, string MachineInstrFn> : MCInstPre
254254
string MachineInstrFnName = MachineInstrFn;
255255
}
256256

257+
// Similar to CheckFunctionPredicate. However it assumes that MachineInstrFn is
258+
// a method in TargetInstrInfo, and MCInstrFn takes an extra pointer to
259+
// MCInstrInfo.
260+
//
261+
// It Expands to:
262+
// - TIIPointer->MachineInstrFn(MI)
263+
// - MCInstrFn(MI, MCII);
264+
class CheckFunctionPredicateWithTII<string MCInstFn, string MachineInstrFn, string
265+
TIIPointer = "TII"> : MCInstPredicate {
266+
string MCInstFnName = MCInstFn;
267+
string TIIPtrName = TIIPointer;
268+
string MachineInstrFnName = MachineInstrFn;
269+
}
270+
257271
// Used to classify machine instructions based on a machine instruction
258272
// predicate.
259273
//

‎llvm/lib/MC/MCSchedule.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
7474

7575
unsigned CPUID = getProcessorID();
7676
while (SCDesc->isVariant()) {
77-
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
77+
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
7878
SCDesc = getSchedClassDesc(SchedClass);
7979
}
8080

@@ -120,7 +120,7 @@ MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
120120

121121
unsigned CPUID = getProcessorID();
122122
while (SCDesc->isVariant()) {
123-
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
123+
SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID);
124124
SCDesc = getSchedClassDesc(SchedClass);
125125
}
126126

‎llvm/lib/MCA/InstrBuilder.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -518,7 +518,8 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
518518
if (IsVariant) {
519519
unsigned CPUID = SM.getProcessorID();
520520
while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
521-
SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
521+
SchedClassID =
522+
STI.resolveVariantSchedClass(SchedClassID, &MCI, &MCII, CPUID);
522523

523524
if (!SchedClassID) {
524525
return make_error<InstructionError<MCInst>>(

‎llvm/lib/Target/ARM/ARMSchedule.td

+5-1
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,11 @@ def : PredicateProlog<[{
151151
(void)STI;
152152
}]>;
153153

154-
def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(*MI)}]>;
154+
def IsPredicated : CheckFunctionPredicateWithTII<
155+
"ARM_MC::isPredicated",
156+
"isPredicated"
157+
>;
158+
def IsPredicatedPred : MCSchedPredicate<IsPredicated>;
155159

156160
//===----------------------------------------------------------------------===//
157161
// Instruction Itinerary classes used for ARM

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,12 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
180180
return ARMArchFeature;
181181
}
182182

183+
bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
184+
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
185+
int PredOpIdx = Desc.findFirstPredOperandIdx();
186+
return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
187+
}
188+
183189
MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
184190
StringRef CPU, StringRef FS) {
185191
std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);

‎llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

+2
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,8 @@ class raw_pwrite_stream;
4242
namespace ARM_MC {
4343
std::string ParseARMTriple(const Triple &TT, StringRef CPU);
4444

45+
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
46+
4547
/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
4648
/// do not need to go through TargetRegistry.
4749
MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,

‎llvm/test/tools/llvm-mca/ARM/cortex-a57-basic-instructions.s

+30-30
Original file line numberDiff line numberDiff line change
@@ -1205,8 +1205,8 @@
12051205
# CHECK-NEXT: 1 1 0.50 mvnseq r2, r3, lsl #10
12061206
# CHECK-NEXT: 1 1 0.50 mvn r5, r6, lsl r7
12071207
# CHECK-NEXT: 1 1 0.50 mvns r5, r6, lsr r7
1208-
# CHECK-NEXT: 1 1 0.50 mvngt r5, r6, asr r7
1209-
# CHECK-NEXT: 1 1 0.50 mvnslt r5, r6, ror r7
1208+
# CHECK-NEXT: 1 2 0.50 mvngt r5, r6, asr r7
1209+
# CHECK-NEXT: 1 2 0.50 mvnslt r5, r6, ror r7
12101210
# CHECK-NEXT: 0 0 0.00 * * U nop
12111211
# CHECK-NEXT: 0 0 0.00 * * U nopgt
12121212
# CHECK-NEXT: 1 1 0.50 orr r4, r5, #61440
@@ -1238,12 +1238,12 @@
12381238
# CHECK-NEXT: 1 1 0.50 orrseq r4, r5, #61440
12391239
# CHECK-NEXT: 1 1 0.50 orrne r4, r5, r6
12401240
# CHECK-NEXT: 1 2 1.00 orrseq r4, r5, r6, lsl #5
1241-
# CHECK-NEXT: 1 2 1.00 orrlo r6, r7, r8, ror r9
1241+
# CHECK-NEXT: 1 2 0.50 orrlo r6, r7, r8, ror r9
12421242
# CHECK-NEXT: 1 2 1.00 orrshi r4, r5, r6, rrx
12431243
# CHECK-NEXT: 1 1 0.50 orrhs r5, r5, #61440
12441244
# CHECK-NEXT: 1 1 0.50 orrseq r4, r4, r5
1245-
# CHECK-NEXT: 1 2 1.00 orrne r6, r6, r7, asr r9
1246-
# CHECK-NEXT: 1 2 1.00 orrslt r6, r6, r7, ror r9
1245+
# CHECK-NEXT: 1 2 0.50 orrne r6, r6, r7, asr r9
1246+
# CHECK-NEXT: 1 2 0.50 orrslt r6, r6, r7, ror r9
12471247
# CHECK-NEXT: 1 2 1.00 orrsgt r4, r4, r5, rrx
12481248
# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3
12491249
# CHECK-NEXT: 1 2 1.00 pkhbt r2, r2, r3, lsl #31
@@ -1312,7 +1312,7 @@
13121312
# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, lsl r9
13131313
# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, lsr r9
13141314
# CHECK-NEXT: 1 2 1.00 rsb r6, r7, r8, asr r9
1315-
# CHECK-NEXT: 1 2 1.00 rsble r6, r7, r8, ror r9
1315+
# CHECK-NEXT: 1 2 0.50 rsble r6, r7, r8, ror r9
13161316
# CHECK-NEXT: 1 2 1.00 rsb r4, r5, r6, rrx
13171317
# CHECK-NEXT: 1 1 0.50 rsb r5, r5, #61440
13181318
# CHECK-NEXT: 1 1 0.50 U rsb r4, r4, r5
@@ -1321,7 +1321,7 @@
13211321
# CHECK-NEXT: 1 2 1.00 rsbne r4, r4, r5, lsr #5
13221322
# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, asr #5
13231323
# CHECK-NEXT: 1 2 1.00 rsb r4, r4, r5, ror #5
1324-
# CHECK-NEXT: 1 2 1.00 rsbgt r6, r6, r7, lsl r9
1324+
# CHECK-NEXT: 1 2 0.50 rsbgt r6, r6, r7, lsl r9
13251325
# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, lsr r9
13261326
# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, asr r9
13271327
# CHECK-NEXT: 1 2 1.00 rsb r6, r6, r7, ror r9
@@ -1340,15 +1340,15 @@
13401340
# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, lsl r9
13411341
# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, lsr r9
13421342
# CHECK-NEXT: 1 2 1.00 rsc r6, r7, r8, asr r9
1343-
# CHECK-NEXT: 1 2 1.00 rscle r6, r7, r8, ror r9
1343+
# CHECK-NEXT: 1 2 0.50 rscle r6, r7, r8, ror r9
13441344
# CHECK-NEXT: 1 1 0.50 rsc r5, r5, #61440
13451345
# CHECK-NEXT: 1 1 0.50 U rsc r4, r4, r5
13461346
# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, lsl #5
13471347
# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, lsr #5
13481348
# CHECK-NEXT: 1 2 1.00 rscne r4, r4, r5, lsr #5
13491349
# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, asr #5
13501350
# CHECK-NEXT: 1 2 1.00 rsc r4, r4, r5, ror #5
1351-
# CHECK-NEXT: 1 2 1.00 rscgt r6, r6, r7, lsl r9
1351+
# CHECK-NEXT: 1 2 0.50 rscgt r6, r6, r7, lsl r9
13521352
# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, lsr r9
13531353
# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, asr r9
13541354
# CHECK-NEXT: 1 2 1.00 rsc r6, r6, r7, ror r9
@@ -1361,11 +1361,11 @@
13611361
# CHECK-NEXT: 1 1 0.50 rrxs pc, lr
13621362
# CHECK-NEXT: 1 1 0.50 rrxs lr, sp
13631363
# CHECK-NEXT: 2 2 1.00 * * U sadd16 r1, r2, r3
1364-
# CHECK-NEXT: 2 2 1.00 * * U sadd16gt r1, r2, r3
1364+
# CHECK-NEXT: 2 4 1.00 * * U sadd16gt r1, r2, r3
13651365
# CHECK-NEXT: 2 2 1.00 * * U sadd8 r1, r2, r3
1366-
# CHECK-NEXT: 2 2 1.00 * * U sadd8le r1, r2, r3
1366+
# CHECK-NEXT: 2 4 1.00 * * U sadd8le r1, r2, r3
13671367
# CHECK-NEXT: 2 3 1.00 * * U sasx r9, r12, r0
1368-
# CHECK-NEXT: 2 3 1.00 * * U sasxeq r9, r12, r0
1368+
# CHECK-NEXT: 2 5 1.00 * * U sasxeq r9, r12, r0
13691369
# CHECK-NEXT: 1 1 0.50 sbc r4, r5, #61440
13701370
# CHECK-NEXT: 1 1 0.50 sbc r7, r8, #-2147483638
13711371
# CHECK-NEXT: 1 1 0.50 sbc r7, r8, #40, #2
@@ -1393,7 +1393,7 @@
13931393
# CHECK-NEXT: 1 1 0.50 U sbfx r4, r5, #16, #1
13941394
# CHECK-NEXT: 1 1 0.50 U sbfxgt r4, r5, #16, #16
13951395
# CHECK-NEXT: 1 1 0.50 * sel r9, r2, r1
1396-
# CHECK-NEXT: 1 1 0.50 * selne r9, r2, r1
1396+
# CHECK-NEXT: 1 2 0.50 * selne r9, r2, r1
13971397
# CHECK-NEXT: 0 0 0.00 U setend be
13981398
# CHECK-NEXT: 0 0 0.00 U setend le
13991399
# CHECK-NEXT: 0 0 0.00 * * U sev
@@ -1507,11 +1507,11 @@
15071507
# CHECK-NEXT: 1 2 1.00 ssat16 r2, #1, r7
15081508
# CHECK-NEXT: 1 2 1.00 ssat16 r3, #16, r5
15091509
# CHECK-NEXT: 2 3 1.00 * * U ssax r2, r3, r4
1510-
# CHECK-NEXT: 2 3 1.00 * * U ssaxlt r2, r3, r4
1510+
# CHECK-NEXT: 2 5 1.00 * * U ssaxlt r2, r3, r4
15111511
# CHECK-NEXT: 2 2 1.00 * * U ssub16 r1, r0, r6
1512-
# CHECK-NEXT: 2 2 1.00 * * U ssub16ne r5, r3, r2
1512+
# CHECK-NEXT: 2 4 1.00 * * U ssub16ne r5, r3, r2
15131513
# CHECK-NEXT: 2 2 1.00 * * U ssub8 r9, r2, r4
1514-
# CHECK-NEXT: 2 2 1.00 * * U ssub8eq r5, r1, r2
1514+
# CHECK-NEXT: 2 4 1.00 * * U ssub8eq r5, r1, r2
15151515
# CHECK-NEXT: 1 2 1.00 * stm r2, {r1, r3, r4, r5, r6, sp}
15161516
# CHECK-NEXT: 1 2 1.00 * stm r3, {r1, r3, r4, r5, r6, lr}
15171517
# CHECK-NEXT: 1 2 1.00 * stmib r4, {r1, r3, r4, r5, r6, sp}
@@ -1613,11 +1613,11 @@
16131613
# CHECK-NEXT: 1 2 1.00 tst r6, r7, asr r9
16141614
# CHECK-NEXT: 1 2 1.00 tst r6, r7, ror r9
16151615
# CHECK-NEXT: 2 2 1.00 * * U uadd16 r1, r2, r3
1616-
# CHECK-NEXT: 2 2 1.00 * * U uadd16gt r1, r2, r3
1616+
# CHECK-NEXT: 2 4 1.00 * * U uadd16gt r1, r2, r3
16171617
# CHECK-NEXT: 2 2 1.00 * * U uadd8 r1, r2, r3
1618-
# CHECK-NEXT: 2 2 1.00 * * U uadd8le r1, r2, r3
1618+
# CHECK-NEXT: 2 4 1.00 * * U uadd8le r1, r2, r3
16191619
# CHECK-NEXT: 2 3 1.00 * * U uasx r9, r12, r0
1620-
# CHECK-NEXT: 2 3 1.00 * * U uasxeq r9, r12, r0
1620+
# CHECK-NEXT: 2 5 1.00 * * U uasxeq r9, r12, r0
16211621
# CHECK-NEXT: 1 1 0.50 U ubfx r4, r5, #16, #1
16221622
# CHECK-NEXT: 1 1 0.50 U ubfxgt r4, r5, #16, #16
16231623
# CHECK-NEXT: 1 2 1.00 uhadd16 r4, r8, r2
@@ -1664,11 +1664,11 @@
16641664
# CHECK-NEXT: 1 2 1.00 usat16 r2, #2, r7
16651665
# CHECK-NEXT: 1 2 1.00 usat16 r3, #15, r5
16661666
# CHECK-NEXT: 2 3 1.00 * * U usax r2, r3, r4
1667-
# CHECK-NEXT: 2 3 1.00 * * U usaxne r2, r3, r4
1667+
# CHECK-NEXT: 2 5 1.00 * * U usaxne r2, r3, r4
16681668
# CHECK-NEXT: 2 2 1.00 * * U usub16 r4, r2, r7
1669-
# CHECK-NEXT: 2 2 1.00 * * U usub16hi r1, r1, r3
1669+
# CHECK-NEXT: 2 4 1.00 * * U usub16hi r1, r1, r3
16701670
# CHECK-NEXT: 2 2 1.00 * * U usub8 r1, r8, r5
1671-
# CHECK-NEXT: 2 2 1.00 * * U usub8le r9, r2, r3
1671+
# CHECK-NEXT: 2 4 1.00 * * U usub8le r9, r2, r3
16721672
# CHECK-NEXT: 1 2 1.00 uxtab r2, r3, r4
16731673
# CHECK-NEXT: 1 2 1.00 uxtab r4, r5, r6
16741674
# CHECK-NEXT: 1 2 1.00 uxtablt r6, r2, r9, ror #8
@@ -1719,7 +1719,7 @@
17191719

17201720
# CHECK: Resource pressure per iteration:
17211721
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
1722-
# CHECK-NEXT: 8.00 158.50 158.50 171.00 497.00 12.00 - -
1722+
# CHECK-NEXT: 8.00 162.00 162.00 171.00 490.00 12.00 - -
17231723

17241724
# CHECK: Resource pressure by instruction:
17251725
# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
@@ -2102,12 +2102,12 @@
21022102
# CHECK-NEXT: - 0.50 0.50 - - - - - orrseq r4, r5, #61440
21032103
# CHECK-NEXT: - 0.50 0.50 - - - - - orrne r4, r5, r6
21042104
# CHECK-NEXT: - - - - 1.00 - - - orrseq r4, r5, r6, lsl #5
2105-
# CHECK-NEXT: - - - - 1.00 - - - orrlo r6, r7, r8, ror r9
2105+
# CHECK-NEXT: - 0.50 0.50 - - - - - orrlo r6, r7, r8, ror r9
21062106
# CHECK-NEXT: - - - - 1.00 - - - orrshi r4, r5, r6, rrx
21072107
# CHECK-NEXT: - 0.50 0.50 - - - - - orrhs r5, r5, #61440
21082108
# CHECK-NEXT: - 0.50 0.50 - - - - - orrseq r4, r4, r5
2109-
# CHECK-NEXT: - - - - 1.00 - - - orrne r6, r6, r7, asr r9
2110-
# CHECK-NEXT: - - - - 1.00 - - - orrslt r6, r6, r7, ror r9
2109+
# CHECK-NEXT: - 0.50 0.50 - - - - - orrne r6, r6, r7, asr r9
2110+
# CHECK-NEXT: - 0.50 0.50 - - - - - orrslt r6, r6, r7, ror r9
21112111
# CHECK-NEXT: - - - - 1.00 - - - orrsgt r4, r4, r5, rrx
21122112
# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3
21132113
# CHECK-NEXT: - - - - 1.00 - - - pkhbt r2, r2, r3, lsl #31
@@ -2176,7 +2176,7 @@
21762176
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, lsl r9
21772177
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, lsr r9
21782178
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r7, r8, asr r9
2179-
# CHECK-NEXT: - - - - 1.00 - - - rsble r6, r7, r8, ror r9
2179+
# CHECK-NEXT: - 0.50 0.50 - - - - - rsble r6, r7, r8, ror r9
21802180
# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r5, r6, rrx
21812181
# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r5, r5, #61440
21822182
# CHECK-NEXT: - 0.50 0.50 - - - - - rsb r4, r4, r5
@@ -2185,7 +2185,7 @@
21852185
# CHECK-NEXT: - - - - 1.00 - - - rsbne r4, r4, r5, lsr #5
21862186
# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, asr #5
21872187
# CHECK-NEXT: - - - - 1.00 - - - rsb r4, r4, r5, ror #5
2188-
# CHECK-NEXT: - - - - 1.00 - - - rsbgt r6, r6, r7, lsl r9
2188+
# CHECK-NEXT: - 0.50 0.50 - - - - - rsbgt r6, r6, r7, lsl r9
21892189
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, lsr r9
21902190
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, asr r9
21912191
# CHECK-NEXT: - - - - 1.00 - - - rsb r6, r6, r7, ror r9
@@ -2204,15 +2204,15 @@
22042204
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, lsl r9
22052205
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, lsr r9
22062206
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r7, r8, asr r9
2207-
# CHECK-NEXT: - - - - 1.00 - - - rscle r6, r7, r8, ror r9
2207+
# CHECK-NEXT: - 0.50 0.50 - - - - - rscle r6, r7, r8, ror r9
22082208
# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r5, r5, #61440
22092209
# CHECK-NEXT: - 0.50 0.50 - - - - - rsc r4, r4, r5
22102210
# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, lsl #5
22112211
# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, lsr #5
22122212
# CHECK-NEXT: - - - - 1.00 - - - rscne r4, r4, r5, lsr #5
22132213
# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, asr #5
22142214
# CHECK-NEXT: - - - - 1.00 - - - rsc r4, r4, r5, ror #5
2215-
# CHECK-NEXT: - - - - 1.00 - - - rscgt r6, r6, r7, lsl r9
2215+
# CHECK-NEXT: - 0.50 0.50 - - - - - rscgt r6, r6, r7, lsl r9
22162216
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, lsr r9
22172217
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, asr r9
22182218
# CHECK-NEXT: - - - - 1.00 - - - rsc r6, r6, r7, ror r9

‎llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp

+7-4
Original file line numberDiff line numberDiff line change
@@ -217,12 +217,14 @@ ResolvedSchedClass::ResolvedSchedClass(const MCSubtargetInfo &STI,
217217
}
218218

219219
static unsigned ResolveVariantSchedClassId(const MCSubtargetInfo &STI,
220+
const MCInstrInfo &InstrInfo,
220221
unsigned SchedClassId,
221222
const MCInst &MCI) {
222223
const auto &SM = STI.getSchedModel();
223-
while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant())
224-
SchedClassId =
225-
STI.resolveVariantSchedClass(SchedClassId, &MCI, SM.getProcessorID());
224+
while (SchedClassId && SM.getSchedClassDesc(SchedClassId)->isVariant()) {
225+
SchedClassId = STI.resolveVariantSchedClass(SchedClassId, &MCI, &InstrInfo,
226+
SM.getProcessorID());
227+
}
226228
return SchedClassId;
227229
}
228230

@@ -234,7 +236,8 @@ ResolvedSchedClass::resolveSchedClassId(const MCSubtargetInfo &SubtargetInfo,
234236
const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel()
235237
.getSchedClassDesc(SchedClassId)
236238
->isVariant();
237-
SchedClassId = ResolveVariantSchedClassId(SubtargetInfo, SchedClassId, MCI);
239+
SchedClassId =
240+
ResolveVariantSchedClassId(SubtargetInfo, InstrInfo, SchedClassId, MCI);
238241
return std::make_pair(SchedClassId, WasVariant);
239242
}
240243

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