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[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Summary: This patch simply adds support for the new CPU in anticipation of Power10. There isn't really any functionality added so there are no associated test cases at this time. Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc Reviewed By: stefanp, nemanjai, amyk, #powerpc Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz, cfe-commits, kbarton, echristo Tags: #clang, #powerpc, #llvm Differential Revision: https://reviews.llvm.org/D80020
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12 files changed

+148
-78
lines changed

12 files changed

+148
-78
lines changed

‎clang/lib/Basic/Targets/PPC.cpp

+26-15
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
151151
Builder.defineMacro("_ARCH_PWR8");
152152
if (ArchDefs & ArchDefinePwr9)
153153
Builder.defineMacro("_ARCH_PWR9");
154+
if (ArchDefs & ArchDefinePwr10)
155+
Builder.defineMacro("_ARCH_PWR10");
154156
if (ArchDefs & ArchDefineA2)
155157
Builder.defineMacro("_ARCH_A2");
156158
if (ArchDefs & ArchDefineA2q) {
@@ -263,41 +265,51 @@ bool PPCTargetInfo::initFeatureMap(
263265
.Case("pwr7", true)
264266
.Case("pwr8", true)
265267
.Case("pwr9", true)
268+
.Case("pwr10", true)
266269
.Case("ppc64", true)
267270
.Case("ppc64le", true)
268271
.Default(false);
269272

270273
Features["qpx"] = (CPU == "a2q");
271-
Features["power9-vector"] = (CPU == "pwr9");
274+
Features["power9-vector"] = llvm::StringSwitch<bool>(CPU)
275+
.Case("pwr10", true)
276+
.Case("pwr9", true)
277+
.Default(false);
272278
Features["crypto"] = llvm::StringSwitch<bool>(CPU)
273279
.Case("ppc64le", true)
280+
.Case("pwr10", true)
274281
.Case("pwr9", true)
275282
.Case("pwr8", true)
276283
.Default(false);
277284
Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
278285
.Case("ppc64le", true)
286+
.Case("pwr10", true)
279287
.Case("pwr9", true)
280288
.Case("pwr8", true)
281289
.Default(false);
282290
Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
283291
.Case("ppc64le", true)
292+
.Case("pwr10", true)
284293
.Case("pwr9", true)
285294
.Case("pwr8", true)
286295
.Case("pwr7", true)
287296
.Default(false);
288297
Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
289298
.Case("ppc64le", true)
299+
.Case("pwr10", true)
290300
.Case("pwr9", true)
291301
.Case("pwr8", true)
292302
.Case("pwr7", true)
293303
.Default(false);
294304
Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
295305
.Case("ppc64le", true)
306+
.Case("pwr10", true)
296307
.Case("pwr9", true)
297308
.Case("pwr8", true)
298309
.Default(false);
299310
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
300311
.Case("ppc64le", true)
312+
.Case("pwr10", true)
301313
.Case("pwr9", true)
302314
.Case("pwr8", true)
303315
.Case("pwr7", true)
@@ -313,10 +325,10 @@ bool PPCTargetInfo::initFeatureMap(
313325
.Case("e500", true)
314326
.Default(false);
315327

316-
// Future CPU should include all of the features of Power 9 as well as any
328+
// Future CPU should include all of the features of Power 10 as well as any
317329
// additional features (yet to be determined) specific to it.
318330
if (CPU == "future") {
319-
initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
331+
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
320332
addFutureSpecificFeatures(Features);
321333
}
322334

@@ -463,18 +475,17 @@ ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
463475
}
464476

465477
static constexpr llvm::StringLiteral ValidCPUNames[] = {
466-
{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
467-
{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
468-
{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
469-
{"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
470-
{"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"},
471-
{"e5500"}, {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"},
472-
{"power5"}, {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
473-
{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
474-
{"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"powerpc"},
475-
{"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"},
476-
{"future"}
477-
};
478+
{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
479+
{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
480+
{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
481+
{"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
482+
{"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"},
483+
{"e5500"}, {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"},
484+
{"power5"}, {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
485+
{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
486+
{"power8"}, {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"},
487+
{"pwr10"}, {"powerpc"}, {"ppc"}, {"powerpc64"}, {"ppc64"},
488+
{"powerpc64le"}, {"ppc64le"}, {"future"}};
478489

479490
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
480491
return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);

‎clang/lib/Basic/Targets/PPC.h

+24-19
Original file line numberDiff line numberDiff line change
@@ -43,13 +43,13 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
4343
ArchDefinePwr7 = 1 << 11,
4444
ArchDefinePwr8 = 1 << 12,
4545
ArchDefinePwr9 = 1 << 13,
46-
ArchDefineFuture = 1 << 14,
47-
ArchDefineA2 = 1 << 15,
48-
ArchDefineA2q = 1 << 16,
49-
ArchDefineE500 = 1 << 17
46+
ArchDefinePwr10 = 1 << 14,
47+
ArchDefineFuture = 1 << 15,
48+
ArchDefineA2 = 1 << 16,
49+
ArchDefineA2q = 1 << 17,
50+
ArchDefineE500 = 1 << 18
5051
} ArchDefineTypes;
5152

52-
5353
ArchDefineTypes ArchDefs = ArchDefineNone;
5454
static const Builtin::Info BuiltinInfo[];
5555
static const char *const GCCRegNames[];
@@ -119,20 +119,20 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
119119
.Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
120120
.Cases("power3", "pwr3", ArchDefinePpcgr)
121121
.Cases("power4", "pwr4",
122-
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
122+
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
123123
.Cases("power5", "pwr5",
124-
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
125-
ArchDefinePpcsq)
124+
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
125+
ArchDefinePpcsq)
126126
.Cases("power5x", "pwr5x",
127-
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
128-
ArchDefinePpcgr | ArchDefinePpcsq)
127+
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
128+
ArchDefinePpcgr | ArchDefinePpcsq)
129129
.Cases("power6", "pwr6",
130-
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
131-
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
130+
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
131+
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
132132
.Cases("power6x", "pwr6x",
133-
ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
134-
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
135-
ArchDefinePpcsq)
133+
ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
134+
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
135+
ArchDefinePpcsq)
136136
.Cases("power7", "pwr7",
137137
ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
138138
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
@@ -146,11 +146,16 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
146146
ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
147147
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
148148
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
149+
.Cases("power10", "pwr10",
150+
ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
151+
ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
152+
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
153+
ArchDefinePpcsq)
149154
.Case("future",
150-
ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
151-
ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
152-
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
153-
ArchDefinePpcsq)
155+
ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
156+
ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
157+
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
158+
ArchDefinePpcgr | ArchDefinePpcsq)
154159
.Cases("8548", "e500", ArchDefineE500)
155160
.Default(ArchDefineNone);
156161
}

‎clang/lib/Driver/ToolChains/Arch/PPC.cpp

+12-8
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ std::string ppc::getPPCTargetCPU(const ArgList &Args) {
7070
.Case("power7", "pwr7")
7171
.Case("power8", "pwr8")
7272
.Case("power9", "pwr9")
73+
.Case("power10", "pwr10")
7374
.Case("future", "future")
7475
.Case("pwr3", "pwr3")
7576
.Case("pwr4", "pwr4")
@@ -80,6 +81,7 @@ std::string ppc::getPPCTargetCPU(const ArgList &Args) {
8081
.Case("pwr7", "pwr7")
8182
.Case("pwr8", "pwr8")
8283
.Case("pwr9", "pwr9")
84+
.Case("pwr10", "pwr10")
8385
.Case("powerpc", "ppc")
8486
.Case("powerpc64", "ppc64")
8587
.Case("powerpc64le", "ppc64le")
@@ -91,14 +93,16 @@ std::string ppc::getPPCTargetCPU(const ArgList &Args) {
9193

9294
const char *ppc::getPPCAsmModeForCPU(StringRef Name) {
9395
return llvm::StringSwitch<const char *>(Name)
94-
.Case("pwr7", "-mpower7")
95-
.Case("power7", "-mpower7")
96-
.Case("pwr8", "-mpower8")
97-
.Case("power8", "-mpower8")
98-
.Case("ppc64le", "-mpower8")
99-
.Case("pwr9", "-mpower9")
100-
.Case("power9", "-mpower9")
101-
.Default("-many");
96+
.Case("pwr7", "-mpower7")
97+
.Case("power7", "-mpower7")
98+
.Case("pwr8", "-mpower8")
99+
.Case("power8", "-mpower8")
100+
.Case("ppc64le", "-mpower8")
101+
.Case("pwr9", "-mpower9")
102+
.Case("power9", "-mpower9")
103+
.Case("pwr10", "-mpower10")
104+
.Case("power10", "-mpower10")
105+
.Default("-many");
102106
}
103107

104108
void ppc::getPPCTargetFeatures(const Driver &D, const llvm::Triple &Triple,

‎clang/test/Misc/target-invalid-cpu-note.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@
8181
// PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750,
8282
// PPC-SAME: 8548, 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4,
8383
// PPC-SAME: pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x,
84-
// PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64,
84+
// PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, power10, pwr10, powerpc, ppc, powerpc64,
8585
// PPC-SAME: ppc64, powerpc64le, ppc64le, future
8686

8787
// RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS

‎clang/test/Preprocessor/init-ppc64.c

+18
Original file line numberDiff line numberDiff line change
@@ -627,12 +627,30 @@
627627
// PPCPOWER9:#define _ARCH_PWR7 1
628628
// PPCPOWER9:#define _ARCH_PWR9 1
629629
//
630+
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
631+
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER10 %s
632+
//
633+
// PPCPOWER10:#define _ARCH_PPC 1
634+
// PPCPOWER10:#define _ARCH_PPC64 1
635+
// PPCPOWER10:#define _ARCH_PPCGR 1
636+
// PPCPOWER10:#define _ARCH_PPCSQ 1
637+
// PPCPOWER10:#define _ARCH_PWR10 1
638+
// PPCPOWER10:#define _ARCH_PWR4 1
639+
// PPCPOWER10:#define _ARCH_PWR5 1
640+
// PPCPOWER10:#define _ARCH_PWR5X 1
641+
// PPCPOWER10:#define _ARCH_PWR6 1
642+
// PPCPOWER10-NOT:#define _ARCH_PWR6X 1
643+
// PPCPOWER10:#define _ARCH_PWR7 1
644+
// PPCPOWER10:#define _ARCH_PWR8 1
645+
// PPCPOWER10:#define _ARCH_PWR9 1
646+
//
630647
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
631648
//
632649
// PPCFUTURE:#define _ARCH_PPC 1
633650
// PPCFUTURE:#define _ARCH_PPC64 1
634651
// PPCFUTURE:#define _ARCH_PPCGR 1
635652
// PPCFUTURE:#define _ARCH_PPCSQ 1
653+
// PPCFUTURE:#define _ARCH_PWR10 1
636654
// PPCFUTURE:#define _ARCH_PWR4 1
637655
// PPCFUTURE:#define _ARCH_PWR5 1
638656
// PPCFUTURE:#define _ARCH_PWR5X 1

‎llvm/lib/Support/Host.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
142142
.Case("POWER8E", "pwr8")
143143
.Case("POWER8NVL", "pwr8")
144144
.Case("POWER9", "pwr9")
145+
.Case("POWER10", "pwr10")
145146
// FIXME: If we get a simulator or machine with the capabilities of
146147
// mcpu=future, we should revisit this and add the name reported by the
147148
// simulator/machine.

‎llvm/lib/Target/PowerPC/PPC.td

+22-5
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ def DirectivePwr6x
5151
def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
5252
def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
5353
def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
54+
def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
5455
def DirectivePwrFuture
5556
: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
5657

@@ -205,6 +206,9 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
205206
def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
206207
"true",
207208
"Enable instructions added in ISA 3.0.">;
209+
def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
210+
"true",
211+
"Enable instructions added in ISA 3.1.">;
208212
def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
209213
"Enable POWER9 Altivec instructions",
210214
[FeatureISA3_0, FeatureP8Altivec]>;
@@ -328,14 +332,25 @@ def ProcessorFeatures {
328332
list<SubtargetFeature> P9Features =
329333
!listconcat(P9InheritableFeatures, P9SpecificFeatures);
330334

335+
// Power10
336+
// For P10 CPU we assume that all of the existing features from Power9
337+
// still exist with the exception of those we know are Power9 specific.
338+
list<SubtargetFeature> P10AdditionalFeatures =
339+
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
340+
FeaturePCRelativeMemops];
341+
list<SubtargetFeature> P10SpecificFeatures = [];
342+
list<SubtargetFeature> P10InheritableFeatures =
343+
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
344+
list<SubtargetFeature> P10Features =
345+
!listconcat(P10InheritableFeatures, P10SpecificFeatures);
346+
331347
// Future
332-
// For future CPU we assume that all of the existing features from Power 9
333-
// still exist with the exception of those we know are Power 9 specific.
348+
// For future CPU we assume that all of the existing features from Power10
349+
// still exist with the exception of those we know are Power10 specific.
334350
list<SubtargetFeature> FutureAdditionalFeatures = [];
335-
list<SubtargetFeature> FutureSpecificFeatures =
336-
[FeaturePrefixInstrs, FeaturePCRelativeMemops];
351+
list<SubtargetFeature> FutureSpecificFeatures = [];
337352
list<SubtargetFeature> FutureInheritableFeatures =
338-
!listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
353+
!listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
339354
list<SubtargetFeature> FutureFeatures =
340355
!listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
341356
}
@@ -540,6 +555,8 @@ def : ProcessorModel<"pwr6x", G5Model,
540555
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
541556
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
542557
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
558+
// No scheduler model yet.
559+
def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>;
543560
// No scheduler model for future CPU.
544561
def : ProcessorModel<"future", NoSchedModel,
545562
ProcessorFeatures.FutureFeatures>;

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -1306,6 +1306,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
13061306
case PPC::DIR_PWR7:
13071307
case PPC::DIR_PWR8:
13081308
case PPC::DIR_PWR9:
1309+
case PPC::DIR_PWR10:
13091310
case PPC::DIR_PWR_FUTURE:
13101311
setPrefLoopAlignment(Align(16));
13111312
setPrefFunctionAlignment(Align(16));
@@ -14913,6 +14914,7 @@ Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
1491314914
case PPC::DIR_PWR7:
1491414915
case PPC::DIR_PWR8:
1491514916
case PPC::DIR_PWR9:
14917+
case PPC::DIR_PWR10:
1491614918
case PPC::DIR_PWR_FUTURE: {
1491714919
if (!ML)
1491814920
break;
@@ -16103,6 +16105,7 @@ SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {
1610316105
// vector 7 2 2
1610416106
return true;
1610516107
case PPC::DIR_PWR9:
16108+
case PPC::DIR_PWR10:
1610616109
case PPC::DIR_PWR_FUTURE:
1610716110
// type mul add shl
1610816111
// scalar 5 2 2

‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ void PPCSubtarget::initializeEnvironment() {
115115
HasAddiLoadFusion = false;
116116
HasAddisLoadFusion = false;
117117
IsISA3_0 = false;
118+
IsISA3_1 = false;
118119
UseLongCalls = false;
119120
SecurePlt = false;
120121
VectorsUseTwoUnits = false;

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