Apply clang-tidy fixes for readability-container-size-empty for MLIR (NFC)

Reviewed By: rriddle, Mogball

Differential Revision: https://reviews.llvm.org/D116252

Author: joker-eph

mlir/lib/Analysis/Utils.cpp

@@ -151,7 +151,7 @@ void ComputationSliceState::dump() const {
 /// if both the src and the dst loops don't have the same bounds. Returns
 /// llvm::None if none of the above can be proven.
 Optional<bool> ComputationSliceState::isSliceMaximalFastCheck() const {
-  assert(lbs.size() == ubs.size() && lbs.size() && ivs.size() &&
+  assert(lbs.size() == ubs.size() && !lbs.empty() && !ivs.empty() &&
          "Unexpected number of lbs, ubs and ivs in slice");
 
   for (unsigned i = 0, end = lbs.size(); i < end; ++i) {

mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp

@@ -105,7 +105,7 @@ static void printOperandAndTypeList(OpAsmPrinter &p, OperandRange operands) {
 /// Print data variables corresponding to a data-sharing clause `name`
 static void printDataVars(OpAsmPrinter &p, OperandRange operands,
                           StringRef name) {
-  if (operands.size()) {
+  if (!operands.empty()) {
     p << name;
     printOperandAndTypeList(p, operands);
   }
@@ -390,7 +390,7 @@ static void printReductionVarList(OpAsmPrinter &p,
 static LogicalResult verifyReductionVarList(Operation *op,
                                             Optional<ArrayAttr> reductions,
                                             OperandRange reductionVars) {
-  if (reductionVars.size() != 0) {
+  if (!reductionVars.empty()) {
     if (!reductions || reductions->size() != reductionVars.size())
       return op->emitOpError()
              << "expected as many reduction symbol references "
@@ -863,7 +863,7 @@ static ParseResult parseClauses(OpAsmParser &parser, OperationState &result,
     schedule[0] = llvm::toUpper(schedule[0]);
     auto attr = parser.getBuilder().getStringAttr(schedule);
     result.addAttribute("schedule_val", attr);
-    if (modifiers.size() > 0) {
+    if (!modifiers.empty()) {
       auto mod = parser.getBuilder().getStringAttr(modifiers[0]);
       result.addAttribute("schedule_modifier", mod);
       // Only SIMD attribute is allowed here!
@@ -1072,7 +1072,7 @@ static void printWsLoopOp(OpAsmPrinter &p, WsLoopOp op) {
   printDataVars(p, op.firstprivate_vars(), "firstprivate");
   printDataVars(p, op.lastprivate_vars(), "lastprivate");
 
-  if (op.linear_vars().size())
+  if (!op.linear_vars().empty())
     printLinearClause(p, op.linear_vars(), op.linear_step_vars());
 
   if (auto sched = op.schedule_val())

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

@@ -669,7 +669,7 @@ getElementType(Type type, Attribute indices,
     emitErrorFn("expected a 32-bit integer array attribute for 'indices'");
     return nullptr;
   }
-  if (!indicesArrayAttr.size()) {
+  if (indicesArrayAttr.empty()) {
     emitErrorFn("expected at least one index for spv.CompositeExtract");
     return nullptr;
   }
@@ -1929,7 +1929,7 @@ static void print(spirv::ExecutionModeOp execModeOp, OpAsmPrinter &printer) {
   printer << " \"" << stringifyExecutionMode(execModeOp.execution_mode())
           << "\"";
   auto values = execModeOp.values();
-  if (!values.size())
+  if (values.empty())
     return;
   printer << ", ";
   llvm::interleaveComma(values, printer, [&](Attribute a) {

mlir/lib/Dialect/SparseTensor/Utils/Merger.cpp

@@ -137,7 +137,7 @@ unsigned Merger::mapSet(Kind kind, unsigned s0, Value v) {
 
 unsigned Merger::optimizeSet(unsigned s0) {
   unsigned s = addSet();
-  assert(latSets[s0].size() != 0);
+  assert(!latSets[s0].empty());
   unsigned p0 = latSets[s0][0];
   for (unsigned p1 : latSets[s0]) {
     bool add = true;

mlir/lib/Dialect/Vector/VectorMultiDimReductionTransforms.cpp

@@ -141,12 +141,12 @@ class ReduceMultiDimReductionRank
     // 2. Compute flattened parallel and reduction sizes.
     int flattenedParallelDim = 0;
     int flattenedReductionDim = 0;
-    if (parallelShapes.size() > 0) {
+    if (!parallelShapes.empty()) {
       flattenedParallelDim = 1;
       for (auto d : parallelShapes)
         flattenedParallelDim *= d;
     }
-    if (reductionShapes.size() > 0) {
+    if (!reductionShapes.empty()) {
       flattenedReductionDim = 1;
       for (auto d : reductionShapes)
         flattenedReductionDim *= d;

mlir/lib/Dialect/Vector/VectorOps.cpp

@@ -340,13 +340,13 @@ static ParseResult parseReductionOp(OpAsmParser &parser,
       parser.parseComma() || parser.parseOperandList(operandsInfo) ||
       parser.parseColonType(redType) ||
       parser.parseKeywordType("into", resType) ||
-      (operandsInfo.size() > 0 &&
+      (!operandsInfo.empty() &&
        parser.resolveOperand(operandsInfo[0], redType, result.operands)) ||
       (operandsInfo.size() > 1 &&
        parser.resolveOperand(operandsInfo[1], resType, result.operands)) ||
       parser.addTypeToList(resType, result.types))
     return failure();
-  if (operandsInfo.size() < 1 || operandsInfo.size() > 2)
+  if (operandsInfo.empty() || operandsInfo.size() > 2)
     return parser.emitError(parser.getNameLoc(),
                             "unsupported number of operands");
   return success();
@@ -546,7 +546,7 @@ static LogicalResult verifyOutputShape(
   }
 
   // Verify 'expectedResultDims'.
-  if (expectedResultDims.size() == 0) {
+  if (expectedResultDims.empty()) {
     // No batch or free dimension implies a scalar result.
     if (resType.isa<VectorType>() || accType.isa<VectorType>())
       return op.emitOpError("invalid accumulator/result vector shape");

mlir/lib/Reducer/ReductionNode.cpp

@@ -61,7 +61,7 @@ ArrayRef<ReductionNode *> ReductionNode::generateNewVariants() {
   // If we haven't created new variant, then we can create varients by removing
   // each of them respectively. For example, given {{1, 3}, {4, 9}}, we can
   // produce variants with range {{1, 3}} and {{4, 9}}.
-  if (variants.size() == 0 && getRanges().size() > 1) {
+  if (variants.empty() && getRanges().size() > 1) {
     for (const Range &range : getRanges()) {
       std::vector<Range> subRanges = getRanges();
       llvm::erase_value(subRanges, range);

mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp

@@ -591,7 +591,7 @@ convertOmpSections(Operation &opInst, llvm::IRBuilderBase &builder,
   // No sections within omp.sections operation - skip generation. This situation
   // is only possible if there is only a terminator operation inside the
   // sections operation
-  if (sectionCBs.size() == 0)
+  if (sectionCBs.empty())
     return success();
 
   assert(isa<omp::SectionOp>(*sectionsOp.region().op_begin()));

mlir/test/lib/Dialect/Affine/TestAffineDataCopy.cpp

@@ -59,7 +59,7 @@ void TestAffineDataCopy::runOnFunction() {
   // Gather all AffineForOps by loop depth.
   std::vector<SmallVector<AffineForOp, 2>> depthToLoops;
   gatherLoops(getFunction(), depthToLoops);
-  assert(depthToLoops.size() && "Loop nest not found");
+  assert(!depthToLoops.empty() && "Loop nest not found");
 
   // Only support tests with a single loop nest and a single innermost loop
   // for now.

mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp

@@ -42,18 +42,18 @@ using llvm::RecordKeeper;
 static bool emitDecls(const RecordKeeper &recordKeeper, raw_ostream &os) {
   const auto &directiveLanguages =
       recordKeeper.getAllDerivedDefinitions("DirectiveLanguage");
-  assert(directiveLanguages.size() != 0 && "DirectiveLanguage missing.");
+  assert(!directiveLanguages.empty() && "DirectiveLanguage missing.");
 
   const auto &clauses = recordKeeper.getAllDerivedDefinitions("Clause");
 
   for (const auto &r : clauses) {
     Clause c{r};
     const auto &clauseVals = c.getClauseVals();
-    if (clauseVals.size() <= 0)
+    if (clauseVals.empty())
       continue;
 
     const auto enumName = c.getEnumName();
-    assert(enumName.size() != 0 && "enumClauseValue field not set.");
+    assert(!enumName.empty() && "enumClauseValue field not set.");
 
     std::vector<std::string> cvDefs;
     for (const auto &cv : clauseVals) {