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[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs
Most Intel CPU scheduler files lumped the immediate and 1 instructions together, but uops.info shows they are quite different. For the most part the by 1 instructions were pretty accurate to the uops.info data except the latency was 3 instead of 2 as uops.info indicates. The by immediate instructions need 7 or 8 uops and have higher latency. It looks like the 8-bit by immediate instructions may need even more uops, but I just lumped them with the 16/32/64. Noticed while checking out PR53648. So mostly I cared about the by 1 instructions. Reviewed By: RKSimon, pengfei Differential Revision: https://reviews.llvm.org/D119217
1 parent c151225 commit 56d6ccd

14 files changed

+329
-245
lines changed

‎llvm/lib/Target/X86/X86SchedBroadwell.td

+17-3
Original file line numberDiff line numberDiff line change
@@ -814,12 +814,26 @@ def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
814814
def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
815815

816816
def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
817-
let Latency = 3;
817+
let Latency = 2;
818818
let NumMicroOps = 3;
819819
let ResourceCycles = [1,2];
820820
}
821-
def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
822-
"RCR(8|16|32|64)r(1|i)")>;
821+
def: InstRW<[BWWriteResGroup35], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
822+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
823+
824+
def BWWriteResGroup36 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
825+
let Latency = 5;
826+
let NumMicroOps = 8;
827+
let ResourceCycles = [2,4,2];
828+
}
829+
def: InstRW<[BWWriteResGroup36], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
830+
831+
def BWWriteResGroup36b : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
832+
let Latency = 6;
833+
let NumMicroOps = 8;
834+
let ResourceCycles = [2,4,2];
835+
}
836+
def: InstRW<[BWWriteResGroup36b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
823837

824838
def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
825839
let Latency = 3;

‎llvm/lib/Target/X86/X86SchedHaswell.td

+17-3
Original file line numberDiff line numberDiff line change
@@ -1299,12 +1299,26 @@ def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
12991299
def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
13001300

13011301
def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
1302-
let Latency = 3;
1302+
let Latency = 2;
13031303
let NumMicroOps = 3;
13041304
let ResourceCycles = [1,2];
13051305
}
1306-
def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)",
1307-
"RCR(8|16|32|64)r(1|i)")>;
1306+
def: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
1307+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
1308+
1309+
def HWWriteResGroup60 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1310+
let Latency = 5;
1311+
let NumMicroOps = 8;
1312+
let ResourceCycles = [2,4,2];
1313+
}
1314+
def: InstRW<[HWWriteResGroup60], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
1315+
1316+
def HWWriteResGroup60b : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> {
1317+
let Latency = 6;
1318+
let NumMicroOps = 8;
1319+
let ResourceCycles = [2,4,2];
1320+
}
1321+
def: InstRW<[HWWriteResGroup60b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
13081322

13091323
def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
13101324
let Latency = 4;

‎llvm/lib/Target/X86/X86SchedIceLake.td

+17-3
Original file line numberDiff line numberDiff line change
@@ -923,12 +923,26 @@ def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> {
923923
def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
924924

925925
def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> {
926-
let Latency = 3;
926+
let Latency = 2;
927927
let NumMicroOps = 3;
928928
let ResourceCycles = [1,2];
929929
}
930-
def: InstRW<[ICXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
931-
"RCR(8|16|32|64)r(1|i)")>;
930+
def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
931+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
932+
933+
def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
934+
let Latency = 5;
935+
let NumMicroOps = 7;
936+
let ResourceCycles = [2,3,2];
937+
}
938+
def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
939+
940+
def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> {
941+
let Latency = 6;
942+
let NumMicroOps = 7;
943+
let ResourceCycles = [2,3,2];
944+
}
945+
def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
932946

933947
def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> {
934948
let Latency = 3;

‎llvm/lib/Target/X86/X86SchedSandyBridge.td

+20-6
Original file line numberDiff line numberDiff line change
@@ -678,13 +678,27 @@ def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
678678
}
679679
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
680680

681-
def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> {
681+
def SBWriteResGroup23 : SchedWriteRes<[SBPort05,SBPort015]> {
682682
let Latency = 2;
683683
let NumMicroOps = 3;
684-
let ResourceCycles = [3];
684+
let ResourceCycles = [2,1];
685+
}
686+
def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
687+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
688+
689+
def SBWriteResGroup24 : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
690+
let Latency = 3;
691+
let NumMicroOps = 8;
692+
let ResourceCycles = [1,1,4,2];
693+
}
694+
def: InstRW<[SBWriteResGroup24], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
695+
696+
def SBWriteResGroup24b : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
697+
let Latency = 4;
698+
let NumMicroOps = 8;
699+
let ResourceCycles = [1,1,4,2];
685700
}
686-
def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1",
687-
"RCR(8|16|32|64)r1")>;
701+
def: InstRW<[SBWriteResGroup24b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
688702

689703
def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
690704
let Latency = 7;
@@ -727,8 +741,8 @@ def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> {
727741
let NumMicroOps = 8;
728742
let ResourceCycles = [8];
729743
}
730-
def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)",
731-
"RCR(8|16|32|64)r(i|CL)")>;
744+
def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
745+
"RCR(8|16|32|64)rCL")>;
732746

733747
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
734748
let Latency = 5;

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

+17-3
Original file line numberDiff line numberDiff line change
@@ -836,12 +836,26 @@ def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
836836
def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
837837

838838
def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
839-
let Latency = 3;
839+
let Latency = 2;
840840
let NumMicroOps = 3;
841841
let ResourceCycles = [1,2];
842842
}
843-
def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)",
844-
"RCR(8|16|32|64)r(1|i)")>;
843+
def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
844+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
845+
846+
def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
847+
let Latency = 5;
848+
let NumMicroOps = 8;
849+
let ResourceCycles = [2,4,2];
850+
}
851+
def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
852+
853+
def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
854+
let Latency = 6;
855+
let NumMicroOps = 8;
856+
let ResourceCycles = [2,4,2];
857+
}
858+
def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
845859

846860
def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
847861
let Latency = 3;

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

+17-3
Original file line numberDiff line numberDiff line change
@@ -905,12 +905,26 @@ def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
905905
def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
906906

907907
def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
908-
let Latency = 3;
908+
let Latency = 2;
909909
let NumMicroOps = 3;
910910
let ResourceCycles = [1,2];
911911
}
912-
def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
913-
"RCR(8|16|32|64)r(1|i)")>;
912+
def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
913+
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
914+
915+
def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
916+
let Latency = 5;
917+
let NumMicroOps = 8;
918+
let ResourceCycles = [2,4,2];
919+
}
920+
def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
921+
922+
def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
923+
let Latency = 6;
924+
let NumMicroOps = 8;
925+
let ResourceCycles = [2,4,2];
926+
}
927+
def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
914928

915929
def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
916930
let Latency = 3;

‎llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s

+33-33
Original file line numberDiff line numberDiff line change
@@ -1506,48 +1506,48 @@ xorq (%rax), %rdi
15061506
# CHECK-NEXT: 1 100 0.33 U outsw (%rsi), %dx
15071507
# CHECK-NEXT: 1 100 0.33 U outsl (%rsi), %dx
15081508
# CHECK-NEXT: 4 4 1.33 * * U pause
1509-
# CHECK-NEXT: 3 2 1.50 rclb %dil
1510-
# CHECK-NEXT: 3 2 1.50 rcrb %dil
1509+
# CHECK-NEXT: 3 2 1.00 rclb %dil
1510+
# CHECK-NEXT: 3 2 1.00 rcrb %dil
15111511
# CHECK-NEXT: 11 11 3.50 * rclb (%rax)
15121512
# CHECK-NEXT: 11 11 3.50 * rcrb (%rax)
1513-
# CHECK-NEXT: 8 5 4.00 rclb $7, %dil
1514-
# CHECK-NEXT: 8 5 4.00 rcrb $7, %dil
1513+
# CHECK-NEXT: 8 4 2.67 rclb $7, %dil
1514+
# CHECK-NEXT: 8 3 2.67 rcrb $7, %dil
15151515
# CHECK-NEXT: 11 11 3.50 * rclb $7, (%rax)
15161516
# CHECK-NEXT: 11 11 3.50 * rcrb $7, (%rax)
15171517
# CHECK-NEXT: 8 5 4.00 rclb %cl, %dil
15181518
# CHECK-NEXT: 8 5 4.00 rcrb %cl, %dil
15191519
# CHECK-NEXT: 11 11 3.50 * rclb %cl, (%rax)
15201520
# CHECK-NEXT: 11 11 3.50 * rcrb %cl, (%rax)
1521-
# CHECK-NEXT: 3 2 1.50 rclw %di
1522-
# CHECK-NEXT: 3 2 1.50 rcrw %di
1521+
# CHECK-NEXT: 3 2 1.00 rclw %di
1522+
# CHECK-NEXT: 3 2 1.00 rcrw %di
15231523
# CHECK-NEXT: 11 11 3.50 * rclw (%rax)
15241524
# CHECK-NEXT: 11 11 3.50 * rcrw (%rax)
1525-
# CHECK-NEXT: 8 5 4.00 rclw $7, %di
1526-
# CHECK-NEXT: 8 5 4.00 rcrw $7, %di
1525+
# CHECK-NEXT: 8 4 2.67 rclw $7, %di
1526+
# CHECK-NEXT: 8 3 2.67 rcrw $7, %di
15271527
# CHECK-NEXT: 11 11 3.50 * rclw $7, (%rax)
15281528
# CHECK-NEXT: 11 11 3.50 * rcrw $7, (%rax)
15291529
# CHECK-NEXT: 8 5 4.00 rclw %cl, %di
15301530
# CHECK-NEXT: 8 5 4.00 rcrw %cl, %di
15311531
# CHECK-NEXT: 11 11 3.50 * rclw %cl, (%rax)
15321532
# CHECK-NEXT: 11 11 3.50 * rcrw %cl, (%rax)
1533-
# CHECK-NEXT: 3 2 1.50 rcll %edi
1534-
# CHECK-NEXT: 3 2 1.50 rcrl %edi
1533+
# CHECK-NEXT: 3 2 1.00 rcll %edi
1534+
# CHECK-NEXT: 3 2 1.00 rcrl %edi
15351535
# CHECK-NEXT: 11 11 3.50 * rcll (%rax)
15361536
# CHECK-NEXT: 11 11 3.50 * rcrl (%rax)
1537-
# CHECK-NEXT: 8 5 4.00 rcll $7, %edi
1538-
# CHECK-NEXT: 8 5 4.00 rcrl $7, %edi
1537+
# CHECK-NEXT: 8 4 2.67 rcll $7, %edi
1538+
# CHECK-NEXT: 8 3 2.67 rcrl $7, %edi
15391539
# CHECK-NEXT: 11 11 3.50 * rcll $7, (%rax)
15401540
# CHECK-NEXT: 11 11 3.50 * rcrl $7, (%rax)
15411541
# CHECK-NEXT: 8 5 4.00 rcll %cl, %edi
15421542
# CHECK-NEXT: 8 5 4.00 rcrl %cl, %edi
15431543
# CHECK-NEXT: 11 11 3.50 * rcll %cl, (%rax)
15441544
# CHECK-NEXT: 11 11 3.50 * rcrl %cl, (%rax)
1545-
# CHECK-NEXT: 3 2 1.50 rclq %rdi
1546-
# CHECK-NEXT: 3 2 1.50 rcrq %rdi
1545+
# CHECK-NEXT: 3 2 1.00 rclq %rdi
1546+
# CHECK-NEXT: 3 2 1.00 rcrq %rdi
15471547
# CHECK-NEXT: 11 11 3.50 * rclq (%rax)
15481548
# CHECK-NEXT: 11 11 3.50 * rcrq (%rax)
1549-
# CHECK-NEXT: 8 5 4.00 rclq $7, %rdi
1550-
# CHECK-NEXT: 8 5 4.00 rcrq $7, %rdi
1549+
# CHECK-NEXT: 8 4 2.67 rclq $7, %rdi
1550+
# CHECK-NEXT: 8 3 2.67 rcrq $7, %rdi
15511551
# CHECK-NEXT: 11 11 3.50 * rclq $7, (%rax)
15521552
# CHECK-NEXT: 11 11 3.50 * rcrq $7, (%rax)
15531553
# CHECK-NEXT: 8 5 4.00 rclq %cl, %rdi
@@ -1953,7 +1953,7 @@ xorq (%rax), %rdi
19531953

19541954
# CHECK: Resource pressure per iteration:
19551955
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
1956-
# CHECK-NEXT: 160.00 - 670.17 294.67 361.00 687.17 455.50 455.50
1956+
# CHECK-NEXT: 160.00 - 658.17 310.67 361.00 683.17 455.50 455.50
19571957

19581958
# CHECK: Resource pressure by instruction:
19591959
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
@@ -2433,48 +2433,48 @@ xorq (%rax), %rdi
24332433
# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsw (%rsi), %dx
24342434
# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsl (%rsi), %dx
24352435
# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - pause
2436-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rclb %dil
2437-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrb %dil
2436+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rclb %dil
2437+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rcrb %dil
24382438
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb (%rax)
24392439
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb (%rax)
2440-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb $7, %dil
2441-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb $7, %dil
2440+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rclb $7, %dil
2441+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rcrb $7, %dil
24422442
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb $7, (%rax)
24432443
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb $7, (%rax)
24442444
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb %cl, %dil
24452445
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb %cl, %dil
24462446
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb %cl, (%rax)
24472447
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb %cl, (%rax)
2448-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rclw %di
2449-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrw %di
2448+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rclw %di
2449+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rcrw %di
24502450
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw (%rax)
24512451
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw (%rax)
2452-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw $7, %di
2453-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw $7, %di
2452+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rclw $7, %di
2453+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rcrw $7, %di
24542454
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw $7, (%rax)
24552455
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw $7, (%rax)
24562456
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw %cl, %di
24572457
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw %cl, %di
24582458
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw %cl, (%rax)
24592459
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw %cl, (%rax)
2460-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rcll %edi
2461-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrl %edi
2460+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rcll %edi
2461+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rcrl %edi
24622462
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll (%rax)
24632463
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl (%rax)
2464-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll $7, %edi
2465-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl $7, %edi
2464+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rcll $7, %edi
2465+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rcrl $7, %edi
24662466
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll $7, (%rax)
24672467
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl $7, (%rax)
24682468
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll %cl, %edi
24692469
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl %cl, %edi
24702470
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll %cl, (%rax)
24712471
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl %cl, (%rax)
2472-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rclq %rdi
2473-
# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrq %rdi
2472+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rclq %rdi
2473+
# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - rcrq %rdi
24742474
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq (%rax)
24752475
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq (%rax)
2476-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq $7, %rdi
2477-
# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq $7, %rdi
2476+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rclq $7, %rdi
2477+
# CHECK-NEXT: - - 2.67 1.67 - 3.67 - - rcrq $7, %rdi
24782478
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq $7, (%rax)
24792479
# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq $7, (%rax)
24802480
# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq %cl, %rdi

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