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[X86][MMX] Remove superfluous 'i' from MMX cvt opnames. NFCI.
This is a very old copy+paste typo - none of these cvt ops have an immediate operand. Noticed while trying to merge MMX instructions into some existing SSE instruction scheduler instregex patterns.
1 parent 0a08813 commit 41052fd

12 files changed

+83
-83
lines changed

‎llvm/lib/Target/X86/X86InstrFoldTables.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -529,11 +529,11 @@ static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
529529
{ X86::LZCNT16rr, X86::LZCNT16rm, 0 },
530530
{ X86::LZCNT32rr, X86::LZCNT32rm, 0 },
531531
{ X86::LZCNT64rr, X86::LZCNT64rm, 0 },
532-
{ X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, TB_ALIGN_16 },
533-
{ X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
534-
{ X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, TB_NO_REVERSE },
535-
{ X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, TB_ALIGN_16 },
536-
{ X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, TB_NO_REVERSE },
532+
{ X86::MMX_CVTPD2PIrr, X86::MMX_CVTPD2PIrm, TB_ALIGN_16 },
533+
{ X86::MMX_CVTPI2PDrr, X86::MMX_CVTPI2PDrm, 0 },
534+
{ X86::MMX_CVTPS2PIrr, X86::MMX_CVTPS2PIrm, TB_NO_REVERSE },
535+
{ X86::MMX_CVTTPD2PIrr, X86::MMX_CVTTPD2PIrm, TB_ALIGN_16 },
536+
{ X86::MMX_CVTTPS2PIrr, X86::MMX_CVTTPS2PIrm, TB_NO_REVERSE },
537537
{ X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
538538
{ X86::MMX_PABSBrr, X86::MMX_PABSBrm, 0 },
539539
{ X86::MMX_PABSDrr, X86::MMX_PABSDrm, 0 },
@@ -1339,7 +1339,7 @@ static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
13391339
{ X86::MINSDrr_Int, X86::MINSDrm_Int, TB_NO_REVERSE },
13401340
{ X86::MINSSrr, X86::MINSSrm, 0 },
13411341
{ X86::MINSSrr_Int, X86::MINSSrm_Int, TB_NO_REVERSE },
1342-
{ X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1342+
{ X86::MMX_CVTPI2PSrr, X86::MMX_CVTPI2PSrm, 0 },
13431343
{ X86::MMX_PACKSSDWrr, X86::MMX_PACKSSDWrm, 0 },
13441344
{ X86::MMX_PACKSSWBrr, X86::MMX_PACKSSWBrm, 0 },
13451345
{ X86::MMX_PACKUSWBrr, X86::MMX_PACKUSWBrm, 0 },

‎llvm/lib/Target/X86/X86InstrMMX.td

+18-18
Original file line numberDiff line numberDiff line change
@@ -123,25 +123,25 @@ multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
123123
multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
124124
Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
125125
string asm, X86FoldableSchedWrite sched, Domain d> {
126-
def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127-
[(set DstRC:$dst, (Int SrcRC:$src))], d>,
128-
Sched<[sched]>;
129-
def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130-
[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
131-
Sched<[sched.Folded]>;
126+
def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127+
[(set DstRC:$dst, (Int SrcRC:$src))], d>,
128+
Sched<[sched]>;
129+
def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130+
[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
131+
Sched<[sched.Folded]>;
132132
}
133133

134134
multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
135135
RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
136136
PatFrag ld_frag, string asm, Domain d> {
137-
def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138-
(ins DstRC:$src1, SrcRC:$src2), asm,
139-
[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
140-
Sched<[WriteCvtI2PS]>;
141-
def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
142-
(ins DstRC:$src1, x86memop:$src2), asm,
143-
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
144-
Sched<[WriteCvtI2PS.Folded]>;
137+
def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138+
(ins DstRC:$src1, SrcRC:$src2), asm,
139+
[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
140+
Sched<[WriteCvtI2PS]>;
141+
def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
142+
(ins DstRC:$src1, x86memop:$src2), asm,
143+
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
144+
Sched<[WriteCvtI2PS.Folded]>;
145145
}
146146

147147
//===----------------------------------------------------------------------===//
@@ -569,14 +569,14 @@ def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
569569
(MMX_MOVFR642Qrr FR64:$src)>;
570570
def : Pat<(x86mmx (MMX_X86movdq2q
571571
(bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),
572-
(MMX_CVTPS2PIirr VR128:$src)>;
572+
(MMX_CVTPS2PIrr VR128:$src)>;
573573
def : Pat<(x86mmx (MMX_X86movdq2q
574574
(bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),
575-
(MMX_CVTTPS2PIirr VR128:$src)>;
575+
(MMX_CVTTPS2PIrr VR128:$src)>;
576576
def : Pat<(x86mmx (MMX_X86movdq2q
577577
(bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
578-
(MMX_CVTPD2PIirr VR128:$src)>;
578+
(MMX_CVTPD2PIrr VR128:$src)>;
579579
def : Pat<(x86mmx (MMX_X86movdq2q
580580
(bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
581-
(MMX_CVTTPD2PIirr VR128:$src)>;
581+
(MMX_CVTTPD2PIrr VR128:$src)>;
582582
}

‎llvm/lib/Target/X86/X86SchedBroadwell.td

+7-7
Original file line numberDiff line numberDiff line change
@@ -783,7 +783,7 @@ def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
783783
let NumMicroOps = 1;
784784
let ResourceCycles = [1];
785785
}
786-
def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
786+
def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSrr)>;
787787
def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
788788
"(V?)CVTDQ2PS(Y?)rr")>;
789789

@@ -862,9 +862,9 @@ def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
862862
let NumMicroOps = 2;
863863
let ResourceCycles = [1,1];
864864
}
865-
def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
866-
def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
867-
"MMX_CVT(T?)PS2PIirr",
865+
def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDrr)>;
866+
def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIrr",
867+
"MMX_CVT(T?)PS2PIrr",
868868
"(V?)CVTDQ2PDrr",
869869
"(V?)CVTPD2PSrr",
870870
"(V?)CVTSD2SSrr",
@@ -1155,7 +1155,7 @@ def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
11551155
let NumMicroOps = 2;
11561156
let ResourceCycles = [1,1];
11571157
}
1158-
def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1158+
def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSrm,
11591159
CVTDQ2PSrm,
11601160
VCVTDQ2PSrm)>;
11611161
def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
@@ -1236,8 +1236,8 @@ def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
12361236
def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
12371237
CVTPD2DQrm,
12381238
CVTTPD2DQrm,
1239-
MMX_CVTPI2PDirm)>;
1240-
def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1239+
MMX_CVTPI2PDrm)>;
1240+
def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIrm",
12411241
"(V?)CVTDQ2PDrm",
12421242
"(V?)CVTSD2SSrm")>;
12431243

‎llvm/lib/Target/X86/X86SchedHaswell.td

+10-10
Original file line numberDiff line numberDiff line change
@@ -995,7 +995,7 @@ def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
995995
let NumMicroOps = 2;
996996
let ResourceCycles = [1,1];
997997
}
998-
def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>;
998+
def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSrm)>;
999999
def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>;
10001000

10011001
def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
@@ -1240,7 +1240,7 @@ def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
12401240
let NumMicroOps = 1;
12411241
let ResourceCycles = [1];
12421242
}
1243-
def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>;
1243+
def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSrr)>;
12441244
def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr",
12451245
"(V?)CVTDQ2PS(Y?)rr")>;
12461246

@@ -1373,11 +1373,11 @@ def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
13731373
let NumMicroOps = 2;
13741374
let ResourceCycles = [1,1];
13751375
}
1376-
def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr,
1377-
MMX_CVTPD2PIirr,
1378-
MMX_CVTPS2PIirr,
1379-
MMX_CVTTPD2PIirr,
1380-
MMX_CVTTPS2PIirr)>;
1376+
def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDrr,
1377+
MMX_CVTPD2PIrr,
1378+
MMX_CVTPS2PIrr,
1379+
MMX_CVTTPD2PIrr,
1380+
MMX_CVTTPS2PIrr)>;
13811381
def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr",
13821382
"(V?)CVTPD2PSrr",
13831383
"(V?)CVTSD2SSrr",
@@ -1418,8 +1418,8 @@ def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
14181418
def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm,
14191419
CVTPD2DQrm,
14201420
CVTTPD2DQrm,
1421-
MMX_CVTPD2PIirm,
1422-
MMX_CVTTPD2PIirm,
1421+
MMX_CVTPD2PIrm,
1422+
MMX_CVTTPD2PIrm,
14231423
CVTDQ2PDrm,
14241424
VCVTDQ2PDrm)>;
14251425

@@ -1428,7 +1428,7 @@ def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
14281428
let NumMicroOps = 3;
14291429
let ResourceCycles = [1,1,1];
14301430
}
1431-
def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm,
1431+
def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDrm,
14321432
CVTSD2SSrm, CVTSD2SSrm_Int,
14331433
VCVTSD2SSrm, VCVTSD2SSrm_Int)>;
14341434

‎llvm/lib/Target/X86/X86SchedIceLake.td

+7-7
Original file line numberDiff line numberDiff line change
@@ -1055,8 +1055,8 @@ def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort015]> {
10551055
let NumMicroOps = 2;
10561056
let ResourceCycles = [1,1];
10571057
}
1058-
def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1059-
"MMX_CVT(T?)PS2PIirr",
1058+
def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
1059+
"MMX_CVT(T?)PS2PIrr",
10601060
"VCVTDQ2PDZ128rr",
10611061
"VCVTPD2DQZ128rr",
10621062
"(V?)CVT(T?)PD2DQrr",
@@ -1162,7 +1162,7 @@ def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> {
11621162
let NumMicroOps = 2;
11631163
let ResourceCycles = [2];
11641164
}
1165-
def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1165+
def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
11661166
def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
11671167
"VCOMPRESSPS(Z|Z128|Z256)rr",
11681168
"VPCOMPRESSD(Z|Z128|Z256)rr",
@@ -1683,7 +1683,7 @@ def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> {
16831683
let NumMicroOps = 2;
16841684
let ResourceCycles = [1,1];
16851685
}
1686-
def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1686+
def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
16871687

16881688
def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> {
16891689
let Latency = 9;
@@ -1741,7 +1741,7 @@ def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort015]> {
17411741
let NumMicroOps = 2;
17421742
let ResourceCycles = [1,1];
17431743
}
1744-
def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1744+
def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
17451745
"(V?)CVTPS2PDrm")>;
17461746

17471747
def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> {
@@ -1938,8 +1938,8 @@ def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
19381938
def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2PSrm,
19391939
CVTPD2DQrm,
19401940
CVTTPD2DQrm,
1941-
MMX_CVTPD2PIirm,
1942-
MMX_CVTTPD2PIirm)>;
1941+
MMX_CVTPD2PIrm,
1942+
MMX_CVTTPD2PIrm)>;
19431943

19441944
def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> {
19451945
let Latency = 11;

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

+9-9
Original file line numberDiff line numberDiff line change
@@ -927,7 +927,7 @@ def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
927927
let NumMicroOps = 2;
928928
let ResourceCycles = [1,1];
929929
}
930-
def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr,
930+
def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDrr,
931931
CVTDQ2PDrr,
932932
VCVTDQ2PDrr)>;
933933

@@ -936,8 +936,8 @@ def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
936936
let NumMicroOps = 2;
937937
let ResourceCycles = [1,1];
938938
}
939-
def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
940-
"MMX_CVT(T?)PS2PIirr",
939+
def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIrr",
940+
"MMX_CVT(T?)PS2PIrr",
941941
"(V?)CVT(T?)PD2DQrr",
942942
"(V?)CVTPD2PSrr",
943943
"(V?)CVTPS2PDrr",
@@ -984,7 +984,7 @@ def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
984984
let NumMicroOps = 2;
985985
let ResourceCycles = [2];
986986
}
987-
def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>;
987+
def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
988988

989989
def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
990990
let Latency = 6;
@@ -1283,7 +1283,7 @@ def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
12831283
let NumMicroOps = 2;
12841284
let ResourceCycles = [1,1];
12851285
}
1286-
def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>;
1286+
def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
12871287

12881288
def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
12891289
let Latency = 9;
@@ -1302,7 +1302,7 @@ def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
13021302
let NumMicroOps = 2;
13031303
let ResourceCycles = [1,1];
13041304
}
1305-
def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1305+
def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm",
13061306
"(V?)CVTPS2PDrm")>;
13071307

13081308
def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
@@ -1345,7 +1345,7 @@ def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
13451345
let NumMicroOps = 3;
13461346
let ResourceCycles = [1,1,1];
13471347
}
1348-
def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>;
1348+
def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
13491349

13501350
def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
13511351
let Latency = 10;
@@ -1425,8 +1425,8 @@ def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
14251425
def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm,
14261426
CVTPD2DQrm,
14271427
CVTTPD2DQrm,
1428-
MMX_CVTPD2PIirm,
1429-
MMX_CVTTPD2PIirm)>;
1428+
MMX_CVTPD2PIrm,
1429+
MMX_CVTTPD2PIrm)>;
14301430

14311431
def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
14321432
let Latency = 11;

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

+7-7
Original file line numberDiff line numberDiff line change
@@ -1047,8 +1047,8 @@ def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
10471047
let NumMicroOps = 2;
10481048
let ResourceCycles = [1,1];
10491049
}
1050-
def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1051-
"MMX_CVT(T?)PS2PIirr",
1050+
def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr",
1051+
"MMX_CVT(T?)PS2PIrr",
10521052
"VCVTDQ2PDZ128rr",
10531053
"VCVTPD2DQZ128rr",
10541054
"(V?)CVT(T?)PD2DQrr",
@@ -1154,7 +1154,7 @@ def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
11541154
let NumMicroOps = 2;
11551155
let ResourceCycles = [2];
11561156
}
1157-
def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>;
1157+
def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>;
11581158
def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr",
11591159
"VCOMPRESSPS(Z|Z128|Z256)rr",
11601160
"VPCOMPRESSD(Z|Z128|Z256)rr",
@@ -1675,7 +1675,7 @@ def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
16751675
let NumMicroOps = 2;
16761676
let ResourceCycles = [1,1];
16771677
}
1678-
def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>;
1678+
def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>;
16791679

16801680
def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
16811681
let Latency = 9;
@@ -1733,7 +1733,7 @@ def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
17331733
let NumMicroOps = 2;
17341734
let ResourceCycles = [1,1];
17351735
}
1736-
def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1736+
def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm",
17371737
"(V?)CVTPS2PDrm")>;
17381738

17391739
def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
@@ -1930,8 +1930,8 @@ def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
19301930
def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm,
19311931
CVTPD2DQrm,
19321932
CVTTPD2DQrm,
1933-
MMX_CVTPD2PIirm,
1934-
MMX_CVTTPD2PIirm)>;
1933+
MMX_CVTPD2PIrm,
1934+
MMX_CVTTPD2PIrm)>;
19351935

19361936
def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
19371937
let Latency = 11;

‎llvm/lib/Target/X86/X86ScheduleAtom.td

+3-3
Original file line numberDiff line numberDiff line change
@@ -525,8 +525,8 @@ def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
525525
let Latency = 5;
526526
let ResourceCycles = [5];
527527
}
528-
def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
529-
MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>;
528+
def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
529+
MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>;
530530

531531
// Port0 and Port1
532532
def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
@@ -547,7 +547,7 @@ def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
547547
let Latency = 5;
548548
let ResourceCycles = [5, 5];
549549
}
550-
def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
550+
def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>;
551551
def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
552552

553553
// Port0 or Port1

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